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linux_dsm_epyc7002/drivers/soc/xilinx/Kconfig

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soc: xilinx: Create folder structure for soc specific drivers Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-19 20:15:25 +07:00
# SPDX-License-Identifier: GPL-2.0
menu "Xilinx SoC drivers"
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-22 01:33:06 +07:00
config XILINX_VCU
soc: xilinx: Fix Kconfig alignment Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16 14:36:09 +07:00
tristate "Xilinx VCU logicoreIP Init"
soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu xlnx_vcu driver uses devm_ioremap_nocache, which is included only when HAS_IOMEM is enabled. drivers/soc/xilinx/xlnx_vcu.o: In function `xvcu_probe': xlnx_vcu.c:(.text+0x116): undefined reference to `devm_ioremap_nocache' xlnx_vcu.c:(.text+0x1ae): undefined reference to `devm_ioremap_nocache' Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16 13:34:48 +07:00
depends on HAS_IOMEM
soc: xilinx: Fix Kconfig alignment Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16 14:36:09 +07:00
help
Provides the driver to enable and disable the isolation between the
processing system and programmable logic part by using the logicoreIP
register set. This driver also configures the frequency based on the
clock information from the logicoreIP register set.
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-22 01:33:06 +07:00
soc: xilinx: Fix Kconfig alignment Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16 14:36:09 +07:00
If you say yes here you get support for the logicoreIP.
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-22 01:33:06 +07:00
soc: xilinx: Fix Kconfig alignment Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16 14:36:09 +07:00
If unsure, say N.
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-22 01:33:06 +07:00
soc: xilinx: Fix Kconfig alignment Tabs should be used for alignment instead of spaces. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-16 14:36:09 +07:00
To compile this driver as a module, choose M here: the
module will be called xlnx_vcu.
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-22 01:33:06 +07:00
drivers: soc: xilinx: Add ZynqMP PM driver Add ZynqMP PM driver. PM driver provides power management support for ZynqMP. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-30 03:38:21 +07:00
config ZYNQMP_POWER
bool "Enable Xilinx Zynq MPSoC Power Management driver"
depends on PM && ARCH_ZYNQMP
default y
help
Say yes to enable power management support for ZyqnMP SoC.
This driver uses firmware driver as an interface for power
management request to firmware. It registers isr to handle
power management callbacks from firmware.
If in doubt, say N.
drivers: soc: xilinx: Add ZynqMP power domain driver The zynqmp-genpd driver communicates the usage requirements for logical power domains / devices to the platform FW. FW is responsible for choosing appropriate power states, taking Linux' usage information into account. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-02 05:08:50 +07:00
config ZYNQMP_PM_DOMAINS
bool "Enable Zynq MPSoC generic PM domains"
default y
depends on PM && ARCH_ZYNQMP && ZYNQMP_FIRMWARE
select PM_GENERIC_DOMAINS
help
Say yes to enable device power management through PM domains
If in doubt, say N.
soc: xilinx: Create folder structure for soc specific drivers Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-19 20:15:25 +07:00
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