2005-04-17 05:20:36 +07:00
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/*
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* arch/arm/mach-pxa/time.c
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*
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2007-07-21 09:39:36 +07:00
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* PXA clocksource, clockevents, and OST interrupt handlers.
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* Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
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*
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* Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
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* by MontaVista Software, Inc. (Nico, your code rocks!)
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2005-04-17 05:20:36 +07:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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2007-07-21 09:39:36 +07:00
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#include <linux/clockchips.h>
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2007-08-17 22:55:22 +07:00
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#include <asm/div64.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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2010-12-16 04:48:15 +07:00
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#include <asm/sched_clock.h>
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2009-01-20 10:04:16 +07:00
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#include <mach/regs-ost.h>
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2012-01-04 05:53:48 +07:00
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#include <mach/irqs.h>
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2005-04-17 05:20:36 +07:00
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2007-08-17 22:55:22 +07:00
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/*
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* This is PXA's sched_clock implementation. This has a resolution
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* of at least 308 ns and a maximum value of 208 days.
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*
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* The return value is guaranteed to be monotonic in that range as
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* long as there is always less than 582 seconds between successive
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* calls to sched_clock() which should always be the case in practice.
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*/
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2011-12-15 18:19:23 +07:00
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static u32 notrace pxa_read_sched_clock(void)
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2007-08-17 22:55:22 +07:00
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{
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2012-06-06 17:42:36 +07:00
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return readl_relaxed(OSCR);
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2007-08-17 22:55:22 +07:00
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}
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2007-11-13 05:45:16 +07:00
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#define MIN_OSCR_DELTA 16
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2005-04-17 05:20:36 +07:00
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static irqreturn_t
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2007-07-21 09:39:36 +07:00
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pxa_ost0_interrupt(int irq, void *dev_id)
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2005-04-17 05:20:36 +07:00
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{
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2007-07-21 09:39:36 +07:00
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struct clock_event_device *c = dev_id;
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2007-11-13 05:45:16 +07:00
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/* Disarm the compare/match, signal the event. */
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2012-06-06 17:42:36 +07:00
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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2007-11-13 05:45:16 +07:00
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c->event_handler(c);
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2005-04-17 05:20:36 +07:00
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return IRQ_HANDLED;
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}
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2007-07-21 09:39:36 +07:00
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static int
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pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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2009-12-17 18:43:29 +07:00
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unsigned long next, oscr;
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2007-07-21 09:39:36 +07:00
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2012-06-06 17:42:36 +07:00
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writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
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next = readl_relaxed(OSCR) + delta;
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writel_relaxed(next, OSMR0);
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oscr = readl_relaxed(OSCR);
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2007-11-09 06:35:46 +07:00
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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2007-07-21 09:39:36 +07:00
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}
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static void
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pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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2012-06-06 17:42:36 +07:00
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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2007-07-21 09:39:36 +07:00
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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/* initializing, released, or preparing for suspend */
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2012-06-06 17:42:36 +07:00
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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2007-07-21 09:39:36 +07:00
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break;
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2007-10-27 21:15:49 +07:00
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case CLOCK_EVT_MODE_RESUME:
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2007-11-13 05:45:16 +07:00
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case CLOCK_EVT_MODE_PERIODIC:
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2007-10-27 21:15:49 +07:00
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break;
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2007-07-21 09:39:36 +07:00
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}
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}
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2012-11-08 06:34:13 +07:00
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#ifdef CONFIG_PM
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static unsigned long osmr[4], oier, oscr;
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static void pxa_timer_suspend(struct clock_event_device *cedev)
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{
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osmr[0] = readl_relaxed(OSMR0);
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osmr[1] = readl_relaxed(OSMR1);
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osmr[2] = readl_relaxed(OSMR2);
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osmr[3] = readl_relaxed(OSMR3);
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oier = readl_relaxed(OIER);
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oscr = readl_relaxed(OSCR);
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}
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static void pxa_timer_resume(struct clock_event_device *cedev)
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{
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/*
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* Ensure that we have at least MIN_OSCR_DELTA between match
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* register 0 and the OSCR, to guarantee that we will receive
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* the one-shot timer interrupt. We adjust OSMR0 in preference
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* to OSCR to guarantee that OSCR is monotonically incrementing.
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*/
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if (osmr[0] - oscr < MIN_OSCR_DELTA)
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osmr[0] += MIN_OSCR_DELTA;
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writel_relaxed(osmr[0], OSMR0);
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writel_relaxed(osmr[1], OSMR1);
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writel_relaxed(osmr[2], OSMR2);
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writel_relaxed(osmr[3], OSMR3);
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writel_relaxed(oier, OIER);
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writel_relaxed(oscr, OSCR);
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}
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#else
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#define pxa_timer_suspend NULL
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#define pxa_timer_resume NULL
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#endif
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2007-07-21 09:39:36 +07:00
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static struct clock_event_device ckevt_pxa_osmr0 = {
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.name = "osmr0",
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2007-11-13 05:45:16 +07:00
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.features = CLOCK_EVT_FEAT_ONESHOT,
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2007-07-21 09:39:36 +07:00
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.rating = 200,
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.set_next_event = pxa_osmr0_set_next_event,
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.set_mode = pxa_osmr0_set_mode,
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2012-11-08 06:34:13 +07:00
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.suspend = pxa_timer_suspend,
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.resume = pxa_timer_resume,
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2005-04-17 05:20:36 +07:00
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};
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2007-07-21 09:39:36 +07:00
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static struct irqaction pxa_ost0_irq = {
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.name = "ost0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = pxa_ost0_interrupt,
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.dev_id = &ckevt_pxa_osmr0,
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};
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2012-11-09 02:40:59 +07:00
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void __init pxa_timer_init(void)
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2005-04-17 05:20:36 +07:00
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{
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2008-12-18 10:10:32 +07:00
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unsigned long clock_tick_rate = get_clock_tick_rate();
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2007-09-02 03:12:50 +07:00
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2012-06-06 17:42:36 +07:00
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writel_relaxed(0, OIER);
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writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
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2005-04-17 05:20:36 +07:00
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2011-12-15 18:19:23 +07:00
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setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
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2007-08-17 22:55:22 +07:00
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2008-12-13 17:50:26 +07:00
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ckevt_pxa_osmr0.cpumask = cpumask_of(0);
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2005-04-17 05:20:36 +07:00
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2007-07-21 09:39:36 +07:00
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setup_irq(IRQ_OST0, &pxa_ost0_irq);
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2005-09-01 18:48:40 +07:00
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2012-06-06 17:42:36 +07:00
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clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
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2011-05-08 20:09:47 +07:00
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clocksource_mmio_readl_up);
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2013-01-15 01:20:02 +07:00
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clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
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MIN_OSCR_DELTA * 2, 0x7fffffff);
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2005-09-01 18:48:40 +07:00
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}
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