2019-06-04 15:11:33 +07:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2006-01-10 00:05:41 +07:00
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/*
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* Copyright (C) 2003-2005 SAN People
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*
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* Debugging macro include header
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*/
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2015-01-13 01:42:14 +07:00
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#define AT91_DBGU_SR (0x14) /* Status Register */
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#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
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#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
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2011-09-01 09:55:46 +07:00
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.macro addruart, rp, rv, tmp
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2015-08-08 17:11:11 +07:00
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ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
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2016-06-07 22:24:39 +07:00
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ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
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2006-01-10 00:05:41 +07:00
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.endm
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.macro senduart,rd,rx
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2011-05-03 00:11:25 +07:00
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strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
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2006-01-10 00:05:41 +07:00
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.endm
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.macro waituart,rd,rx
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2011-05-03 00:11:25 +07:00
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1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
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tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
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2006-01-10 00:05:41 +07:00
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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2011-05-03 00:11:25 +07:00
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1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
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tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
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2006-01-10 00:05:41 +07:00
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beq 1001b
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.endm
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