2006-05-24 07:18:44 +07:00
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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2012-03-07 05:34:26 +07:00
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#ifndef LINUX_DMAENGINE_H
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#define LINUX_DMAENGINE_H
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2006-06-27 16:53:56 +07:00
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2006-05-24 07:18:44 +07:00
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#include <linux/device.h>
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dma: add channel request API that supports deferred probe
dma_request_slave_channel() simply returns NULL whenever DMA channel
lookup fails. Lookup could fail for two distinct reasons:
a) No DMA specification exists for the channel name.
This includes situations where no DMA specifications exist at all, or
other general lookup problems.
b) A DMA specification does exist, yet the driver for that channel is not
yet registered.
Case (b) should trigger deferred probe in client drivers. However, since
they have no way to differentiate the two situations, it cannot.
Implement new function dma_request_slave_channel_reason(), which performs
identically to dma_request_slave_channel(), except that it returns an
error-pointer rather than NULL, which allows callers to detect when
deferred probe should occur.
Eventually, all drivers should be converted to this new API, the old API
removed, and the new API renamed to the more desirable name. This patch
doesn't convert the existing API and all drivers in one go, since some
drivers call dma_request_slave_channel() then dma_request_channel() if
that fails. That would require either modifying dma_request_channel() in
the same way, or adding extra error-handling code to all affected
drivers, and there are close to 100 drivers using the other API, rather
than just the 15-20 or so that use dma_request_slave_channel(), which
might be tenable in a single patch.
acpi_dma_request_slave_chan_by_name() doesn't currently implement
deferred probe. It should, but this will be addressed later.
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-11-27 00:04:22 +07:00
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#include <linux/err.h>
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2006-05-24 07:18:44 +07:00
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#include <linux/uio.h>
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2011-11-24 08:12:59 +07:00
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#include <linux/bug.h>
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2011-07-25 21:27:52 +07:00
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#include <linux/scatterlist.h>
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2011-07-29 13:55:11 +07:00
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#include <linux/bitmap.h>
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2012-02-01 17:42:18 +07:00
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#include <linux/types.h>
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2011-07-29 13:55:11 +07:00
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#include <asm/page.h>
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2011-06-16 18:01:34 +07:00
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2006-05-24 07:18:44 +07:00
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/**
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2006-07-04 09:44:51 +07:00
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* typedef dma_cookie_t - an opaque DMA cookie
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2006-05-24 07:18:44 +07:00
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*
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* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
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*/
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typedef s32 dma_cookie_t;
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2010-03-01 12:18:16 +07:00
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#define DMA_MIN_COOKIE 1
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2006-05-24 07:18:44 +07:00
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2013-08-10 14:46:50 +07:00
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static inline int dma_submit_error(dma_cookie_t cookie)
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{
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return cookie < 0 ? cookie : 0;
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}
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2006-05-24 07:18:44 +07:00
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/**
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* enum dma_status - DMA transaction status
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2013-10-16 14:59:02 +07:00
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* @DMA_COMPLETE: transaction completed
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2006-05-24 07:18:44 +07:00
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* @DMA_IN_PROGRESS: transaction not yet processed
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2010-03-27 06:50:49 +07:00
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* @DMA_PAUSED: transaction is paused
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2006-05-24 07:18:44 +07:00
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* @DMA_ERROR: transaction failed
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*/
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enum dma_status {
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2013-10-17 08:59:57 +07:00
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DMA_COMPLETE,
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2006-05-24 07:18:44 +07:00
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DMA_IN_PROGRESS,
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2010-03-27 06:50:49 +07:00
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DMA_PAUSED,
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2006-05-24 07:18:44 +07:00
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DMA_ERROR,
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};
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
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/**
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* enum dma_transaction_type - DMA transaction types/indexes
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2009-09-09 07:42:51 +07:00
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*
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* Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
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* automatically set as dma devices are registered.
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
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*/
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enum dma_transaction_type {
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DMA_MEMCPY,
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DMA_XOR,
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async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
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DMA_PQ,
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2009-04-09 04:28:37 +07:00
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DMA_XOR_VAL,
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DMA_PQ_VAL,
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
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DMA_INTERRUPT,
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2010-09-30 18:46:44 +07:00
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DMA_SG,
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2009-01-07 01:38:15 +07:00
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DMA_PRIVATE,
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2009-09-09 07:42:51 +07:00
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DMA_ASYNC_TX,
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-09 01:59:35 +07:00
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DMA_SLAVE,
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2010-09-30 20:56:32 +07:00
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DMA_CYCLIC,
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2011-10-13 14:03:30 +07:00
|
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DMA_INTERLEAVE,
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
/* last transaction type for creation of the capabilities mask */
|
2011-10-13 14:03:30 +07:00
|
|
|
DMA_TX_TYPE_END,
|
|
|
|
};
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-09 01:59:35 +07:00
|
|
|
|
2011-10-13 16:45:27 +07:00
|
|
|
/**
|
|
|
|
* enum dma_transfer_direction - dma transfer mode and direction indicator
|
|
|
|
* @DMA_MEM_TO_MEM: Async/Memcpy mode
|
|
|
|
* @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
|
|
|
|
* @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
|
|
|
|
* @DMA_DEV_TO_DEV: Slave mode & From Device to Device
|
|
|
|
*/
|
|
|
|
enum dma_transfer_direction {
|
|
|
|
DMA_MEM_TO_MEM,
|
|
|
|
DMA_MEM_TO_DEV,
|
|
|
|
DMA_DEV_TO_MEM,
|
|
|
|
DMA_DEV_TO_DEV,
|
2011-12-13 22:48:03 +07:00
|
|
|
DMA_TRANS_NONE,
|
2011-10-13 16:45:27 +07:00
|
|
|
};
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
|
2011-10-13 14:03:30 +07:00
|
|
|
/**
|
|
|
|
* Interleaved Transfer Request
|
|
|
|
* ----------------------------
|
|
|
|
* A chunk is collection of contiguous bytes to be transfered.
|
|
|
|
* The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
|
|
|
|
* ICGs may or maynot change between chunks.
|
|
|
|
* A FRAME is the smallest series of contiguous {chunk,icg} pairs,
|
|
|
|
* that when repeated an integral number of times, specifies the transfer.
|
|
|
|
* A transfer template is specification of a Frame, the number of times
|
|
|
|
* it is to be repeated and other per-transfer attributes.
|
|
|
|
*
|
|
|
|
* Practically, a client driver would have ready a template for each
|
|
|
|
* type of transfer it is going to need during its lifetime and
|
|
|
|
* set only 'src_start' and 'dst_start' before submitting the requests.
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* | Frame-1 | Frame-2 | ~ | Frame-'numf' |
|
|
|
|
* |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
|
|
|
|
*
|
|
|
|
* == Chunk size
|
|
|
|
* ... ICG
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct data_chunk - Element of scatter-gather list that makes a frame.
|
|
|
|
* @size: Number of bytes to read from source.
|
|
|
|
* size_dst := fn(op, size_src), so doesn't mean much for destination.
|
|
|
|
* @icg: Number of bytes to jump after last src/dst address of this
|
|
|
|
* chunk and before first src/dst address for next chunk.
|
|
|
|
* Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
|
|
|
|
* Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
|
|
|
|
*/
|
|
|
|
struct data_chunk {
|
|
|
|
size_t size;
|
|
|
|
size_t icg;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dma_interleaved_template - Template to convey DMAC the transfer pattern
|
|
|
|
* and attributes.
|
|
|
|
* @src_start: Bus address of source for the first chunk.
|
|
|
|
* @dst_start: Bus address of destination for the first chunk.
|
|
|
|
* @dir: Specifies the type of Source and Destination.
|
|
|
|
* @src_inc: If the source address increments after reading from it.
|
|
|
|
* @dst_inc: If the destination address increments after writing to it.
|
|
|
|
* @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
|
|
|
|
* Otherwise, source is read contiguously (icg ignored).
|
|
|
|
* Ignored if src_inc is false.
|
|
|
|
* @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
|
|
|
|
* Otherwise, destination is filled contiguously (icg ignored).
|
|
|
|
* Ignored if dst_inc is false.
|
|
|
|
* @numf: Number of frames in this template.
|
|
|
|
* @frame_size: Number of chunks in a frame i.e, size of sgl[].
|
|
|
|
* @sgl: Array of {chunk,icg} pairs that make up a frame.
|
|
|
|
*/
|
|
|
|
struct dma_interleaved_template {
|
|
|
|
dma_addr_t src_start;
|
|
|
|
dma_addr_t dst_start;
|
|
|
|
enum dma_transfer_direction dir;
|
|
|
|
bool src_inc;
|
|
|
|
bool dst_inc;
|
|
|
|
bool src_sgl;
|
|
|
|
bool dst_sgl;
|
|
|
|
size_t numf;
|
|
|
|
size_t frame_size;
|
|
|
|
struct data_chunk sgl[0];
|
|
|
|
};
|
|
|
|
|
2008-02-03 09:49:58 +07:00
|
|
|
/**
|
2008-04-18 10:17:26 +07:00
|
|
|
* enum dma_ctrl_flags - DMA flags to augment operation preparation,
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
* control completion, and communicate status.
|
2008-02-03 09:49:58 +07:00
|
|
|
* @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
* this transaction
|
2009-12-11 00:35:15 +07:00
|
|
|
* @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
* acknowledges receipt, i.e. has has a chance to establish any dependency
|
|
|
|
* chains
|
|
|
|
* @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
|
|
|
|
* @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
|
|
|
|
* @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
|
|
|
|
* sources that were the result of a previous operation, in the case of a PQ
|
|
|
|
* operation it continues the calculation with new sources
|
2009-09-09 07:42:50 +07:00
|
|
|
* @DMA_PREP_FENCE - tell the driver that subsequent operations depend
|
|
|
|
* on the result of this operation
|
2008-02-03 09:49:58 +07:00
|
|
|
*/
|
2008-04-18 10:17:26 +07:00
|
|
|
enum dma_ctrl_flags {
|
2008-02-03 09:49:58 +07:00
|
|
|
DMA_PREP_INTERRUPT = (1 << 0),
|
2008-04-18 10:17:26 +07:00
|
|
|
DMA_CTRL_ACK = (1 << 1),
|
2013-10-19 00:35:33 +07:00
|
|
|
DMA_PREP_PQ_DISABLE_P = (1 << 2),
|
|
|
|
DMA_PREP_PQ_DISABLE_Q = (1 << 3),
|
|
|
|
DMA_PREP_CONTINUE = (1 << 4),
|
|
|
|
DMA_PREP_FENCE = (1 << 5),
|
2008-02-03 09:49:58 +07:00
|
|
|
};
|
|
|
|
|
2010-03-27 06:44:01 +07:00
|
|
|
/**
|
|
|
|
* enum dma_ctrl_cmd - DMA operations that can optionally be exercised
|
|
|
|
* on a running channel.
|
|
|
|
* @DMA_TERMINATE_ALL: terminate all ongoing transfers
|
|
|
|
* @DMA_PAUSE: pause ongoing transfers
|
|
|
|
* @DMA_RESUME: resume paused transfer
|
2010-08-04 18:37:33 +07:00
|
|
|
* @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
|
|
|
|
* that need to runtime reconfigure the slave channels (as opposed to passing
|
|
|
|
* configuration data in statically from the platform). An additional
|
|
|
|
* argument of struct dma_slave_config must be passed in with this
|
|
|
|
* command.
|
2010-03-27 06:44:01 +07:00
|
|
|
*/
|
|
|
|
enum dma_ctrl_cmd {
|
|
|
|
DMA_TERMINATE_ALL,
|
|
|
|
DMA_PAUSE,
|
|
|
|
DMA_RESUME,
|
2010-08-04 18:37:33 +07:00
|
|
|
DMA_SLAVE_CONFIG,
|
2010-03-27 06:44:01 +07:00
|
|
|
};
|
|
|
|
|
2009-08-30 09:09:26 +07:00
|
|
|
/**
|
|
|
|
* enum sum_check_bits - bit position of pq_check_flags
|
|
|
|
*/
|
|
|
|
enum sum_check_bits {
|
|
|
|
SUM_CHECK_P = 0,
|
|
|
|
SUM_CHECK_Q = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
|
|
|
|
* @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
|
|
|
|
* @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
|
|
|
|
*/
|
|
|
|
enum sum_check_flags {
|
|
|
|
SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
|
|
|
|
SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
|
|
|
|
};
|
|
|
|
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
/**
|
|
|
|
* dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
|
|
|
|
* See linux/cpumask.h
|
|
|
|
*/
|
|
|
|
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
|
|
|
|
|
2006-05-24 07:18:44 +07:00
|
|
|
/**
|
|
|
|
* struct dma_chan_percpu - the per-CPU part of struct dma_chan
|
|
|
|
* @memcpy_count: transaction counter
|
|
|
|
* @bytes_transferred: byte counter
|
|
|
|
*/
|
|
|
|
|
|
|
|
struct dma_chan_percpu {
|
|
|
|
/* stats */
|
|
|
|
unsigned long memcpy_count;
|
|
|
|
unsigned long bytes_transferred;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dma_chan - devices supply DMA channels, clients use them
|
2006-07-04 09:44:51 +07:00
|
|
|
* @device: ptr to the dma device who supplies this channel, always !%NULL
|
2006-05-24 07:18:44 +07:00
|
|
|
* @cookie: last cookie value returned to client
|
2012-03-07 05:34:06 +07:00
|
|
|
* @completed_cookie: last completed cookie for this channel
|
2006-07-04 09:44:51 +07:00
|
|
|
* @chan_id: channel ID for sysfs
|
2009-01-07 01:38:21 +07:00
|
|
|
* @dev: class device for sysfs
|
2006-05-24 07:18:44 +07:00
|
|
|
* @device_node: used to add this to the device chan list
|
|
|
|
* @local: per-cpu pointer to a struct dma_chan_percpu
|
2013-12-18 23:09:39 +07:00
|
|
|
* @client_count: how many clients are using this channel
|
2009-01-07 01:38:14 +07:00
|
|
|
* @table_count: number of appearances in the mem-to-mem allocation table
|
2009-02-19 05:48:26 +07:00
|
|
|
* @private: private data for certain client-channel associations
|
2006-05-24 07:18:44 +07:00
|
|
|
*/
|
|
|
|
struct dma_chan {
|
|
|
|
struct dma_device *device;
|
|
|
|
dma_cookie_t cookie;
|
2012-03-07 05:34:06 +07:00
|
|
|
dma_cookie_t completed_cookie;
|
2006-05-24 07:18:44 +07:00
|
|
|
|
|
|
|
/* sysfs */
|
|
|
|
int chan_id;
|
2009-01-07 01:38:21 +07:00
|
|
|
struct dma_chan_dev *dev;
|
2006-05-24 07:18:44 +07:00
|
|
|
|
|
|
|
struct list_head device_node;
|
2010-02-02 12:39:15 +07:00
|
|
|
struct dma_chan_percpu __percpu *local;
|
2008-07-09 01:58:21 +07:00
|
|
|
int client_count;
|
2009-01-07 01:38:14 +07:00
|
|
|
int table_count;
|
2009-02-19 05:48:26 +07:00
|
|
|
void *private;
|
2006-05-24 07:18:44 +07:00
|
|
|
};
|
|
|
|
|
2009-01-07 01:38:21 +07:00
|
|
|
/**
|
|
|
|
* struct dma_chan_dev - relate sysfs device node to backing channel device
|
2013-12-18 23:09:39 +07:00
|
|
|
* @chan: driver channel device
|
|
|
|
* @device: sysfs device
|
|
|
|
* @dev_id: parent dma_device dev_id
|
|
|
|
* @idr_ref: reference count to gate release of dma_device dev_id
|
2009-01-07 01:38:21 +07:00
|
|
|
*/
|
|
|
|
struct dma_chan_dev {
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct device device;
|
2009-01-07 01:38:21 +07:00
|
|
|
int dev_id;
|
|
|
|
atomic_t *idr_ref;
|
2009-01-07 01:38:21 +07:00
|
|
|
};
|
|
|
|
|
2010-08-04 18:37:33 +07:00
|
|
|
/**
|
2014-05-15 21:15:31 +07:00
|
|
|
* enum dma_slave_buswidth - defines bus width of the DMA slave
|
2010-08-04 18:37:33 +07:00
|
|
|
* device, source or target buses
|
|
|
|
*/
|
|
|
|
enum dma_slave_buswidth {
|
|
|
|
DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
|
|
|
|
DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
|
|
|
|
DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
|
2014-07-03 11:51:52 +07:00
|
|
|
DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
|
2010-08-04 18:37:33 +07:00
|
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
|
|
|
|
DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dma_slave_config - dma slave channel runtime config
|
|
|
|
* @direction: whether the data shall go in or out on this slave
|
2013-12-16 15:12:17 +07:00
|
|
|
* channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
|
2014-08-21 00:20:53 +07:00
|
|
|
* legal values. DEPRECATED, drivers should use the direction argument
|
|
|
|
* to the device_prep_slave_sg and device_prep_dma_cyclic functions or
|
|
|
|
* the dir field in the dma_interleaved_template structure.
|
2010-08-04 18:37:33 +07:00
|
|
|
* @src_addr: this is the physical address where DMA slave data
|
|
|
|
* should be read (RX), if the source is memory this argument is
|
|
|
|
* ignored.
|
|
|
|
* @dst_addr: this is the physical address where DMA slave data
|
|
|
|
* should be written (TX), if the source is memory this argument
|
|
|
|
* is ignored.
|
|
|
|
* @src_addr_width: this is the width in bytes of the source (RX)
|
|
|
|
* register where DMA data shall be read. If the source
|
|
|
|
* is memory this may be ignored depending on architecture.
|
|
|
|
* Legal values: 1, 2, 4, 8.
|
|
|
|
* @dst_addr_width: same as src_addr_width but for destination
|
|
|
|
* target (TX) mutatis mutandis.
|
|
|
|
* @src_maxburst: the maximum number of words (note: words, as in
|
|
|
|
* units of the src_addr_width member, not bytes) that can be sent
|
|
|
|
* in one burst to the device. Typically something like half the
|
|
|
|
* FIFO depth on I/O peripherals so you don't overflow it. This
|
|
|
|
* may or may not be applicable on memory sources.
|
|
|
|
* @dst_maxburst: same as src_maxburst but for destination target
|
|
|
|
* mutatis mutandis.
|
2012-02-01 17:42:18 +07:00
|
|
|
* @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
|
|
|
|
* with 'true' if peripheral should be flow controller. Direction will be
|
|
|
|
* selected at Runtime.
|
2012-06-06 12:25:26 +07:00
|
|
|
* @slave_id: Slave requester id. Only valid for slave channels. The dma
|
|
|
|
* slave peripheral will have unique id as dma requester which need to be
|
|
|
|
* pass as slave config.
|
2010-08-04 18:37:33 +07:00
|
|
|
*
|
|
|
|
* This struct is passed in as configuration data to a DMA engine
|
|
|
|
* in order to set up a certain channel for DMA transport at runtime.
|
|
|
|
* The DMA device/engine has to provide support for an additional
|
|
|
|
* command in the channel config interface, DMA_SLAVE_CONFIG
|
|
|
|
* and this struct will then be passed in as an argument to the
|
|
|
|
* DMA engine device_control() function.
|
|
|
|
*
|
dma: Remove comment about embedding dma_slave_config into custom structs
The documentation for the dma_slave_config struct recommends that if a DMA
controller has special configuration options, which can not be configured
through the dma_slave_config struct, the driver should create its own custom
config struct and embed the dma_slave_config struct in it and pass the custom
config struct to dmaengine_slave_config(). This overloads the generic
dmaengine_slave_config() API with custom semantics and any caller of the
dmaengine_slave_config() that is not aware of these special semantics will cause
undefined behavior. This means that it is impossible for generic code to make
use of dmaengine_slave_config(). Such a restriction contradicts the very idea of
having a generic API.
E.g. consider the following case of a DMA controller that has an option to
reverse the field polarity of the DMA transfer with the following implementation
for setting the configuration:
struct my_slave_config {
struct dma_slave_config config;
unsigned int field_polarity;
};
static int my_dma_controller_slave_config(struct dma_chan *chan,
struct dma_slave_config *config)
{
struct my_slave_config *my_cfg = container_of(config,
struct my_slave_config, config);
...
my_dma_set_field_polarity(chan, my_cfg->field_polarity);
...
}
Now a generic user of the dmaengine API might want to configure a DMA channel
for this DMA controller that it obtained using the following code:
struct dma_slave_config config;
config.src_addr = ...;
...
dmaengine_slave_config(chan, &config);
The call to dmaengine_slave_config() will eventually call into
my_dma_controller_slave_config() which will cast from dma_slave_config to
my_slave_config and then tries to access the field_polarity member. Since the
dma_slave_config struct that was passed in was never embedded into a
my_slave_config struct this attempt will just read random stack garbage and use
that to configure the DMA controller. This is bad. Instead, if a DMA controller
really needs to have custom configuration options, the driver should create a
custom API for it. This makes it very clear that there is a direct dependency
of a user of such an API and the implementer. E.g.:
int my_dma_set_field_polarity(struct dma_chan *chan,
unsigned int field_polarity) {
if (chan->device->dev->driver != &my_dma_controller_driver.driver)
return -EINVAL;
...
}
EXPORT_SYMBOL_GPL(my_dma_set_field_polarity);
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-02-16 20:21:22 +07:00
|
|
|
* The rationale for adding configuration information to this struct is as
|
|
|
|
* follows: if it is likely that more than one DMA slave controllers in
|
|
|
|
* the world will support the configuration option, then make it generic.
|
|
|
|
* If not: if it is fixed so that it be sent in static from the platform
|
|
|
|
* data, then prefer to do that.
|
2010-08-04 18:37:33 +07:00
|
|
|
*/
|
|
|
|
struct dma_slave_config {
|
2011-10-13 16:45:27 +07:00
|
|
|
enum dma_transfer_direction direction;
|
2010-08-04 18:37:33 +07:00
|
|
|
dma_addr_t src_addr;
|
|
|
|
dma_addr_t dst_addr;
|
|
|
|
enum dma_slave_buswidth src_addr_width;
|
|
|
|
enum dma_slave_buswidth dst_addr_width;
|
|
|
|
u32 src_maxburst;
|
|
|
|
u32 dst_maxburst;
|
2012-02-01 17:42:18 +07:00
|
|
|
bool device_fc;
|
2012-06-06 12:25:26 +07:00
|
|
|
unsigned int slave_id;
|
2010-08-04 18:37:33 +07:00
|
|
|
};
|
|
|
|
|
2014-01-11 20:02:16 +07:00
|
|
|
/**
|
|
|
|
* enum dma_residue_granularity - Granularity of the reported transfer residue
|
|
|
|
* @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
|
|
|
|
* DMA channel is only able to tell whether a descriptor has been completed or
|
|
|
|
* not, which means residue reporting is not supported by this channel. The
|
|
|
|
* residue field of the dma_tx_state field will always be 0.
|
|
|
|
* @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
|
|
|
|
* completed segment of the transfer (For cyclic transfers this is after each
|
|
|
|
* period). This is typically implemented by having the hardware generate an
|
|
|
|
* interrupt after each transferred segment and then the drivers updates the
|
|
|
|
* outstanding residue by the size of the segment. Another possibility is if
|
|
|
|
* the hardware supports scatter-gather and the segment descriptor has a field
|
|
|
|
* which gets set after the segment has been completed. The driver then counts
|
|
|
|
* the number of segments without the flag set to compute the residue.
|
|
|
|
* @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
|
|
|
|
* burst. This is typically only supported if the hardware has a progress
|
|
|
|
* register of some sort (E.g. a register with the current read/write address
|
|
|
|
* or a register with the amount of bursts/beats/bytes that have been
|
|
|
|
* transferred or still need to be transferred).
|
|
|
|
*/
|
|
|
|
enum dma_residue_granularity {
|
|
|
|
DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
|
|
|
|
DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
|
|
|
|
DMA_RESIDUE_GRANULARITY_BURST = 2,
|
|
|
|
};
|
|
|
|
|
2013-07-08 15:45:25 +07:00
|
|
|
/* struct dma_slave_caps - expose capabilities of a slave channel only
|
|
|
|
*
|
|
|
|
* @src_addr_widths: bit mask of src addr widths the channel supports
|
|
|
|
* @dstn_addr_widths: bit mask of dstn addr widths the channel supports
|
|
|
|
* @directions: bit mask of slave direction the channel supported
|
|
|
|
* since the enum dma_transfer_direction is not defined as bits for each
|
|
|
|
* type of direction, the dma controller should fill (1 << <TYPE>) and same
|
|
|
|
* should be checked by controller as well
|
|
|
|
* @cmd_pause: true, if pause and thereby resume is supported
|
|
|
|
* @cmd_terminate: true, if terminate cmd is supported
|
2014-01-11 20:02:16 +07:00
|
|
|
* @residue_granularity: granularity of the reported transfer residue
|
2013-07-08 15:45:25 +07:00
|
|
|
*/
|
|
|
|
struct dma_slave_caps {
|
|
|
|
u32 src_addr_widths;
|
|
|
|
u32 dstn_addr_widths;
|
|
|
|
u32 directions;
|
|
|
|
bool cmd_pause;
|
|
|
|
bool cmd_terminate;
|
2014-01-11 20:02:16 +07:00
|
|
|
enum dma_residue_granularity residue_granularity;
|
2013-07-08 15:45:25 +07:00
|
|
|
};
|
|
|
|
|
2009-01-07 01:38:21 +07:00
|
|
|
static inline const char *dma_chan_name(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
return dev_name(&chan->dev->device);
|
|
|
|
}
|
2007-07-10 01:56:42 +07:00
|
|
|
|
2006-05-24 07:18:44 +07:00
|
|
|
void dma_chan_cleanup(struct kref *kref);
|
|
|
|
|
2009-01-07 01:38:15 +07:00
|
|
|
/**
|
|
|
|
* typedef dma_filter_fn - callback filter for dma_request_channel
|
|
|
|
* @chan: channel to be reviewed
|
|
|
|
* @filter_param: opaque parameter passed through dma_request_channel
|
|
|
|
*
|
|
|
|
* When this optional parameter is specified in a call to dma_request_channel a
|
|
|
|
* suitable channel is passed to this routine for further dispositioning before
|
|
|
|
* being returned. Where 'suitable' indicates a non-busy channel that
|
2009-01-07 01:38:19 +07:00
|
|
|
* satisfies the given capability mask. It returns 'true' to indicate that the
|
|
|
|
* channel is suitable.
|
2009-01-07 01:38:15 +07:00
|
|
|
*/
|
2009-01-07 01:38:19 +07:00
|
|
|
typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
|
2009-01-07 01:38:15 +07:00
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
typedef void (*dma_async_tx_callback)(void *dma_async_param);
|
2013-10-19 00:35:23 +07:00
|
|
|
|
|
|
|
struct dmaengine_unmap_data {
|
2014-05-22 04:02:37 +07:00
|
|
|
u8 map_cnt;
|
2013-10-19 00:35:23 +07:00
|
|
|
u8 to_cnt;
|
|
|
|
u8 from_cnt;
|
|
|
|
u8 bidi_cnt;
|
|
|
|
struct device *dev;
|
|
|
|
struct kref kref;
|
|
|
|
size_t len;
|
|
|
|
dma_addr_t addr[0];
|
|
|
|
};
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
/**
|
|
|
|
* struct dma_async_tx_descriptor - async transaction descriptor
|
|
|
|
* ---dma generic offload fields---
|
|
|
|
* @cookie: tracking cookie for this transaction, set to -EBUSY if
|
|
|
|
* this tx is sitting on a dependency list
|
2008-04-18 10:17:26 +07:00
|
|
|
* @flags: flags to augment operation preparation, control completion, and
|
|
|
|
* communicate status
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @phys: physical address of the descriptor
|
|
|
|
* @chan: target channel for this operation
|
|
|
|
* @tx_submit: set the prepared descriptor(s) to be executed by the engine
|
|
|
|
* @callback: routine to call after this operation is complete
|
|
|
|
* @callback_param: general parameter to pass to the callback routine
|
|
|
|
* ---async_tx api specific fields---
|
2008-04-18 10:17:25 +07:00
|
|
|
* @next: at completion submit this descriptor
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @parent: pointer to the next level up in the dependency chain
|
2008-04-18 10:17:25 +07:00
|
|
|
* @lock: protect the parent and next pointers
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
*/
|
|
|
|
struct dma_async_tx_descriptor {
|
|
|
|
dma_cookie_t cookie;
|
2008-04-18 10:17:26 +07:00
|
|
|
enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
dma_addr_t phys;
|
|
|
|
struct dma_chan *chan;
|
|
|
|
dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
|
|
|
|
dma_async_tx_callback callback;
|
|
|
|
void *callback_param;
|
2013-10-19 00:35:23 +07:00
|
|
|
struct dmaengine_unmap_data *unmap;
|
2010-10-08 06:44:50 +07:00
|
|
|
#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2008-04-18 10:17:25 +07:00
|
|
|
struct dma_async_tx_descriptor *next;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
struct dma_async_tx_descriptor *parent;
|
|
|
|
spinlock_t lock;
|
2010-05-18 06:24:16 +07:00
|
|
|
#endif
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
};
|
|
|
|
|
2013-10-19 00:35:25 +07:00
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
2013-10-19 00:35:23 +07:00
|
|
|
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
|
|
|
|
struct dmaengine_unmap_data *unmap)
|
|
|
|
{
|
|
|
|
kref_get(&unmap->kref);
|
|
|
|
tx->unmap = unmap;
|
|
|
|
}
|
|
|
|
|
2013-10-19 00:35:25 +07:00
|
|
|
struct dmaengine_unmap_data *
|
|
|
|
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
|
2013-10-19 00:35:24 +07:00
|
|
|
void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
|
2013-10-19 00:35:25 +07:00
|
|
|
#else
|
|
|
|
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
|
|
|
|
struct dmaengine_unmap_data *unmap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline struct dmaengine_unmap_data *
|
|
|
|
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2013-10-19 00:35:24 +07:00
|
|
|
|
2013-10-19 00:35:23 +07:00
|
|
|
static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
if (tx->unmap) {
|
2013-10-19 00:35:24 +07:00
|
|
|
dmaengine_unmap_put(tx->unmap);
|
2013-10-19 00:35:23 +07:00
|
|
|
tx->unmap = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-10-08 06:44:50 +07:00
|
|
|
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2010-05-18 06:24:16 +07:00
|
|
|
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
|
|
|
|
{
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
spin_lock_bh(&txd->lock);
|
|
|
|
}
|
|
|
|
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
spin_unlock_bh(&txd->lock);
|
|
|
|
}
|
|
|
|
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
|
|
|
|
{
|
|
|
|
txd->next = next;
|
|
|
|
next->parent = txd;
|
|
|
|
}
|
|
|
|
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
txd->parent = NULL;
|
|
|
|
}
|
|
|
|
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
txd->next = NULL;
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return txd->parent;
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return txd->next;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-03-27 06:50:49 +07:00
|
|
|
/**
|
|
|
|
* struct dma_tx_state - filled in to report the status of
|
|
|
|
* a transfer.
|
|
|
|
* @last: last completed DMA cookie
|
|
|
|
* @used: last issued DMA cookie (i.e. the one in progress)
|
|
|
|
* @residue: the remaining number of bytes left to transmit
|
|
|
|
* on the selected transfer for states DMA_IN_PROGRESS and
|
|
|
|
* DMA_PAUSED if this is implemented in the driver, else 0
|
|
|
|
*/
|
|
|
|
struct dma_tx_state {
|
|
|
|
dma_cookie_t last;
|
|
|
|
dma_cookie_t used;
|
|
|
|
u32 residue;
|
|
|
|
};
|
|
|
|
|
2006-05-24 07:18:44 +07:00
|
|
|
/**
|
|
|
|
* struct dma_device - info on the entity supplying DMA services
|
|
|
|
* @chancnt: how many DMA channels are supported
|
2009-03-06 18:07:14 +07:00
|
|
|
* @privatecnt: how many DMA channels are requested by dma_request_channel
|
2006-05-24 07:18:44 +07:00
|
|
|
* @channels: the list of struct dma_chan
|
|
|
|
* @global_node: list_head for global dma_device_list
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @cap_mask: one or more dma_capability flags
|
|
|
|
* @max_xor: maximum number of xor sources, 0 if no capability
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
* @max_pq: maximum number of PQ sources and PQ-continue capability
|
2009-09-09 07:42:53 +07:00
|
|
|
* @copy_align: alignment shift for memcpy operations
|
|
|
|
* @xor_align: alignment shift for xor operations
|
|
|
|
* @pq_align: alignment shift for pq operations
|
|
|
|
* @fill_align: alignment shift for memset operations
|
2006-07-04 09:44:51 +07:00
|
|
|
* @dev_id: unique device ID
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @dev: struct device reference for dma mapping api
|
2006-07-04 09:44:51 +07:00
|
|
|
* @device_alloc_chan_resources: allocate resources and return the
|
|
|
|
* number of allocated descriptors
|
|
|
|
* @device_free_chan_resources: release DMA channel's resources
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @device_prep_dma_memcpy: prepares a memcpy operation
|
|
|
|
* @device_prep_dma_xor: prepares a xor operation
|
2009-04-09 04:28:37 +07:00
|
|
|
* @device_prep_dma_xor_val: prepares a xor validation operation
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
* @device_prep_dma_pq: prepares a pq operation
|
|
|
|
* @device_prep_dma_pq_val: prepares a pqzero_sum operation
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-09 01:59:35 +07:00
|
|
|
* @device_prep_slave_sg: prepares a slave dma operation
|
2010-09-30 20:56:32 +07:00
|
|
|
* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
|
|
|
|
* The function takes a buffer of size buf_len. The callback function will
|
|
|
|
* be called after period_len bytes have been transferred.
|
2011-10-13 14:03:30 +07:00
|
|
|
* @device_prep_interleaved_dma: Transfer expression in a generic way.
|
2010-03-27 06:44:01 +07:00
|
|
|
* @device_control: manipulate all pending operations on a channel, returns
|
|
|
|
* zero or error code
|
2010-03-27 06:50:49 +07:00
|
|
|
* @device_tx_status: poll for transaction completion, the optional
|
|
|
|
* txstate parameter can be supplied with a pointer to get a
|
2011-03-31 08:57:33 +07:00
|
|
|
* struct with auxiliary transfer status information, otherwise the call
|
2010-03-27 06:50:49 +07:00
|
|
|
* will just return a simple status code
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* @device_issue_pending: push pending transactions to hardware
|
2013-07-08 15:45:25 +07:00
|
|
|
* @device_slave_caps: return the slave channel capabilities
|
2006-05-24 07:18:44 +07:00
|
|
|
*/
|
|
|
|
struct dma_device {
|
|
|
|
|
|
|
|
unsigned int chancnt;
|
2009-03-06 18:07:14 +07:00
|
|
|
unsigned int privatecnt;
|
2006-05-24 07:18:44 +07:00
|
|
|
struct list_head channels;
|
|
|
|
struct list_head global_node;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
dma_cap_mask_t cap_mask;
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
unsigned short max_xor;
|
|
|
|
unsigned short max_pq;
|
2009-09-09 07:42:53 +07:00
|
|
|
u8 copy_align;
|
|
|
|
u8 xor_align;
|
|
|
|
u8 pq_align;
|
|
|
|
u8 fill_align;
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
#define DMA_HAS_PQ_CONTINUE (1 << 15)
|
2006-05-24 07:18:44 +07:00
|
|
|
|
|
|
|
int dev_id;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
struct device *dev;
|
2006-05-24 07:18:44 +07:00
|
|
|
|
2009-01-07 01:38:17 +07:00
|
|
|
int (*device_alloc_chan_resources)(struct dma_chan *chan);
|
2006-05-24 07:18:44 +07:00
|
|
|
void (*device_free_chan_resources)(struct dma_chan *chan);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
|
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
|
2008-02-03 09:49:57 +07:00
|
|
|
struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
2008-02-03 09:49:58 +07:00
|
|
|
size_t len, unsigned long flags);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
|
2008-02-03 09:49:57 +07:00
|
|
|
struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
|
2008-02-03 09:49:58 +07:00
|
|
|
unsigned int src_cnt, size_t len, unsigned long flags);
|
2009-04-09 04:28:37 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
|
2008-02-03 09:49:57 +07:00
|
|
|
struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
|
2009-08-30 09:09:26 +07:00
|
|
|
size_t len, enum sum_check_flags *result, unsigned long flags);
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
|
|
|
|
struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
|
|
|
|
unsigned int src_cnt, const unsigned char *scf,
|
|
|
|
size_t len, unsigned long flags);
|
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
|
|
|
|
struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
|
|
|
|
unsigned int src_cnt, const unsigned char *scf, size_t len,
|
|
|
|
enum sum_check_flags *pqres, unsigned long flags);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
|
2008-04-18 10:17:26 +07:00
|
|
|
struct dma_chan *chan, unsigned long flags);
|
2010-09-30 18:46:44 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
|
|
|
|
struct dma_chan *chan,
|
|
|
|
struct scatterlist *dst_sg, unsigned int dst_nents,
|
|
|
|
struct scatterlist *src_sg, unsigned int src_nents,
|
|
|
|
unsigned long flags);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-09 01:59:35 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
2011-10-13 16:45:27 +07:00
|
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
2012-03-09 03:35:13 +07:00
|
|
|
unsigned long flags, void *context);
|
2010-09-30 20:56:32 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
|
|
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
2012-03-09 03:35:13 +07:00
|
|
|
size_t period_len, enum dma_transfer_direction direction,
|
2014-08-01 17:20:10 +07:00
|
|
|
unsigned long flags);
|
2011-10-13 14:03:30 +07:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
|
|
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
|
|
unsigned long flags);
|
2010-05-18 06:30:42 +07:00
|
|
|
int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
|
|
unsigned long arg);
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-09 01:59:35 +07:00
|
|
|
|
2010-03-27 06:50:49 +07:00
|
|
|
enum dma_status (*device_tx_status)(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie,
|
|
|
|
struct dma_tx_state *txstate);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
void (*device_issue_pending)(struct dma_chan *chan);
|
2013-07-08 15:45:25 +07:00
|
|
|
int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
|
2006-05-24 07:18:44 +07:00
|
|
|
};
|
|
|
|
|
2010-09-30 20:56:33 +07:00
|
|
|
static inline int dmaengine_device_control(struct dma_chan *chan,
|
|
|
|
enum dma_ctrl_cmd cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
2012-11-12 06:03:20 +07:00
|
|
|
if (chan->device->device_control)
|
|
|
|
return chan->device->device_control(chan, cmd, arg);
|
2013-02-14 16:00:16 +07:00
|
|
|
|
|
|
|
return -ENOSYS;
|
2010-09-30 20:56:33 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int dmaengine_slave_config(struct dma_chan *chan,
|
|
|
|
struct dma_slave_config *config)
|
|
|
|
{
|
|
|
|
return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
|
|
|
|
(unsigned long)config);
|
|
|
|
}
|
|
|
|
|
2013-01-10 15:52:56 +07:00
|
|
|
static inline bool is_slave_direction(enum dma_transfer_direction direction)
|
|
|
|
{
|
|
|
|
return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
|
|
|
|
}
|
|
|
|
|
2011-07-25 21:27:52 +07:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
|
2012-04-26 01:50:53 +07:00
|
|
|
struct dma_chan *chan, dma_addr_t buf, size_t len,
|
2011-10-13 16:45:27 +07:00
|
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
2011-07-25 21:27:52 +07:00
|
|
|
{
|
|
|
|
struct scatterlist sg;
|
2012-04-26 01:50:53 +07:00
|
|
|
sg_init_table(&sg, 1);
|
|
|
|
sg_dma_address(&sg) = buf;
|
|
|
|
sg_dma_len(&sg) = len;
|
2011-07-25 21:27:52 +07:00
|
|
|
|
2012-03-09 03:35:13 +07:00
|
|
|
return chan->device->device_prep_slave_sg(chan, &sg, 1,
|
|
|
|
dir, flags, NULL);
|
2011-07-25 21:27:52 +07:00
|
|
|
}
|
|
|
|
|
2012-03-09 04:11:18 +07:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
|
|
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
|
|
|
{
|
|
|
|
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
|
2012-03-09 03:35:13 +07:00
|
|
|
dir, flags, NULL);
|
2012-03-09 04:11:18 +07:00
|
|
|
}
|
|
|
|
|
2012-06-01 06:26:38 +07:00
|
|
|
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
|
|
|
struct rio_dma_ext;
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
|
|
|
|
enum dma_transfer_direction dir, unsigned long flags,
|
|
|
|
struct rio_dma_ext *rio_ext)
|
|
|
|
{
|
|
|
|
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
|
|
|
|
dir, flags, rio_ext);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-03-09 04:11:18 +07:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
|
|
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
2012-09-24 14:58:04 +07:00
|
|
|
size_t period_len, enum dma_transfer_direction dir,
|
|
|
|
unsigned long flags)
|
2012-03-09 04:11:18 +07:00
|
|
|
{
|
|
|
|
return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
|
2014-08-01 17:20:10 +07:00
|
|
|
period_len, dir, flags);
|
2012-11-06 20:32:39 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
|
|
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
return chan->device->device_prep_interleaved_dma(chan, xt, flags);
|
2011-07-25 21:27:52 +07:00
|
|
|
}
|
|
|
|
|
2014-10-11 22:46:43 +07:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
|
|
|
|
struct dma_chan *chan,
|
|
|
|
struct scatterlist *dst_sg, unsigned int dst_nents,
|
|
|
|
struct scatterlist *src_sg, unsigned int src_nents,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
|
|
|
|
src_sg, src_nents, flags);
|
|
|
|
}
|
|
|
|
|
2013-07-08 15:45:25 +07:00
|
|
|
static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
|
|
|
|
{
|
|
|
|
if (!chan || !caps)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* check if the channel supports slave transactions */
|
|
|
|
if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
if (chan->device->device_slave_caps)
|
|
|
|
return chan->device->device_slave_caps(chan, caps);
|
|
|
|
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
2010-09-30 20:56:33 +07:00
|
|
|
static inline int dmaengine_terminate_all(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int dmaengine_pause(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
return dmaengine_device_control(chan, DMA_PAUSE, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int dmaengine_resume(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
return dmaengine_device_control(chan, DMA_RESUME, 0);
|
|
|
|
}
|
|
|
|
|
2012-06-12 01:11:40 +07:00
|
|
|
static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie, struct dma_tx_state *state)
|
|
|
|
{
|
|
|
|
return chan->device->device_tx_status(chan, cookie, state);
|
|
|
|
}
|
|
|
|
|
2011-01-02 06:00:23 +07:00
|
|
|
static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
|
2010-09-30 20:56:33 +07:00
|
|
|
{
|
|
|
|
return desc->tx_submit(desc);
|
|
|
|
}
|
|
|
|
|
2009-09-09 07:42:53 +07:00
|
|
|
static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
size_t mask;
|
|
|
|
|
|
|
|
if (!align)
|
|
|
|
return true;
|
|
|
|
mask = (1 << align) - 1;
|
|
|
|
if (mask & (off1 | off2 | len))
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->copy_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->xor_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->pq_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->fill_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
static inline void
|
|
|
|
dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
|
|
|
|
{
|
|
|
|
dma->max_pq = maxpq;
|
|
|
|
if (has_pq_continue)
|
|
|
|
dma->max_pq |= DMA_HAS_PQ_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dmaf_continue(enum dma_ctrl_flags flags)
|
|
|
|
{
|
|
|
|
return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
|
|
|
|
{
|
|
|
|
enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
|
|
|
|
|
|
|
|
return (flags & mask) == mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
|
|
|
|
{
|
|
|
|
return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
|
|
|
|
}
|
|
|
|
|
2010-08-14 20:02:44 +07:00
|
|
|
static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-15 02:20:36 +07:00
|
|
|
{
|
|
|
|
return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dma_maxpq - reduce maxpq in the face of continued operations
|
|
|
|
* @dma - dma device with PQ capability
|
|
|
|
* @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
|
|
|
|
*
|
|
|
|
* When an engine does not support native continuation we need 3 extra
|
|
|
|
* source slots to reuse P and Q with the following coefficients:
|
|
|
|
* 1/ {00} * P : remove P from Q', but use it as a source for P'
|
|
|
|
* 2/ {01} * Q : use Q to continue Q' calculation
|
|
|
|
* 3/ {00} * Q : subtract Q from P' to cancel (2)
|
|
|
|
*
|
|
|
|
* In the case where P is disabled we only need 1 extra source:
|
|
|
|
* 1/ {01} * Q : use Q to continue Q' calculation
|
|
|
|
*/
|
|
|
|
static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
|
|
|
|
{
|
|
|
|
if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
|
|
|
|
return dma_dev_to_maxpq(dma);
|
|
|
|
else if (dmaf_p_disabled_continue(flags))
|
|
|
|
return dma_dev_to_maxpq(dma) - 1;
|
|
|
|
else if (dmaf_continue(flags))
|
|
|
|
return dma_dev_to_maxpq(dma) - 3;
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
2006-05-24 07:18:44 +07:00
|
|
|
/* --- public DMA engine API --- */
|
|
|
|
|
2009-01-11 15:20:39 +07:00
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
2009-01-07 01:38:17 +07:00
|
|
|
void dmaengine_get(void);
|
|
|
|
void dmaengine_put(void);
|
2009-01-11 15:20:39 +07:00
|
|
|
#else
|
|
|
|
static inline void dmaengine_get(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void dmaengine_put(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-03-25 23:13:25 +07:00
|
|
|
#ifdef CONFIG_ASYNC_TX_DMA
|
|
|
|
#define async_dmaengine_get() dmaengine_get()
|
|
|
|
#define async_dmaengine_put() dmaengine_put()
|
2010-10-08 06:44:50 +07:00
|
|
|
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2009-09-09 07:42:51 +07:00
|
|
|
#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
|
|
|
|
#else
|
2009-03-25 23:13:25 +07:00
|
|
|
#define async_dma_find_channel(type) dma_find_channel(type)
|
2010-10-08 06:44:50 +07:00
|
|
|
#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
|
2009-03-25 23:13:25 +07:00
|
|
|
#else
|
|
|
|
static inline void async_dmaengine_get(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void async_dmaengine_put(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline struct dma_chan *
|
|
|
|
async_dma_find_channel(enum dma_transaction_type type)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2009-09-09 07:42:51 +07:00
|
|
|
#endif /* CONFIG_ASYNC_TX_DMA */
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
|
2013-12-31 03:37:29 +07:00
|
|
|
struct dma_chan *chan);
|
2006-05-24 07:18:44 +07:00
|
|
|
|
2008-07-18 07:59:56 +07:00
|
|
|
static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
{
|
2008-04-18 10:17:26 +07:00
|
|
|
tx->flags |= DMA_CTRL_ACK;
|
|
|
|
}
|
|
|
|
|
2009-01-20 05:36:21 +07:00
|
|
|
static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
tx->flags &= ~DMA_CTRL_ACK;
|
|
|
|
}
|
|
|
|
|
2008-07-18 07:59:56 +07:00
|
|
|
static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
|
2008-04-18 10:17:26 +07:00
|
|
|
{
|
2008-07-18 07:59:56 +07:00
|
|
|
return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
|
2006-05-24 07:18:44 +07:00
|
|
|
}
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
|
|
|
|
static inline void
|
|
|
|
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
2006-05-24 07:18:44 +07:00
|
|
|
{
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
set_bit(tx_type, dstp->bits);
|
|
|
|
}
|
2006-05-24 07:18:44 +07:00
|
|
|
|
2009-03-06 18:07:14 +07:00
|
|
|
#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
|
|
|
|
static inline void
|
|
|
|
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
|
|
|
{
|
|
|
|
clear_bit(tx_type, dstp->bits);
|
|
|
|
}
|
|
|
|
|
2009-01-07 01:38:15 +07:00
|
|
|
#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
|
|
|
|
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
|
|
|
|
{
|
|
|
|
bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
|
|
|
|
}
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
|
|
|
|
static inline int
|
|
|
|
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
|
|
|
|
{
|
|
|
|
return test_bit(tx_type, srcp->bits);
|
2006-05-24 07:18:44 +07:00
|
|
|
}
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
#define for_each_dma_cap_mask(cap, mask) \
|
2012-10-26 21:35:15 +07:00
|
|
|
for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
|
2006-05-24 07:18:44 +07:00
|
|
|
/**
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* dma_async_issue_pending - flush pending transactions to HW
|
2006-07-04 09:44:51 +07:00
|
|
|
* @chan: target DMA channel
|
2006-05-24 07:18:44 +07:00
|
|
|
*
|
|
|
|
* This allows drivers to push copies to HW in batches,
|
|
|
|
* reducing MMIO writes where possible.
|
|
|
|
*/
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
static inline void dma_async_issue_pending(struct dma_chan *chan)
|
2006-05-24 07:18:44 +07:00
|
|
|
{
|
2008-03-01 21:51:29 +07:00
|
|
|
chan->device->device_issue_pending(chan);
|
2006-05-24 07:18:44 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
* dma_async_is_tx_complete - poll for transaction completion
|
2006-05-24 07:18:44 +07:00
|
|
|
* @chan: DMA channel
|
|
|
|
* @cookie: transaction identifier to check status of
|
|
|
|
* @last: returns last completed cookie, can be NULL
|
|
|
|
* @used: returns last issued cookie, can be NULL
|
|
|
|
*
|
|
|
|
* If @last and @used are passed in, upon return they reflect the driver
|
|
|
|
* internal state and can be used with dma_async_is_complete() to check
|
|
|
|
* the status of multiple cookies without re-checking hardware state.
|
|
|
|
*/
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-03 01:10:43 +07:00
|
|
|
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
|
2006-05-24 07:18:44 +07:00
|
|
|
dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
|
|
|
|
{
|
2010-03-27 06:50:49 +07:00
|
|
|
struct dma_tx_state state;
|
|
|
|
enum dma_status status;
|
|
|
|
|
|
|
|
status = chan->device->device_tx_status(chan, cookie, &state);
|
|
|
|
if (last)
|
|
|
|
*last = state.last;
|
|
|
|
if (used)
|
|
|
|
*used = state.used;
|
|
|
|
return status;
|
2006-05-24 07:18:44 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_async_is_complete - test a cookie against chan state
|
|
|
|
* @cookie: transaction identifier to test status of
|
|
|
|
* @last_complete: last know completed transaction
|
|
|
|
* @last_used: last cookie value handed out
|
|
|
|
*
|
2012-11-08 17:01:01 +07:00
|
|
|
* dma_async_is_complete() is used in dma_async_is_tx_complete()
|
2008-04-22 05:38:45 +07:00
|
|
|
* the test logic is separated for lightweight testing of multiple cookies
|
2006-05-24 07:18:44 +07:00
|
|
|
*/
|
|
|
|
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
|
|
|
|
dma_cookie_t last_complete, dma_cookie_t last_used)
|
|
|
|
{
|
|
|
|
if (last_complete <= last_used) {
|
|
|
|
if ((cookie <= last_complete) || (cookie > last_used))
|
2013-10-16 14:59:02 +07:00
|
|
|
return DMA_COMPLETE;
|
2006-05-24 07:18:44 +07:00
|
|
|
} else {
|
|
|
|
if ((cookie <= last_complete) && (cookie > last_used))
|
2013-10-16 14:59:02 +07:00
|
|
|
return DMA_COMPLETE;
|
2006-05-24 07:18:44 +07:00
|
|
|
}
|
|
|
|
return DMA_IN_PROGRESS;
|
|
|
|
}
|
|
|
|
|
2010-03-27 06:52:10 +07:00
|
|
|
static inline void
|
|
|
|
dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
|
|
|
|
{
|
|
|
|
if (st) {
|
|
|
|
st->last = last;
|
|
|
|
st->used = used;
|
|
|
|
st->residue = residue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-06 07:14:31 +07:00
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
2013-09-10 06:51:59 +07:00
|
|
|
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
|
|
|
|
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
|
2009-01-06 07:14:31 +07:00
|
|
|
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
|
2009-01-20 05:33:14 +07:00
|
|
|
void dma_issue_pending_all(void);
|
2013-03-25 19:23:52 +07:00
|
|
|
struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
|
|
|
|
dma_filter_fn fn, void *fn_param);
|
dma: add channel request API that supports deferred probe
dma_request_slave_channel() simply returns NULL whenever DMA channel
lookup fails. Lookup could fail for two distinct reasons:
a) No DMA specification exists for the channel name.
This includes situations where no DMA specifications exist at all, or
other general lookup problems.
b) A DMA specification does exist, yet the driver for that channel is not
yet registered.
Case (b) should trigger deferred probe in client drivers. However, since
they have no way to differentiate the two situations, it cannot.
Implement new function dma_request_slave_channel_reason(), which performs
identically to dma_request_slave_channel(), except that it returns an
error-pointer rather than NULL, which allows callers to detect when
deferred probe should occur.
Eventually, all drivers should be converted to this new API, the old API
removed, and the new API renamed to the more desirable name. This patch
doesn't convert the existing API and all drivers in one go, since some
drivers call dma_request_slave_channel() then dma_request_channel() if
that fails. That would require either modifying dma_request_channel() in
the same way, or adding extra error-handling code to all affected
drivers, and there are close to 100 drivers using the other API, rather
than just the 15-20 or so that use dma_request_slave_channel(), which
might be tenable in a single patch.
acpi_dma_request_slave_chan_by_name() doesn't currently implement
deferred probe. It should, but this will be addressed later.
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-11-27 00:04:22 +07:00
|
|
|
struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
|
|
|
|
const char *name);
|
2013-02-24 22:36:09 +07:00
|
|
|
struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
|
2010-12-22 20:46:46 +07:00
|
|
|
void dma_release_channel(struct dma_chan *chan);
|
2009-01-06 07:14:31 +07:00
|
|
|
#else
|
2013-09-10 06:51:59 +07:00
|
|
|
static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
|
|
|
|
{
|
2013-10-16 14:59:02 +07:00
|
|
|
return DMA_COMPLETE;
|
2013-09-10 06:51:59 +07:00
|
|
|
}
|
2009-01-06 07:14:31 +07:00
|
|
|
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
2013-10-16 14:59:02 +07:00
|
|
|
return DMA_COMPLETE;
|
2009-01-06 07:14:31 +07:00
|
|
|
}
|
2009-01-20 05:33:14 +07:00
|
|
|
static inline void dma_issue_pending_all(void)
|
|
|
|
{
|
2010-12-22 20:46:46 +07:00
|
|
|
}
|
2013-03-25 19:23:52 +07:00
|
|
|
static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
|
2010-12-22 20:46:46 +07:00
|
|
|
dma_filter_fn fn, void *fn_param)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
dma: add channel request API that supports deferred probe
dma_request_slave_channel() simply returns NULL whenever DMA channel
lookup fails. Lookup could fail for two distinct reasons:
a) No DMA specification exists for the channel name.
This includes situations where no DMA specifications exist at all, or
other general lookup problems.
b) A DMA specification does exist, yet the driver for that channel is not
yet registered.
Case (b) should trigger deferred probe in client drivers. However, since
they have no way to differentiate the two situations, it cannot.
Implement new function dma_request_slave_channel_reason(), which performs
identically to dma_request_slave_channel(), except that it returns an
error-pointer rather than NULL, which allows callers to detect when
deferred probe should occur.
Eventually, all drivers should be converted to this new API, the old API
removed, and the new API renamed to the more desirable name. This patch
doesn't convert the existing API and all drivers in one go, since some
drivers call dma_request_slave_channel() then dma_request_channel() if
that fails. That would require either modifying dma_request_channel() in
the same way, or adding extra error-handling code to all affected
drivers, and there are close to 100 drivers using the other API, rather
than just the 15-20 or so that use dma_request_slave_channel(), which
might be tenable in a single patch.
acpi_dma_request_slave_chan_by_name() doesn't currently implement
deferred probe. It should, but this will be addressed later.
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-11-27 00:04:22 +07:00
|
|
|
static inline struct dma_chan *dma_request_slave_channel_reason(
|
|
|
|
struct device *dev, const char *name)
|
|
|
|
{
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
}
|
2012-09-15 05:41:57 +07:00
|
|
|
static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
|
2013-02-24 22:36:09 +07:00
|
|
|
const char *name)
|
2012-09-15 05:41:57 +07:00
|
|
|
{
|
2012-09-25 17:48:55 +07:00
|
|
|
return NULL;
|
2012-09-15 05:41:57 +07:00
|
|
|
}
|
2010-12-22 20:46:46 +07:00
|
|
|
static inline void dma_release_channel(struct dma_chan *chan)
|
|
|
|
{
|
2009-01-20 05:33:14 +07:00
|
|
|
}
|
2009-01-06 07:14:31 +07:00
|
|
|
#endif
|
2006-05-24 07:18:44 +07:00
|
|
|
|
|
|
|
/* --- DMA device --- */
|
|
|
|
|
|
|
|
int dma_async_device_register(struct dma_device *device);
|
|
|
|
void dma_async_device_unregister(struct dma_device *device);
|
2009-01-06 07:14:31 +07:00
|
|
|
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
|
2013-06-28 19:39:12 +07:00
|
|
|
struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
|
2013-11-27 02:40:51 +07:00
|
|
|
struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
|
2012-04-05 06:10:46 +07:00
|
|
|
struct dma_chan *net_dma_find_channel(void);
|
2009-01-07 01:38:15 +07:00
|
|
|
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
|
2013-02-02 01:22:52 +07:00
|
|
|
#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
|
|
|
|
__dma_request_slave_channel_compat(&(mask), x, y, dev, name)
|
|
|
|
|
|
|
|
static inline struct dma_chan
|
2013-03-25 19:23:52 +07:00
|
|
|
*__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
|
|
|
|
dma_filter_fn fn, void *fn_param,
|
|
|
|
struct device *dev, char *name)
|
2013-02-02 01:22:52 +07:00
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
|
|
|
|
chan = dma_request_slave_channel(dev, name);
|
|
|
|
if (chan)
|
|
|
|
return chan;
|
|
|
|
|
|
|
|
return __dma_request_channel(mask, fn, fn_param);
|
|
|
|
}
|
2006-05-24 07:18:44 +07:00
|
|
|
|
2006-05-24 07:50:37 +07:00
|
|
|
/* --- Helper iov-locking functions --- */
|
|
|
|
|
|
|
|
struct dma_page_list {
|
2008-03-29 10:09:38 +07:00
|
|
|
char __user *base_address;
|
2006-05-24 07:50:37 +07:00
|
|
|
int nr_pages;
|
|
|
|
struct page **pages;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dma_pinned_list {
|
|
|
|
int nr_iovecs;
|
|
|
|
struct dma_page_list page_list[0];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
|
|
|
|
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
|
|
|
|
|
|
|
|
dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
|
|
|
|
struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
|
|
|
|
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
|
|
|
|
struct dma_pinned_list *pinned_list, struct page *page,
|
|
|
|
unsigned int offset, size_t len);
|
|
|
|
|
2006-05-24 07:18:44 +07:00
|
|
|
#endif /* DMAENGINE_H */
|