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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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151 lines
3.3 KiB
C
151 lines
3.3 KiB
C
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/*
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* linux/drivers/ide/legacy/q40ide.c -- Q40 I/O port IDE Driver
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*
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* (c) Richard Zidlicky
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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*
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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/*
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* Bases of the IDE interfaces
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*/
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#define Q40IDE_NUM_HWIFS 2
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#define PCIDE_BASE1 0x1f0
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#define PCIDE_BASE2 0x170
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#define PCIDE_BASE3 0x1e8
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#define PCIDE_BASE4 0x168
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#define PCIDE_BASE5 0x1e0
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#define PCIDE_BASE6 0x160
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static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
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PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
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PCIDE_BASE6 */
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};
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/*
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* Offsets from one of the above bases
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*/
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/* used to do addr translation here but it is easier to do in setup ports */
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/*#define IDE_OFF_B(x) ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/
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#define IDE_OFF_B(x) ((unsigned long)((IDE_##x##_OFFSET)))
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#define IDE_OFF_W(x) ((unsigned long)((IDE_##x##_OFFSET)))
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static const int pcide_offsets[IDE_NR_PORTS] = {
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IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR),
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IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS),
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518/*IDE_OFF(CMD)*/
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};
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static int q40ide_default_irq(unsigned long base)
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{
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switch (base) {
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case 0x1f0: return 14;
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case 0x170: return 15;
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case 0x1e8: return 11;
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default:
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return 0;
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}
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}
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/*
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* This is very similar to ide_setup_ports except that addresses
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* are pretranslated for q40 ISA access
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*/
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void q40_ide_setup_ports ( hw_regs_t *hw,
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unsigned long base, int *offsets,
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unsigned long ctrl, unsigned long intr,
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ide_ack_intr_t *ack_intr,
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/*
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* ide_io_ops_t *iops,
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*/
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int irq)
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{
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int i;
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for (i = 0; i < IDE_NR_PORTS; i++) {
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/* BIG FAT WARNING:
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assumption: only DATA port is ever used in 16 bit mode */
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if ( i==0 )
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hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]);
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else
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hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]);
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}
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hw->irq = irq;
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hw->dma = NO_DMA;
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hw->ack_intr = ack_intr;
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/*
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* hw->iops = iops;
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*/
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}
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/*
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* the static array is needed to have the name reported in /proc/ioports,
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* hwif->name unfortunately isn<EFBFBD>t available yet
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*/
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static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
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"ide0", "ide1"
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};
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/*
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* Probe for Q40 IDE interfaces
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*/
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void q40ide_init(void)
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{
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int i;
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ide_hwif_t *hwif;
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int index;
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const char *name;
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if (!MACH_IS_Q40)
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return ;
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for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
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hw_regs_t hw;
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name = q40_ide_names[i];
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if (!request_region(pcide_bases[i], 8, name)) {
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printk("could not reserve ports %lx-%lx for %s\n",
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pcide_bases[i],pcide_bases[i]+8,name);
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continue;
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}
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if (!request_region(pcide_bases[i]+0x206, 1, name)) {
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printk("could not reserve port %lx for %s\n",
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pcide_bases[i]+0x206,name);
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release_region(pcide_bases[i], 8);
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continue;
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}
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q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets,
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pcide_bases[i]+0x206,
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0, NULL,
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// m68kide_iops,
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q40ide_default_irq(pcide_bases[i]));
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index = ide_register_hw(&hw, &hwif);
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// **FIXME**
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if (index != -1)
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hwif->mmio = 2;
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}
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}
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