2005-06-28 19:48:56 +07:00
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/* via_irq.c
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*
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* Copyright 2004 BEAM Ltd.
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* Copyright 2002 Tungsten Graphics, Inc.
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* Copyright 2005 Thomas Hellstrom.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Terry Barnaby <terry1@beam.ltd.uk>
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* Keith Whitwell <keith@tungstengraphics.com>
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* Thomas Hellstrom <unichrome@shipmail.org>
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*
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* This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
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* interrupt, as well as an infrastructure to handle other interrupts of the chip.
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* The refresh rate is also calculated for video playback sync purposes.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "via_drm.h"
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#include "via_drv.h"
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#define VIA_REG_INTERRUPT 0x200
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/* VIA_REG_INTERRUPT */
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#define VIA_IRQ_GLOBAL (1 << 31)
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#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
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#define VIA_IRQ_VBLANK_PENDING (1 << 3)
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#define VIA_IRQ_HQV0_ENABLE (1 << 11)
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#define VIA_IRQ_HQV1_ENABLE (1 << 25)
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#define VIA_IRQ_HQV0_PENDING (1 << 9)
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#define VIA_IRQ_HQV1_PENDING (1 << 10)
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2005-11-12 17:52:46 +07:00
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#define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
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#define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
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#define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
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#define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
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#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
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#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
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#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
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#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
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2005-06-28 19:48:56 +07:00
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/*
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* Device-specific IRQs go here. This type might need to be extended with
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* the register if there are multiple IRQ control registers.
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2005-09-25 11:28:13 +07:00
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* Currently we activate the HQV interrupts of Unichrome Pro group A.
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2005-06-28 19:48:56 +07:00
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*/
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static maskarray_t via_pro_group_a_irqs[] = {
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2005-09-25 11:28:13 +07:00
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{VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
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0x00000000},
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{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
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2005-11-12 17:52:46 +07:00
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0x00000000},
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{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
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VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
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{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
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VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
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2005-09-25 11:28:13 +07:00
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};
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static int via_num_pro_group_a =
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sizeof(via_pro_group_a_irqs) / sizeof(maskarray_t);
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2005-11-12 17:52:46 +07:00
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static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
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2005-09-25 11:28:13 +07:00
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2005-11-12 17:52:46 +07:00
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static maskarray_t via_unichrome_irqs[] = {
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{VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
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VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
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{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
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VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
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};
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2005-09-25 11:28:13 +07:00
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static int via_num_unichrome = sizeof(via_unichrome_irqs) / sizeof(maskarray_t);
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2005-11-12 17:52:46 +07:00
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static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
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2005-09-25 11:28:13 +07:00
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static unsigned time_diff(struct timeval *now, struct timeval *then)
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2005-06-28 19:48:56 +07:00
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{
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2005-09-25 11:28:13 +07:00
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return (now->tv_usec >= then->tv_usec) ?
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now->tv_usec - then->tv_usec :
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1000000 - (then->tv_usec - now->tv_usec);
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2005-06-28 19:48:56 +07:00
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}
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irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
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{
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drm_device_t *dev = (drm_device_t *) arg;
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drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
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u32 status;
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int handled = 0;
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struct timeval cur_vblank;
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drm_via_irq_t *cur_irq = dev_priv->via_irqs;
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int i;
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status = VIA_READ(VIA_REG_INTERRUPT);
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if (status & VIA_IRQ_VBLANK_PENDING) {
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atomic_inc(&dev->vbl_received);
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2005-09-25 11:28:13 +07:00
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if (!(atomic_read(&dev->vbl_received) & 0x0F)) {
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2005-06-28 19:48:56 +07:00
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do_gettimeofday(&cur_vblank);
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2005-09-25 11:28:13 +07:00
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if (dev_priv->last_vblank_valid) {
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dev_priv->usec_per_vblank =
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time_diff(&cur_vblank,
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&dev_priv->last_vblank) >> 4;
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2005-06-28 19:48:56 +07:00
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}
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dev_priv->last_vblank = cur_vblank;
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dev_priv->last_vblank_valid = 1;
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2005-09-25 11:28:13 +07:00
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}
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if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
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2005-06-28 19:48:56 +07:00
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DRM_DEBUG("US per vblank is: %u\n",
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2005-09-25 11:28:13 +07:00
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dev_priv->usec_per_vblank);
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2005-06-28 19:48:56 +07:00
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}
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DRM_WAKEUP(&dev->vbl_queue);
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drm_vbl_send_signals(dev);
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handled = 1;
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}
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2005-09-25 11:28:13 +07:00
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for (i = 0; i < dev_priv->num_irqs; ++i) {
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2005-06-28 19:48:56 +07:00
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if (status & cur_irq->pending_mask) {
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2005-09-25 11:28:13 +07:00
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atomic_inc(&cur_irq->irq_received);
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DRM_WAKEUP(&cur_irq->irq_queue);
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2005-06-28 19:48:56 +07:00
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handled = 1;
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2005-11-12 17:52:46 +07:00
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if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
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via_dmablit_handler(dev, 0, 1);
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} else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {
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via_dmablit_handler(dev, 1, 1);
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}
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2005-06-28 19:48:56 +07:00
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}
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cur_irq++;
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}
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2005-09-25 11:28:13 +07:00
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2005-06-28 19:48:56 +07:00
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/* Acknowlege interrupts */
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VIA_WRITE(VIA_REG_INTERRUPT, status);
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if (handled)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
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{
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u32 status;
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if (dev_priv) {
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/* Acknowlege interrupts */
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status = VIA_READ(VIA_REG_INTERRUPT);
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2005-09-25 11:28:13 +07:00
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VIA_WRITE(VIA_REG_INTERRUPT, status |
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2005-06-28 19:48:56 +07:00
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dev_priv->irq_pending_mask);
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}
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}
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int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
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unsigned int cur_vblank;
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int ret = 0;
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DRM_DEBUG("viadrv_vblank_wait\n");
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if (!dev_priv) {
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DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
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return -EINVAL;
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}
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viadrv_acknowledge_irqs(dev_priv);
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/* Assume that the user has missed the current sequence number
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* by about a day rather than she wants to wait for years
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* using vertical blanks...
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*/
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DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
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(((cur_vblank = atomic_read(&dev->vbl_received)) -
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*sequence) <= (1 << 23)));
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2005-09-25 11:28:13 +07:00
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2005-06-28 19:48:56 +07:00
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*sequence = cur_vblank;
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return ret;
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}
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2006-02-02 15:21:38 +07:00
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static int
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2005-06-28 19:48:56 +07:00
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via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence,
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unsigned int *sequence)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
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unsigned int cur_irq_sequence;
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2006-04-11 13:18:28 +07:00
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drm_via_irq_t *cur_irq;
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2005-06-28 19:48:56 +07:00
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int ret = 0;
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2006-04-05 15:10:11 +07:00
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maskarray_t *masks;
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2005-11-12 17:52:46 +07:00
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int real_irq;
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2005-06-28 19:48:56 +07:00
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DRM_DEBUG("%s\n", __FUNCTION__);
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if (!dev_priv) {
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DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
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return DRM_ERR(EINVAL);
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}
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2005-11-12 17:52:46 +07:00
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if (irq >= drm_via_irq_num) {
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2005-09-25 11:28:13 +07:00
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DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
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irq);
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2005-06-28 19:48:56 +07:00
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return DRM_ERR(EINVAL);
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}
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2005-09-25 11:28:13 +07:00
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2005-11-12 17:52:46 +07:00
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real_irq = dev_priv->irq_map[irq];
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if (real_irq < 0) {
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DRM_ERROR("%s Video IRQ %d not available on this hardware.\n",
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__FUNCTION__, irq);
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return DRM_ERR(EINVAL);
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}
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2006-04-05 15:10:11 +07:00
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masks = dev_priv->irq_masks;
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2006-04-11 13:18:28 +07:00
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cur_irq = dev_priv->via_irqs + real_irq;
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2005-06-28 19:48:56 +07:00
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2005-11-12 17:52:46 +07:00
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if (masks[real_irq][2] && !force_sequence) {
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2005-06-28 19:48:56 +07:00
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DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
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2005-09-25 11:28:13 +07:00
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((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
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masks[irq][4]));
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2005-06-28 19:48:56 +07:00
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cur_irq_sequence = atomic_read(&cur_irq->irq_received);
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} else {
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DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
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2005-09-25 11:28:13 +07:00
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(((cur_irq_sequence =
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atomic_read(&cur_irq->irq_received)) -
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*sequence) <= (1 << 23)));
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2005-06-28 19:48:56 +07:00
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}
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*sequence = cur_irq_sequence;
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return ret;
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}
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/*
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* drm_dma.h hooks
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*/
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void via_driver_irq_preinstall(drm_device_t * dev)
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{
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drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
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u32 status;
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2006-04-11 13:18:28 +07:00
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drm_via_irq_t *cur_irq;
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2005-06-28 19:48:56 +07:00
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int i;
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DRM_DEBUG("driver_irq_preinstall: dev_priv: %p\n", dev_priv);
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if (dev_priv) {
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2006-04-11 13:18:28 +07:00
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cur_irq = dev_priv->via_irqs;
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2005-06-28 19:48:56 +07:00
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dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
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dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
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dev_priv->irq_masks = (dev_priv->pro_group_a) ?
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2005-09-25 11:28:13 +07:00
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via_pro_group_a_irqs : via_unichrome_irqs;
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2005-06-28 19:48:56 +07:00
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dev_priv->num_irqs = (dev_priv->pro_group_a) ?
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2005-09-25 11:28:13 +07:00
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via_num_pro_group_a : via_num_unichrome;
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2005-11-12 17:52:46 +07:00
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dev_priv->irq_map = (dev_priv->pro_group_a) ?
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via_irqmap_pro_group_a : via_irqmap_unichrome;
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2005-09-25 11:28:13 +07:00
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for (i = 0; i < dev_priv->num_irqs; ++i) {
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2005-06-28 19:48:56 +07:00
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atomic_set(&cur_irq->irq_received, 0);
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2005-09-25 11:28:13 +07:00
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cur_irq->enable_mask = dev_priv->irq_masks[i][0];
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2005-06-28 19:48:56 +07:00
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cur_irq->pending_mask = dev_priv->irq_masks[i][1];
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2005-09-25 11:28:13 +07:00
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DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
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2005-06-28 19:48:56 +07:00
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dev_priv->irq_enable_mask |= cur_irq->enable_mask;
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dev_priv->irq_pending_mask |= cur_irq->pending_mask;
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cur_irq++;
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2005-09-25 11:28:13 +07:00
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2005-06-28 19:48:56 +07:00
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DRM_DEBUG("Initializing IRQ %d\n", i);
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}
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2005-09-25 11:28:13 +07:00
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dev_priv->last_vblank_valid = 0;
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2005-06-28 19:48:56 +07:00
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2005-11-12 17:52:46 +07:00
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/* Clear VSync interrupt regs */
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2005-06-28 19:48:56 +07:00
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status = VIA_READ(VIA_REG_INTERRUPT);
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2005-09-25 11:28:13 +07:00
|
|
|
VIA_WRITE(VIA_REG_INTERRUPT, status &
|
2005-06-28 19:48:56 +07:00
|
|
|
~(dev_priv->irq_enable_mask));
|
2005-09-25 11:28:13 +07:00
|
|
|
|
2005-06-28 19:48:56 +07:00
|
|
|
/* Clear bits if they're already high */
|
|
|
|
viadrv_acknowledge_irqs(dev_priv);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void via_driver_irq_postinstall(drm_device_t * dev)
|
|
|
|
{
|
|
|
|
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
|
|
|
|
u32 status;
|
|
|
|
|
|
|
|
DRM_DEBUG("via_driver_irq_postinstall\n");
|
|
|
|
if (dev_priv) {
|
|
|
|
status = VIA_READ(VIA_REG_INTERRUPT);
|
|
|
|
VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
|
|
|
|
| dev_priv->irq_enable_mask);
|
|
|
|
|
|
|
|
/* Some magic, oh for some data sheets ! */
|
|
|
|
|
|
|
|
VIA_WRITE8(0x83d4, 0x11);
|
|
|
|
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
|
2005-09-25 11:28:13 +07:00
|
|
|
|
2005-06-28 19:48:56 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void via_driver_irq_uninstall(drm_device_t * dev)
|
|
|
|
{
|
|
|
|
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
|
|
|
|
u32 status;
|
|
|
|
|
|
|
|
DRM_DEBUG("driver_irq_uninstall)\n");
|
|
|
|
if (dev_priv) {
|
|
|
|
|
|
|
|
/* Some more magic, oh for some data sheets ! */
|
|
|
|
|
|
|
|
VIA_WRITE8(0x83d4, 0x11);
|
|
|
|
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
|
|
|
|
|
|
|
|
status = VIA_READ(VIA_REG_INTERRUPT);
|
2005-09-25 11:28:13 +07:00
|
|
|
VIA_WRITE(VIA_REG_INTERRUPT, status &
|
2005-06-28 19:48:56 +07:00
|
|
|
~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int via_wait_irq(DRM_IOCTL_ARGS)
|
|
|
|
{
|
2005-11-12 17:52:46 +07:00
|
|
|
DRM_DEVICE;
|
2005-06-28 19:48:56 +07:00
|
|
|
drm_via_irqwait_t __user *argp = (void __user *)data;
|
|
|
|
drm_via_irqwait_t irqwait;
|
|
|
|
struct timeval now;
|
|
|
|
int ret = 0;
|
|
|
|
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
|
|
|
|
drm_via_irq_t *cur_irq = dev_priv->via_irqs;
|
|
|
|
int force_sequence;
|
|
|
|
|
|
|
|
if (!dev->irq)
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait));
|
|
|
|
if (irqwait.request.irq >= dev_priv->num_irqs) {
|
2005-09-25 11:28:13 +07:00
|
|
|
DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
|
2005-06-28 19:48:56 +07:00
|
|
|
irqwait.request.irq);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
cur_irq += irqwait.request.irq;
|
|
|
|
|
|
|
|
switch (irqwait.request.type & ~VIA_IRQ_FLAGS_MASK) {
|
|
|
|
case VIA_IRQ_RELATIVE:
|
|
|
|
irqwait.request.sequence += atomic_read(&cur_irq->irq_received);
|
|
|
|
irqwait.request.type &= ~_DRM_VBLANK_RELATIVE;
|
|
|
|
case VIA_IRQ_ABSOLUTE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (irqwait.request.type & VIA_IRQ_SIGNAL) {
|
2005-09-25 11:28:13 +07:00
|
|
|
DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
|
2005-06-28 19:48:56 +07:00
|
|
|
__FUNCTION__);
|
|
|
|
return DRM_ERR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
force_sequence = (irqwait.request.type & VIA_IRQ_FORCE_SEQUENCE);
|
|
|
|
|
|
|
|
ret = via_driver_irq_wait(dev, irqwait.request.irq, force_sequence,
|
|
|
|
&irqwait.request.sequence);
|
|
|
|
do_gettimeofday(&now);
|
|
|
|
irqwait.reply.tval_sec = now.tv_sec;
|
|
|
|
irqwait.reply.tval_usec = now.tv_usec;
|
|
|
|
|
|
|
|
DRM_COPY_TO_USER_IOCTL(argp, irqwait, sizeof(irqwait));
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|