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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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256 lines
9.2 KiB
C
256 lines
9.2 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
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*
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* Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
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* Copyright (C) 1999 by Ralf Baechle
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*/
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#ifndef _ASM_SGI_SN0_HUBNI_H
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#define _ASM_SGI_SN0_HUBNI_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#endif
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/*
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* Hub Network Interface registers
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*
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* All registers in this file are subject to change until Hub chip tapeout.
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*/
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#define NI_BASE 0x600000
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#define NI_BASE_TABLES 0x630000
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#define NI_STATUS_REV_ID 0x600000 /* Hub network status, rev, and ID */
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#define NI_PORT_RESET 0x600008 /* Reset the network interface */
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#define NI_PROTECTION 0x600010 /* NI register access permissions */
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#define NI_GLOBAL_PARMS 0x600018 /* LLP parameters */
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#define NI_SCRATCH_REG0 0x600100 /* Scratch register 0 (64 bits) */
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#define NI_SCRATCH_REG1 0x600108 /* Scratch register 1 (64 bits) */
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#define NI_DIAG_PARMS 0x600110 /* Parameters for diags */
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#define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
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#define NI_VECTOR 0x600208 /* Vector PIO route */
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#define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
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#define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
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#define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
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#define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
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#define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
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#define NI_IO_PROTECT 0x600400 /* PIO protection bits */
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#define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
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#define NI_AGE_CPU0_MEMORY 0x600500 /* CPU 0 memory age control */
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#define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
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#define NI_AGE_CPU1_MEMORY 0x600510 /* CPU 1 memory age control */
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#define NI_AGE_CPU1_PIO 0x600518 /* CPU 1 PIO age control */
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#define NI_AGE_GBR_MEMORY 0x600520 /* GBR memory age control */
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#define NI_AGE_GBR_PIO 0x600528 /* GBR PIO age control */
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#define NI_AGE_IO_MEMORY 0x600530 /* IO memory age control */
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#define NI_AGE_IO_PIO 0x600538 /* IO PIO age control */
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#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
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#define NI_AGE_REG_MAX NI_AGE_IO_PIO
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#define NI_PORT_PARMS 0x608000 /* LLP Parameters */
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#define NI_PORT_ERROR 0x608008 /* LLP Errors */
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#define NI_PORT_ERROR_CLEAR 0x608088 /* Clear the error bits */
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#define NI_META_TABLE0 0x638000 /* First meta routing table entry */
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#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
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#define NI_META_ENTRIES 32
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#define NI_LOCAL_TABLE0 0x638100 /* First local routing table entry */
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#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
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#define NI_LOCAL_ENTRIES 16
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/*
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* NI_STATUS_REV_ID mask and shift definitions
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* Have to use UINT64_CAST instead of 'L' suffix, for assembler.
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*/
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#define NSRI_8BITMODE_SHFT 30
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#define NSRI_8BITMODE_MASK (UINT64_CAST 0x1 << 30)
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#define NSRI_LINKUP_SHFT 29
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#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
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#define NSRI_DOWNREASON_SHFT 28 /* 0=failed, 1=never came */
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#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
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#define NSRI_MORENODES_SHFT 18
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#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18) /* Max. # of nodes */
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#define MORE_MEMORY 0
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#define MORE_NODES 1
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#define NSRI_REGIONSIZE_SHFT 17
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#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17) /* Granularity */
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#define REGIONSIZE_FINE 1
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#define REGIONSIZE_COARSE 0
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#define NSRI_NODEID_SHFT 8
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#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID */
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#define NSRI_REV_SHFT 4
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#define NSRI_REV_MASK (UINT64_CAST 0xf << 4) /* Chip Revision */
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#define NSRI_CHIPID_SHFT 0
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#define NSRI_CHIPID_MASK (UINT64_CAST 0xf) /* Chip type ID */
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/*
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* In fine mode, each node is a region. In coarse mode, there are
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* eight nodes per region.
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*/
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#define NASID_TO_FINEREG_SHFT 0
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#define NASID_TO_COARSEREG_SHFT 3
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/* NI_PORT_RESET mask definitions */
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#define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
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#define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
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#define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
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/* NI_PROTECTION mask and shift definitions */
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#define NPROT_RESETOK (UINT64_CAST 1)
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/* NI_GLOBAL_PARMS mask and shift definitions */
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#define NGP_MAXRETRY_SHFT 48 /* Maximum retries */
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#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
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#define NGP_TAILTOWRAP_SHFT 32 /* Tail timeout wrap */
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#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
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#define NGP_CREDITTOVAL_SHFT 16 /* Tail timeout wrap */
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#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
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#define NGP_TAILTOVAL_SHFT 4 /* Tail timeout value */
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#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
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/* NI_DIAG_PARMS mask and shift definitions */
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#define NDP_PORTTORESET (UINT64_CAST 1 << 18) /* Port tmout reset */
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#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12) /* LLP 8-bit mode */
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#define NDP_PORTDISABLE (UINT64_CAST 1 << 6) /* Port disable */
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#define NDP_SENDERROR (UINT64_CAST 1) /* Send data error */
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/*
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* NI_VECTOR_PARMS mask and shift definitions.
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* TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
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*/
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#define NVP_PIOID_SHFT 40
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#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
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#define NVP_WRITEID_SHFT 32
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#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
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#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8) /* Bits 19:3 */
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#define NVP_TYPE_SHFT 0
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#define NVP_TYPE_MASK (UINT64_CAST 0x3)
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/* NI_VECTOR_STATUS mask and shift definitions */
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#define NVS_VALID (UINT64_CAST 1 << 63)
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#define NVS_OVERRUN (UINT64_CAST 1 << 62)
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#define NVS_TARGET_SHFT 51
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#define NVS_TARGET_MASK (UINT64_CAST 0x3ff << 51)
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#define NVS_PIOID_SHFT 40
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#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
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#define NVS_WRITEID_SHFT 32
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#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
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#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8) /* Bits 31:3 */
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#define NVS_TYPE_SHFT 0
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#define NVS_TYPE_MASK (UINT64_CAST 0x7)
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#define NVS_ERROR_MASK (UINT64_CAST 0x4) /* bit set means error */
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#define PIOTYPE_READ 0 /* VECTOR_PARMS and VECTOR_STATUS */
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#define PIOTYPE_WRITE 1 /* VECTOR_PARMS and VECTOR_STATUS */
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#define PIOTYPE_UNDEFINED 2 /* VECTOR_PARMS and VECTOR_STATUS */
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#define PIOTYPE_EXCHANGE 3 /* VECTOR_PARMS and VECTOR_STATUS */
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#define PIOTYPE_ADDR_ERR 4 /* VECTOR_STATUS only */
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#define PIOTYPE_CMD_ERR 5 /* VECTOR_STATUS only */
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#define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */
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#define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */
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/* NI_AGE_XXX mask and shift definitions */
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#define NAGE_VCH_SHFT 10
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#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)
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#define NAGE_CC_SHFT 8
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#define NAGE_CC_MASK (UINT64_CAST 3 << 8)
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#define NAGE_AGE_SHFT 0
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#define NAGE_AGE_MASK (UINT64_CAST 0xff)
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#define NAGE_MASK (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
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#define VCHANNEL_A 0
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#define VCHANNEL_B 1
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#define VCHANNEL_ANY 2
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/* NI_PORT_PARMS mask and shift definitions */
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#define NPP_NULLTO_SHFT 10
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#define NPP_NULLTO_MASK (UINT64_CAST 0x3f << 16)
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#define NPP_MAXBURST_SHFT 0
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#define NPP_MAXBURST_MASK (UINT64_CAST 0x3ff)
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#define NPP_RESET_DFLT_HUB20 ((UINT64_CAST 1 << NPP_NULLTO_SHFT) | \
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(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
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#define NPP_RESET_DEFAULTS ((UINT64_CAST 6 << NPP_NULLTO_SHFT) | \
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(UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
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/* NI_PORT_ERROR mask and shift definitions */
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#define NPE_LINKRESET (UINT64_CAST 1 << 37)
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#define NPE_INTERNALERROR (UINT64_CAST 1 << 36)
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#define NPE_BADMESSAGE (UINT64_CAST 1 << 35)
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#define NPE_BADDEST (UINT64_CAST 1 << 34)
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#define NPE_FIFOOVERFLOW (UINT64_CAST 1 << 33)
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#define NPE_CREDITTO_SHFT 28
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#define NPE_CREDITTO_MASK (UINT64_CAST 0xf << 28)
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#define NPE_TAILTO_SHFT 24
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#define NPE_TAILTO_MASK (UINT64_CAST 0xf << 24)
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#define NPE_RETRYCOUNT_SHFT 16
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#define NPE_RETRYCOUNT_MASK (UINT64_CAST 0xff << 16)
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#define NPE_CBERRCOUNT_SHFT 8
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#define NPE_CBERRCOUNT_MASK (UINT64_CAST 0xff << 8)
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#define NPE_SNERRCOUNT_SHFT 0
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#define NPE_SNERRCOUNT_MASK (UINT64_CAST 0xff << 0)
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#define NPE_MASK 0x3effffffff
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#define NPE_COUNT_MAX 0xff
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#define NPE_FATAL_ERRORS (NPE_LINKRESET | NPE_INTERNALERROR | \
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NPE_BADMESSAGE | NPE_BADDEST | \
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NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
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NPE_TAILTO_MASK)
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/* NI_META_TABLE mask and shift definitions */
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#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
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/* NI_LOCAL_TABLE mask and shift definitions */
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#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
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#ifndef __ASSEMBLY__
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typedef union hubni_port_error_u {
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u64 nipe_reg_value;
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struct {
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u64 nipe_rsvd: 26, /* unused */
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nipe_lnk_reset: 1, /* link reset */
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nipe_intl_err: 1, /* internal error */
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nipe_bad_msg: 1, /* bad message */
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nipe_bad_dest: 1, /* bad dest */
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nipe_fifo_ovfl: 1, /* fifo overflow */
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nipe_rsvd1: 1, /* unused */
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nipe_credit_to: 4, /* credit timeout */
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nipe_tail_to: 4, /* tail timeout */
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nipe_retry_cnt: 8, /* retry error count */
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nipe_cb_cnt: 8, /* checkbit error count */
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nipe_sn_cnt: 8; /* sequence number count */
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} nipe_fields_s;
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} hubni_port_error_t;
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#define NI_LLP_RETRY_MAX 0xff
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#define NI_LLP_CB_MAX 0xff
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#define NI_LLP_SN_MAX 0xff
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_SGI_SN0_HUBNI_H */
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