2015-04-21 04:31:14 +07:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef VI_H
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#define VI_H
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#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
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#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
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#define SDMA_MAX_INSTANCE 2
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/* crtc instance offsets */
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#define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
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#define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
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#define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
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#define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
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#define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
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#define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
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#define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
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/* dig instance offsets */
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#define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
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#define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
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#define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
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#define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
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#define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
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#define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
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#define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
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#define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
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#define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
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/* audio endpt instance offsets */
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#define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
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#define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
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#define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
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#define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
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#define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
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#define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
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#define AUD6_REGISTER_OFFSET (0x17c4 - 0x17a8)
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/* hpd instance offsets */
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#define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
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#define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
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#define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
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#define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
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#define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
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#define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
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#define AMDGPU_NUM_OF_VMIDS 8
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#define RB_BITMAP_WIDTH_PER_SH 2
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2015-06-03 20:02:01 +07:00
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#define MC_SEQ_MISC0__MT__MASK 0xf0000000
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#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
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#define MC_SEQ_MISC0__MT__DDR2 0x20000000
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#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
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#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
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#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
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#define MC_SEQ_MISC0__MT__HBM 0x60000000
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#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
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2015-04-21 04:31:14 +07:00
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/*
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* PM4
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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((reg) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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#define PACKET2_PAD_SHIFT 0
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#define PACKET2_PAD_MASK (0x3fffffff << 0)
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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/* Packet 3 types */
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#define PACKET3_NOP 0x10
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#define PACKET3_SET_BASE 0x11
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#define PACKET3_BASE_INDEX(x) ((x) << 0)
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#define CE_PARTITION_BASE 3
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#define PACKET3_CLEAR_STATE 0x12
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#define PACKET3_INDEX_BUFFER_SIZE 0x13
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_DISPATCH_INDIRECT 0x16
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#define PACKET3_ATOMIC_GDS 0x1D
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#define PACKET3_ATOMIC_MEM 0x1E
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#define PACKET3_OCCLUSION_QUERY 0x1F
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#define PACKET3_SET_PREDICATION 0x20
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#define PACKET3_REG_RMW 0x21
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#define PACKET3_COND_EXEC 0x22
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#define PACKET3_PRED_EXEC 0x23
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#define PACKET3_DRAW_INDIRECT 0x24
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#define PACKET3_DRAW_INDEX_INDIRECT 0x25
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#define PACKET3_INDEX_BASE 0x26
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#define PACKET3_DRAW_INDEX_2 0x27
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#define PACKET3_CONTEXT_CONTROL 0x28
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#define PACKET3_INDEX_TYPE 0x2A
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#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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#define PACKET3_NUM_INSTANCES 0x2F
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#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PACKET3_INDIRECT_BUFFER_CONST 0x33
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#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_PREAMBLE 0x36
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#define PACKET3_WRITE_DATA 0x37
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#define WRITE_DATA_DST_SEL(x) ((x) << 8)
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/* 0 - register
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* 1 - memory (sync - via GRBM)
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* 2 - gl2
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* 3 - gds
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* 4 - reserved
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* 5 - memory (async - direct)
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*/
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#define WR_ONE_ADDR (1 << 16)
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#define WR_CONFIRM (1 << 20)
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#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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*/
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#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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/* 0 - me
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* 1 - pfp
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* 2 - ce
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*/
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#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PACKET3_MEM_SEMAPHORE 0x39
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# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
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# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
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# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
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# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
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# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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/* 0 - always
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* 1 - <
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* 2 - <=
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* 3 - ==
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* 4 - !=
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* 5 - >=
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* 6 - >
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*/
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#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
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/* 0 - reg
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* 1 - mem
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*/
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#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
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/* 0 - wait_reg_mem
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* 1 - wr_wait_wr_reg
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*/
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#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
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/* 0 - me
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* 1 - pfp
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*/
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#define PACKET3_INDIRECT_BUFFER 0x3F
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#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
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#define INDIRECT_BUFFER_VALID (1 << 23)
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#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_DEST_BASE_0_ENA (1 << 0)
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# define PACKET3_DEST_BASE_1_ENA (1 << 1)
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
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# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
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# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
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# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
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# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
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# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
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# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
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# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
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# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
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# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
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# define PACKET3_DEST_BASE_2_ENA (1 << 19)
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# define PACKET3_DEST_BASE_3_ENA (1 << 21)
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# define PACKET3_TCL1_ACTION_ENA (1 << 22)
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# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
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# define PACKET3_CB_ACTION_ENA (1 << 25)
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# define PACKET3_DB_ACTION_ENA (1 << 26)
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# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
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# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
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# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
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#define PACKET3_COND_WRITE 0x45
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#define PACKET3_EVENT_WRITE 0x46
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#define EVENT_TYPE(x) ((x) << 0)
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#define EVENT_INDEX(x) ((x) << 8)
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/* 0 - any non-TS event
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* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
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* 2 - SAMPLE_PIPELINESTAT
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* 3 - SAMPLE_STREAMOUTSTAT*
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* 4 - *S_PARTIAL_FLUSH
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* 5 - EOP events
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* 6 - EOS events
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*/
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#define PACKET3_EVENT_WRITE_EOP 0x47
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#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
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#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
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#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
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#define EOP_TCL1_ACTION_EN (1 << 16)
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#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
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#define EOP_TCL2_VOLATILE (1 << 24)
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#define EOP_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define DATA_SEL(x) ((x) << 29)
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/* 0 - discard
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* 1 - send low 32bit data
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* 2 - send 64bit data
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* 3 - send 64bit GPU counter value
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* 4 - send 64bit sys counter value
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*/
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#define INT_SEL(x) ((x) << 24)
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/* 0 - none
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* 1 - interrupt only (DATA_SEL = 0)
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* 2 - interrupt when data write is confirmed
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*/
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#define DST_SEL(x) ((x) << 16)
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/* 0 - MC
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* 1 - TC/L2
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*/
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#define PACKET3_EVENT_WRITE_EOS 0x48
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#define PACKET3_RELEASE_MEM 0x49
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#define PACKET3_PREAMBLE_CNTL 0x4A
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# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
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# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
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#define PACKET3_DMA_DATA 0x50
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/* 1. header
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* 2. CONTROL
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* 3. SRC_ADDR_LO or DATA [31:0]
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* 4. SRC_ADDR_HI [31:0]
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* 5. DST_ADDR_LO [31:0]
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* 6. DST_ADDR_HI [7:0]
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* 7. COMMAND [30:21] | BYTE_COUNT [20:0]
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*/
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/* CONTROL */
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# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
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/* 0 - ME
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* 1 - PFP
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*/
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# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
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# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
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/* 0 - DST_ADDR using DAS
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* 1 - GDS
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* 3 - DST_ADDR using L2
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*/
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# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
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# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
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/* 0 - SRC_ADDR using SAS
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* 1 - GDS
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* 2 - DATA
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* 3 - SRC_ADDR using L2
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*/
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# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_DMA_DATA_DIS_WC (1 << 21)
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# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
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/* 0 - none
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* 1 - 8 in 16
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* 2 - 8 in 32
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* 3 - 8 in 64
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*/
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# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
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# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
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# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
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#define PACKET3_AQUIRE_MEM 0x58
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#define PACKET3_REWIND 0x59
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#define PACKET3_LOAD_UCONFIG_REG 0x5E
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#define PACKET3_LOAD_SH_REG 0x5F
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#define PACKET3_LOAD_CONFIG_REG 0x60
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#define PACKET3_LOAD_CONTEXT_REG 0x61
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#define PACKET3_SET_CONFIG_REG 0x68
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#define PACKET3_SET_CONFIG_REG_START 0x00002000
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#define PACKET3_SET_CONFIG_REG_END 0x00002c00
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#define PACKET3_SET_CONTEXT_REG 0x69
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|
#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
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#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
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|
#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
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#define PACKET3_SET_SH_REG 0x76
|
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|
#define PACKET3_SET_SH_REG_START 0x00002c00
|
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|
|
#define PACKET3_SET_SH_REG_END 0x00003000
|
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|
|
#define PACKET3_SET_SH_REG_OFFSET 0x77
|
|
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|
#define PACKET3_SET_QUEUE_REG 0x78
|
|
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|
|
#define PACKET3_SET_UCONFIG_REG 0x79
|
|
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|
|
#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
|
|
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|
|
#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
|
|
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|
|
#define PACKET3_SCRATCH_RAM_WRITE 0x7D
|
|
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|
|
#define PACKET3_SCRATCH_RAM_READ 0x7E
|
|
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|
|
#define PACKET3_LOAD_CONST_RAM 0x80
|
|
|
|
|
#define PACKET3_WRITE_CONST_RAM 0x81
|
|
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|
|
#define PACKET3_DUMP_CONST_RAM 0x83
|
|
|
|
|
#define PACKET3_INCREMENT_CE_COUNTER 0x84
|
|
|
|
|
#define PACKET3_INCREMENT_DE_COUNTER 0x85
|
|
|
|
|
#define PACKET3_WAIT_ON_CE_COUNTER 0x86
|
|
|
|
|
#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
|
|
|
|
|
#define PACKET3_SWITCH_BUFFER 0x8B
|
|
|
|
|
|
|
|
|
|
#define VCE_CMD_NO_OP 0x00000000
|
|
|
|
|
#define VCE_CMD_END 0x00000001
|
|
|
|
|
#define VCE_CMD_IB 0x00000002
|
|
|
|
|
#define VCE_CMD_FENCE 0x00000003
|
|
|
|
|
#define VCE_CMD_TRAP 0x00000004
|
|
|
|
|
#define VCE_CMD_IB_AUTO 0x00000005
|
|
|
|
|
#define VCE_CMD_SEMAPHORE 0x00000006
|
|
|
|
|
|
|
|
|
|
#endif
|
