License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2005-04-17 05:20:36 +07:00
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/*
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* pci.h
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*
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* PCI defines and function prototypes
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*/
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#ifndef LINUX_PCI_H
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#define LINUX_PCI_H
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2006-04-29 07:46:02 +07:00
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#include <linux/mod_devicetable.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/types.h>
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2008-04-30 03:38:48 +07:00
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#include <linux/init.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/ioport.h>
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#include <linux/list.h>
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2006-08-15 12:43:17 +07:00
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#include <linux/compiler.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/errno.h>
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2008-06-11 04:28:50 +07:00
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#include <linux/kobject.h>
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2011-07-27 06:09:06 +07:00
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#include <linux/atomic.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/device.h>
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2017-04-13 14:06:42 +07:00
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#include <linux/interrupt.h>
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2008-10-22 09:39:55 +07:00
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#include <linux/io.h>
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2015-02-05 12:44:44 +07:00
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#include <linux/resource_ext.h>
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2012-10-13 16:46:48 +07:00
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#include <uapi/linux/pci.h>
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2005-04-17 05:20:36 +07:00
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2006-12-20 04:12:07 +07:00
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#include <linux/pci_ids.h>
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2013-02-28 07:06:45 +07:00
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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* in a single byte as follows:
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*
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* 7:3 = slot
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* 2:0 = function
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2013-11-15 01:28:18 +07:00
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*
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* PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
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2013-02-28 07:06:45 +07:00
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* In the interest of not exposing interfaces to user-space unnecessarily,
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2013-11-15 01:28:18 +07:00
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* the following kernel-only defines are being added here.
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2013-02-28 07:06:45 +07:00
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*/
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2017-12-03 02:21:37 +07:00
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#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
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2013-02-28 07:06:45 +07:00
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/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
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#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
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2008-06-11 04:28:50 +07:00
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/* pci_slot represents a physical slot */
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struct pci_slot {
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2017-12-03 02:21:37 +07:00
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struct pci_bus *bus; /* Bus this slot is on */
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struct list_head list; /* Node in list of slots */
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struct hotplug_slot *hotplug; /* Hotplug info (move here) */
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unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
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struct kobject kobj;
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2008-06-11 04:28:50 +07:00
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};
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2008-10-21 06:41:07 +07:00
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static inline const char *pci_slot_name(const struct pci_slot *slot)
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{
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return kobject_name(&slot->kobj);
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}
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2005-04-17 05:20:36 +07:00
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/* File state for mmap()s on /proc/bus/pci/X/Y */
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enum pci_mmap_state {
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pci_mmap_io,
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pci_mmap_mem
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};
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2017-12-03 02:21:37 +07:00
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/* For PCI devices, the region numbers are assigned this way: */
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2008-11-22 01:39:32 +07:00
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enum {
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/* #0-5: standard PCI resources */
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PCI_STD_RESOURCES,
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PCI_STD_RESOURCE_END = 5,
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/* #6: expansion ROM resource */
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PCI_ROM_RESOURCE,
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2017-12-03 02:21:37 +07:00
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/* Device-specific resources */
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2009-03-20 10:25:11 +07:00
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#ifdef CONFIG_PCI_IOV
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PCI_IOV_RESOURCES,
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PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
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#endif
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2017-12-03 02:21:37 +07:00
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/* Resources assigned to buses behind the bridge */
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2008-11-22 01:39:32 +07:00
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#define PCI_BRIDGE_RESOURCE_NUM 4
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PCI_BRIDGE_RESOURCES,
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PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
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PCI_BRIDGE_RESOURCE_NUM - 1,
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2017-12-03 02:21:37 +07:00
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/* Total resources associated with a PCI device */
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2008-11-22 01:39:32 +07:00
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PCI_NUM_RESOURCES,
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2017-12-03 02:21:37 +07:00
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/* Preserve this for compatibility */
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2012-01-05 06:49:45 +07:00
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DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
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2008-11-22 01:39:32 +07:00
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};
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2005-04-17 05:20:36 +07:00
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2017-08-16 02:02:16 +07:00
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/**
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* enum pci_interrupt_pin - PCI INTx interrupt values
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* @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
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* @PCI_INTERRUPT_INTA: PCI INTA pin
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* @PCI_INTERRUPT_INTB: PCI INTB pin
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* @PCI_INTERRUPT_INTC: PCI INTC pin
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* @PCI_INTERRUPT_INTD: PCI INTD pin
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*
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* Corresponds to values for legacy PCI INTx interrupts, as can be found in the
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* PCI_INTERRUPT_PIN register.
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*/
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enum pci_interrupt_pin {
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PCI_INTERRUPT_UNKNOWN,
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PCI_INTERRUPT_INTA,
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PCI_INTERRUPT_INTB,
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PCI_INTERRUPT_INTC,
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PCI_INTERRUPT_INTD,
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};
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/* The number of legacy PCI INTx interrupts */
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#define PCI_NUM_INTX 4
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2016-06-18 03:23:52 +07:00
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/*
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* pci_power_t values must match the bits in the Capabilities PME_Support
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* and Control/Status PowerState fields in the Power Management capability.
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*/
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2005-04-17 05:20:36 +07:00
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typedef int __bitwise pci_power_t;
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2005-07-29 01:37:33 +07:00
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#define PCI_D0 ((pci_power_t __force) 0)
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#define PCI_D1 ((pci_power_t __force) 1)
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#define PCI_D2 ((pci_power_t __force) 2)
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2005-04-17 05:20:36 +07:00
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#define PCI_D3hot ((pci_power_t __force) 3)
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#define PCI_D3cold ((pci_power_t __force) 4)
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2005-08-18 05:32:19 +07:00
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#define PCI_UNKNOWN ((pci_power_t __force) 5)
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2005-04-17 05:25:24 +07:00
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#define PCI_POWER_ERROR ((pci_power_t __force) -1)
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2005-04-17 05:20:36 +07:00
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2009-04-28 00:33:16 +07:00
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/* Remember to update this when the list above changes! */
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extern const char *pci_power_names[];
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static inline const char *pci_power_name(pci_power_t state)
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{
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2016-06-08 00:48:33 +07:00
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return pci_power_names[1 + (__force int) state];
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2009-04-28 00:33:16 +07:00
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}
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PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 09:23:51 +07:00
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#define PCI_PM_D2_DELAY 200
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#define PCI_PM_D3_WAIT 10
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#define PCI_PM_D3COLD_WAIT 100
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#define PCI_PM_BUS_WAIT 50
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2009-01-17 03:54:43 +07:00
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2017-12-03 02:21:37 +07:00
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/**
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2019-05-14 21:47:24 +07:00
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* typedef pci_channel_state_t
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*
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2017-12-03 02:21:37 +07:00
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* The pci_channel state describes connectivity between the CPU and
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* the PCI device. If some PCI bus between here and the PCI device
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* has crashed or locked up, this info is reflected here.
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2005-11-17 06:10:41 +07:00
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*/
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typedef unsigned int __bitwise pci_channel_state_t;
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enum pci_channel_state {
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/* I/O channel is in normal state */
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pci_channel_io_normal = (__force pci_channel_state_t) 1,
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/* I/O to channel is blocked */
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pci_channel_io_frozen = (__force pci_channel_state_t) 2,
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/* PCI card is dead */
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pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
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};
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2007-04-07 04:39:36 +07:00
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typedef unsigned int __bitwise pcie_reset_state_t;
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enum pcie_reset_state {
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/* Reset is NOT asserted (Use to deassert reset) */
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pcie_deassert_reset = (__force pcie_reset_state_t) 1,
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2013-11-15 01:28:18 +07:00
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/* Use #PERST to reset PCIe device */
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2007-04-07 04:39:36 +07:00
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pcie_warm_reset = (__force pcie_reset_state_t) 2,
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2013-11-15 01:28:18 +07:00
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/* Use PCIe Hot Reset to reset device */
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2007-04-07 04:39:36 +07:00
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pcie_hot_reset = (__force pcie_reset_state_t) 3
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};
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2007-10-25 15:16:30 +07:00
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typedef unsigned short __bitwise pci_dev_flags_t;
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enum pci_dev_flags {
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2017-12-03 02:21:37 +07:00
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/* INTX_DISABLE in PCI_COMMAND register disables MSI too */
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2014-05-23 06:07:36 +07:00
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PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
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2008-07-24 23:18:38 +07:00
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/* Device configuration is irrevocably lost if disabled into D3 */
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2014-05-23 06:07:36 +07:00
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PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
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2011-07-22 12:46:07 +07:00
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/* Provide indication device is assigned by a Virtual Machine Manager */
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2014-05-23 06:07:36 +07:00
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PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
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2014-02-04 04:27:39 +07:00
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/* Flag for quirk use to store if quirk-specific ACS is enabled */
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2014-05-23 06:07:36 +07:00
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PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
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2014-05-29 03:57:02 +07:00
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/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
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PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
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2015-01-16 07:16:04 +07:00
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/* Do not use bus resets for device */
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PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
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2014-11-22 01:24:08 +07:00
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/* Do not use PM reset even if device advertises NoSoftRst- */
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PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
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2015-07-14 01:40:02 +07:00
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|
|
/* Get VPD from function 0 VPD */
|
|
|
|
PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
|
2017-12-03 02:21:37 +07:00
|
|
|
/* A non-root bridge where translation occurs, stop alias search here */
|
2017-04-14 03:30:44 +07:00
|
|
|
PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
|
2017-04-04 04:02:50 +07:00
|
|
|
/* Do not use FLR even if device advertises PCI_AF_CAP */
|
|
|
|
PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
|
2017-08-15 10:23:23 +07:00
|
|
|
/* Don't use Relaxed Ordering for TLPs directed at this device */
|
2017-10-25 19:16:46 +07:00
|
|
|
PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
|
2007-10-25 15:16:30 +07:00
|
|
|
};
|
|
|
|
|
2008-06-11 21:35:17 +07:00
|
|
|
enum pci_irq_reroute_variant {
|
|
|
|
INTEL_IRQ_REROUTE_VARIANT = 1,
|
|
|
|
MAX_IRQ_REROUTE_VARIANTS = 3
|
|
|
|
};
|
|
|
|
|
2006-02-14 23:52:22 +07:00
|
|
|
typedef unsigned short __bitwise pci_bus_flags_t;
|
|
|
|
enum pci_bus_flags {
|
2016-08-26 06:26:10 +07:00
|
|
|
PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
|
|
|
|
PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
|
|
|
|
PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
|
PCI: Check whether bridges allow access to extended config space
Even if a device supports extended config space, i.e., it is a PCI-X Mode 2
or a PCI Express device, the extended space may not be accessible if
there's a conventional PCI bus in the path to it.
We currently figure that out in pci_cfg_space_size() by reading the first
dword of extended config space. On most platforms that returns ~0 data if
the space is inaccessible, but it may set error bits in PCI status
registers, and on some platforms it causes exceptions that we currently
don't recover from.
For example, a PCIe-to-conventional PCI bridge treats config transactions
with a non-zero Extended Register Address as an Unsupported Request on PCIe
and a received Master-Abort on the destination bus (see PCI Express to
PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the
following bus topology:
LS1043 PCIe Root Port
-> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)
-> PMC slot connector (for legacy PMC modules)
With a PMC module topology as follows:
PMC connector
-> PCI-to-PCIe bridge
-> PCIe switch (4 ports)
-> 4 PCIe devices (one on each port)
The PCIe devices on the PMC module support extended config space, but we
can't reach it because the PEX8112 can't generate accesses to the extended
space on its secondary bus. Attempts to access it cause Unsupported
Request errors, which result in synchronous aborts on this platform.
To avoid these errors, check whether bridges are capable of generating
extended config space addresses on their secondary interfaces. If they
can't, we restrict devices below the bridge to only the 256-byte
PCI-compatible config space.
Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
[bhelgaas: changelog, rework patch so bus_flags testing is all in
pci_bridge_child_ext_cfg_accessible()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-05-04 03:21:44 +07:00
|
|
|
PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
|
2006-02-14 23:52:22 +07:00
|
|
|
};
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
|
2013-07-31 13:53:21 +07:00
|
|
|
enum pcie_link_width {
|
|
|
|
PCIE_LNK_WIDTH_RESRV = 0x00,
|
|
|
|
PCIE_LNK_X1 = 0x01,
|
|
|
|
PCIE_LNK_X2 = 0x02,
|
|
|
|
PCIE_LNK_X4 = 0x04,
|
|
|
|
PCIE_LNK_X8 = 0x08,
|
2017-12-03 02:21:37 +07:00
|
|
|
PCIE_LNK_X12 = 0x0c,
|
2013-07-31 13:53:21 +07:00
|
|
|
PCIE_LNK_X16 = 0x10,
|
|
|
|
PCIE_LNK_X32 = 0x20,
|
2017-12-03 02:21:37 +07:00
|
|
|
PCIE_LNK_WIDTH_UNKNOWN = 0xff,
|
2013-07-31 13:53:21 +07:00
|
|
|
};
|
|
|
|
|
2009-12-13 20:11:31 +07:00
|
|
|
/* Based on the PCI Hotplug Spec, but some values are made up by us */
|
|
|
|
enum pci_bus_speed {
|
|
|
|
PCI_SPEED_33MHz = 0x00,
|
|
|
|
PCI_SPEED_66MHz = 0x01,
|
|
|
|
PCI_SPEED_66MHz_PCIX = 0x02,
|
|
|
|
PCI_SPEED_100MHz_PCIX = 0x03,
|
|
|
|
PCI_SPEED_133MHz_PCIX = 0x04,
|
|
|
|
PCI_SPEED_66MHz_PCIX_ECC = 0x05,
|
|
|
|
PCI_SPEED_100MHz_PCIX_ECC = 0x06,
|
|
|
|
PCI_SPEED_133MHz_PCIX_ECC = 0x07,
|
|
|
|
PCI_SPEED_66MHz_PCIX_266 = 0x09,
|
|
|
|
PCI_SPEED_100MHz_PCIX_266 = 0x0a,
|
|
|
|
PCI_SPEED_133MHz_PCIX_266 = 0x0b,
|
2009-12-13 20:11:34 +07:00
|
|
|
AGP_UNKNOWN = 0x0c,
|
|
|
|
AGP_1X = 0x0d,
|
|
|
|
AGP_2X = 0x0e,
|
|
|
|
AGP_4X = 0x0f,
|
|
|
|
AGP_8X = 0x10,
|
2009-12-13 20:11:31 +07:00
|
|
|
PCI_SPEED_66MHz_PCIX_533 = 0x11,
|
|
|
|
PCI_SPEED_100MHz_PCIX_533 = 0x12,
|
|
|
|
PCI_SPEED_133MHz_PCIX_533 = 0x13,
|
|
|
|
PCIE_SPEED_2_5GT = 0x14,
|
|
|
|
PCIE_SPEED_5_0GT = 0x15,
|
2009-12-13 20:11:35 +07:00
|
|
|
PCIE_SPEED_8_0GT = 0x16,
|
2018-03-12 16:13:32 +07:00
|
|
|
PCIE_SPEED_16_0GT = 0x17,
|
2019-06-04 23:24:43 +07:00
|
|
|
PCIE_SPEED_32_0GT = 0x18,
|
2009-12-13 20:11:31 +07:00
|
|
|
PCI_SPEED_UNKNOWN = 0xff,
|
|
|
|
};
|
|
|
|
|
2018-06-26 01:17:41 +07:00
|
|
|
enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
|
|
|
|
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
|
|
|
|
|
2011-05-10 23:02:11 +07:00
|
|
|
struct pci_cap_saved_data {
|
2017-12-03 02:21:37 +07:00
|
|
|
u16 cap_nr;
|
|
|
|
bool cap_extended;
|
|
|
|
unsigned int size;
|
|
|
|
u32 data[0];
|
2006-02-08 16:11:38 +07:00
|
|
|
};
|
|
|
|
|
2011-05-10 23:02:11 +07:00
|
|
|
struct pci_cap_saved_state {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct hlist_node next;
|
|
|
|
struct pci_cap_saved_data cap;
|
2011-05-10 23:02:11 +07:00
|
|
|
};
|
|
|
|
|
2016-11-09 08:15:05 +07:00
|
|
|
struct irq_affinity;
|
PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-25 08:46:41 +07:00
|
|
|
struct pcie_link_state;
|
2008-04-29 02:30:35 +07:00
|
|
|
struct pci_vpd;
|
2009-03-20 10:25:11 +07:00
|
|
|
struct pci_sriov;
|
2009-05-18 12:51:32 +07:00
|
|
|
struct pci_ats;
|
PCI/P2PDMA: Support peer-to-peer memory
Some PCI devices may have memory mapped in a BAR space that's intended for
use in peer-to-peer transactions. To enable such transactions the memory
must be registered with ZONE_DEVICE pages so it can be used by DMA
interfaces in existing drivers.
Add an interface for other subsystems to find and allocate chunks of P2P
memory as necessary to facilitate transfers between two PCI peers:
struct pci_dev *pci_p2pmem_find[_many]();
int pci_p2pdma_distance[_many]();
void *pci_alloc_p2pmem();
The new interface requires a driver to collect a list of client devices
involved in the transaction then call pci_p2pmem_find() to obtain any
suitable P2P memory. Alternatively, if the caller knows a device which
provides P2P memory, they can use pci_p2pdma_distance() to determine if it
is usable. With a suitable p2pmem device, memory can then be allocated
with pci_alloc_p2pmem() for use in DMA transactions.
Depending on hardware, using peer-to-peer memory may reduce the bandwidth
of the transfer but can significantly reduce pressure on system memory.
This may be desirable in many cases: for example a system could be designed
with a small CPU connected to a PCIe switch by a small number of lanes
which would maximize the number of lanes available to connect to NVMe
devices.
The code is designed to only utilize the p2pmem device if all the devices
involved in a transfer are behind the same PCI bridge. This is because we
have no way of knowing whether peer-to-peer routing between PCIe Root Ports
is supported (PCIe r4.0, sec 1.3.1). Additionally, the benefits of P2P
transfers that go through the RC is limited to only reducing DRAM usage
and, in some cases, coding convenience. The PCI-SIG may be exploring
adding a new capability bit to advertise whether this is possible for
future hardware.
This commit includes significant rework and feedback from Christoph
Hellwig.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: fold in fix from Keith Busch <keith.busch@intel.com>:
https://lore.kernel.org/linux-pci/20181012155920.15418-1-keith.busch@intel.com,
to address comment from Dan Carpenter <dan.carpenter@oracle.com>, fold in
https://lore.kernel.org/linux-pci/20181017160510.17926-1-logang@deltatee.com]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-10-05 04:27:35 +07:00
|
|
|
struct pci_p2pdma;
|
2008-04-29 02:30:35 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* The pci_dev structure describes PCI devices */
|
2005-04-17 05:20:36 +07:00
|
|
|
struct pci_dev {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct list_head bus_list; /* Node in per-bus list */
|
|
|
|
struct pci_bus *bus; /* Bus this device is on */
|
|
|
|
struct pci_bus *subordinate; /* Bus this device bridges to */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
void *sysdata; /* Hook for sys-specific extension */
|
|
|
|
struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
|
2008-06-11 04:28:50 +07:00
|
|
|
struct pci_slot *slot; /* Physical slot this device is in */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int devfn; /* Encoded device & function index */
|
2005-04-17 05:20:36 +07:00
|
|
|
unsigned short vendor;
|
|
|
|
unsigned short device;
|
|
|
|
unsigned short subsystem_vendor;
|
|
|
|
unsigned short subsystem_device;
|
|
|
|
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
|
2007-06-09 05:46:30 +07:00
|
|
|
u8 revision; /* PCI revision, low byte of class word */
|
2005-04-17 05:20:36 +07:00
|
|
|
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
|
2016-09-28 03:23:34 +07:00
|
|
|
#ifdef CONFIG_PCIEAER
|
|
|
|
u16 aer_cap; /* AER capability offset */
|
2018-07-01 03:07:17 +07:00
|
|
|
struct aer_stats *aer_stats; /* AER stats for this device */
|
2016-09-28 03:23:34 +07:00
|
|
|
#endif
|
2013-11-15 01:28:18 +07:00
|
|
|
u8 pcie_cap; /* PCIe capability offset */
|
2013-04-04 23:54:30 +07:00
|
|
|
u8 msi_cap; /* MSI capability offset */
|
|
|
|
u8 msix_cap; /* MSI-X capability offset */
|
2013-11-15 01:28:18 +07:00
|
|
|
u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
|
2017-12-03 02:21:37 +07:00
|
|
|
u8 rom_base_reg; /* Config register controlling ROM */
|
|
|
|
u8 pin; /* Interrupt pin this device uses */
|
|
|
|
u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
|
|
|
|
unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
struct pci_driver *driver; /* Driver bound to this device */
|
2005-04-17 05:20:36 +07:00
|
|
|
u64 dma_mask; /* Mask of the bits of bus address this
|
|
|
|
device implements. Normally this is
|
|
|
|
0xffffffff. You only need to change
|
|
|
|
this if your device has broken DMA
|
|
|
|
or supports 64-bit transfers. */
|
|
|
|
|
2008-02-05 13:27:55 +07:00
|
|
|
struct device_dma_parameters dma_parms;
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
pci_power_t current_state; /* Current operating state. In ACPI,
|
|
|
|
this is D0-D3, D0 being fully
|
|
|
|
functional, and D3 being off. */
|
2018-09-07 13:16:51 +07:00
|
|
|
unsigned int imm_ready:1; /* Supports Immediate Readiness */
|
2013-04-18 05:57:56 +07:00
|
|
|
u8 pm_cap; /* PM capability offset */
|
2008-07-07 08:36:24 +07:00
|
|
|
unsigned int pme_support:5; /* Bitmask of states from which PME#
|
|
|
|
can be generated */
|
PCI / PM: Extend PME polling to all PCI devices
The land of PCI power management is a land of sorrow and ugliness,
especially in the area of signaling events by devices. There are
devices that set their PME Status bits, but don't really bother
to send a PME message or assert PME#. There are hardware vendors
who don't connect PME# lines to the system core logic (they know
who they are). There are PCI Express Root Ports that don't bother
to trigger interrupts when they receive PME messages from the devices
below. There are ACPI BIOSes that forget to provide _PRW methods for
devices capable of signaling wakeup. Finally, there are BIOSes that
do provide _PRW methods for such devices, but then don't bother to
call Notify() for those devices from the corresponding _Lxx/_Exx
GPE-handling methods. In all of these cases the kernel doesn't have
a chance to receive a proper notification that it should wake up a
device, so devices stay in low-power states forever. Worse yet, in
some cases they continuously send PME Messages that are silently
ignored, because the kernel simply doesn't know that it should clear
the device's PME Status bit.
This problem was first observed for "parallel" (non-Express) PCI
devices on add-on cards and Matthew Garrett addressed it by adding
code that polls PME Status bits of such devices, if they are enabled
to signal PME, to the kernel. Recently, however, it has turned out
that PCI Express devices are also affected by this issue and that it
is not limited to add-on devices, so it seems necessary to extend
the PME polling to all PCI devices, including PCI Express and planar
ones. Still, it would be wasteful to poll the PME Status bits of
devices that are known to receive proper PME notifications, so make
the kernel (1) poll the PME Status bits of all PCI and PCIe devices
enabled to signal PME and (2) disable the PME Status polling for
devices for which correct PME notifications are received.
Tested-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-04 04:16:33 +07:00
|
|
|
unsigned int pme_poll:1; /* Poll device's PME status bit */
|
2008-07-07 08:36:24 +07:00
|
|
|
unsigned int d1_support:1; /* Low power state D1 is supported */
|
|
|
|
unsigned int d2_support:1; /* Low power state D2 is supported */
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 09:23:51 +07:00
|
|
|
unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
|
|
|
|
unsigned int no_d3cold:1; /* D3cold is forbidden */
|
2016-06-02 15:17:12 +07:00
|
|
|
unsigned int bridge_d3:1; /* Allow D3 for bridge */
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 09:23:51 +07:00
|
|
|
unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int mmio_always_on:1; /* Disallow turning off io/mem
|
|
|
|
decoding during BAR sizing */
|
2009-09-09 04:14:49 +07:00
|
|
|
unsigned int wakeup_prepared:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int runtime_d3cold:1; /* Whether go through runtime
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 09:23:51 +07:00
|
|
|
D3cold, not set for devices
|
|
|
|
powered on/off by the
|
|
|
|
corresponding bridge */
|
PCI: PM: Avoid possible suspend-to-idle issue
If a PCI driver leaves the device handled by it in D0 and calls
pci_save_state() on the device in its ->suspend() or ->suspend_late()
callback, it can expect the device to stay in D0 over the whole
s2idle cycle. However, that may not be the case if there is a
spurious wakeup while the system is suspended, because in that case
pci_pm_suspend_noirq() will run again after pci_pm_resume_noirq()
which calls pci_restore_state(), via pci_pm_default_resume_early(),
so state_saved is cleared and the second iteration of
pci_pm_suspend_noirq() will invoke pci_prepare_to_sleep() which
may change the power state of the device.
To avoid that, add a new internal flag, skip_bus_pm, that will be set
by pci_pm_suspend_noirq() when it runs for the first time during the
given system suspend-resume cycle if the state of the device has
been saved already and the device is still in D0. Setting that flag
will cause the next iterations of pci_pm_suspend_noirq() to set
state_saved for pci_pm_resume_noirq(), so that it always restores the
device state from the originally saved data, and avoid calling
pci_prepare_to_sleep() for the device.
Fixes: 33e4f80ee69b ("ACPI / PM: Ignore spurious SCI wakeups from suspend-to-idle")
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-05-17 16:08:50 +07:00
|
|
|
unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
|
PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device
Powering off a hot-pluggable device, e.g., with pci_set_power_state(D3cold),
normally generates a hot-remove event that unbinds the driver.
Some drivers expect to remain bound to a device even while they power it
off and back on again. This can be dangerous, because if the device is
removed or replaced while it is powered off, the driver doesn't know that
anything changed. But some drivers accept that risk.
Add pci_ignore_hotplug() for use by drivers that know their device cannot
be removed. Using pci_ignore_hotplug() tells the PCI core that hot-plug
events for the device should be ignored.
The radeon and nouveau drivers use this to switch between a low-power,
integrated GPU and a higher-power, higher-performance discrete GPU. They
power off the unused GPU, but they want to remain bound to it.
This is a reimplementation of f244d8b623da ("ACPIPHP / radeon / nouveau:
Fix VGA switcheroo problem related to hotplug") but extends it to work with
both acpiphp and pciehp.
This fixes a problem where systems with dual GPUs using the radeon drivers
become unusable, freezing every few seconds (see bugzillas below). The
resume of the radeon device may also fail, e.g.,
This fixes problems on dual GPU systems where the radeon driver becomes
unusable because of problems while suspending the device, as in bug 79701:
[drm] radeon: finishing device.
radeon 0000:01:00.0: Userspace still has active objects !
radeon 0000:01:00.0: ffff8800cb4ec288 ffff8800cb4ec000 16384 4294967297 force free
...
WARNING: CPU: 0 PID: 67 at /home/apw/COD/linux/drivers/gpu/drm/radeon/radeon_gart.c:234 radeon_gart_unbind+0xd2/0xe0 [radeon]()
trying to unbind memory from uninitialized GART !
or while resuming it, as in bug 77261:
radeon 0000:01:00.0: ring 0 stalled for more than 10158msec
radeon 0000:01:00.0: GPU lockup ...
radeon 0000:01:00.0: GPU pci config reset
pciehp 0000:00:01.0:pcie04: Card not present on Slot(1-1)
radeon 0000:01:00.0: GPU reset succeeded, trying to resume
*ERROR* radeon: dpm resume failed
radeon 0000:01:00.0: Wait for MC idle timedout !
Link: https://bugzilla.kernel.org/show_bug.cgi?id=77261
Link: https://bugzilla.kernel.org/show_bug.cgi?id=79701
Reported-by: Shawn Starr <shawn.starr@rogers.com>
Reported-by: Jose P. <lbdkmjdf@sharklasers.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Rajat Jain <rajatxjain@gmail.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Dave Airlie <airlied@redhat.com>
CC: stable@vger.kernel.org # v3.15+
2014-09-11 02:45:01 +07:00
|
|
|
unsigned int ignore_hotplug:1; /* Ignore hotplug events */
|
PCI: pciehp: Allow exclusive userspace control of indicators
PCIe hotplug supports optional Attention and Power Indicators, which are
used internally by pciehp. Users can't control the Power Indicator, but
they can control the Attention Indicator by writing to a sysfs "attention"
file.
The Slot Control register has two bits for each indicator, and the PCIe
spec defines the encodings for each as (Reserved/On/Blinking/Off). For
sysfs "attention" writes, pciehp_set_attention_status() maps into these
encodings, so the only useful write values are 0 (Off), 1 (On), and 2
(Blinking).
However, some platforms use all four bits for platform-specific indicators,
and they need to allow direct user control of them while preventing pciehp
from using them at all.
Add a "hotplug_user_indicators" flag to the pci_dev structure. When set,
pciehp does not use either the Attention Indicator or the Power Indicator,
and the low four bits (values 0x0 - 0xf) of sysfs "attention" write values
are written directly to the Attention Indicator Control and Power Indicator
Control fields.
[bhelgaas: changelog, rename flag and accessors to s/attention/indicator/]
Signed-off-by: Keith Busch <keith.busch@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-09-13 23:31:59 +07:00
|
|
|
unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
|
|
|
|
controlled exclusively by
|
|
|
|
user sysfs */
|
2019-03-30 00:07:35 +07:00
|
|
|
unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
|
|
|
|
bit manually */
|
2009-12-31 18:15:54 +07:00
|
|
|
unsigned int d3_delay; /* D3->D0 transition time in ms */
|
PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform
support. This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.
D3cold is the deepest power saving state for a PCIe device, where its main
power is removed. While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.
To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal. WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.
Some devices, such as those in plug-in slots, have no direct platform
logic. For example, there is usually no ACPI _PR3 for them. D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device. When the PCIe port is powered on/off, the device is powered
on/off too. Wakeup events from the device will be notified to the
corresponding PCIe port.
For more information about PCIe D3cold and corresponding ACPI support,
please refer to:
- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0
[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-23 09:23:51 +07:00
|
|
|
unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-25 08:46:41 +07:00
|
|
|
#ifdef CONFIG_PCIEASPM
|
2013-11-15 01:28:18 +07:00
|
|
|
struct pcie_link_state *link_state; /* ASPM link state */
|
2017-11-29 05:43:50 +07:00
|
|
|
unsigned int ltr_path:1; /* Latency Tolerance Reporting
|
|
|
|
supported from root to here */
|
PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-25 08:46:41 +07:00
|
|
|
#endif
|
2018-06-30 22:24:24 +07:00
|
|
|
unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
|
PCI: add PCI Express ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Note: some devices might not work well with aspm, either because chipset
issue or device issue. The patch provide API (pci_disable_link_state),
driver can disable ASPM for specific device.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2008-02-25 08:46:41 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
pci_channel_state_t error_state; /* Current connectivity state */
|
|
|
|
struct device dev; /* Generic device interface */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
int cfg_size; /* Size of config space */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Instead of touching interrupt line and base address registers
|
|
|
|
* directly, use the values stored here. They might be different!
|
|
|
|
*/
|
|
|
|
unsigned int irq;
|
|
|
|
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
bool match_driver; /* Skip attaching driver */
|
|
|
|
|
|
|
|
unsigned int transparent:1; /* Subtractive decode bridge */
|
2019-01-20 00:35:04 +07:00
|
|
|
unsigned int io_window:1; /* Bridge has I/O window */
|
|
|
|
unsigned int pref_window:1; /* Bridge has pref mem window */
|
|
|
|
unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int multifunction:1; /* Multi-function device */
|
|
|
|
|
|
|
|
unsigned int is_busmaster:1; /* Is busmaster */
|
|
|
|
unsigned int no_msi:1; /* May not use MSI */
|
2019-05-30 20:05:58 +07:00
|
|
|
unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int block_cfg_access:1; /* Config space access blocked */
|
|
|
|
unsigned int broken_parity_status:1; /* Generates false positive parity */
|
|
|
|
unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
|
2013-11-15 01:28:18 +07:00
|
|
|
unsigned int msi_enabled:1;
|
2006-05-26 09:58:27 +07:00
|
|
|
unsigned int msix_enabled:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int ari_enabled:1; /* ARI forwarding */
|
|
|
|
unsigned int ats_enabled:1; /* Address Translation Svc */
|
2017-05-30 23:25:48 +07:00
|
|
|
unsigned int pasid_enabled:1; /* Process Address Space ID */
|
|
|
|
unsigned int pri_enabled:1; /* Page Request Interface */
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 14:00:26 +07:00
|
|
|
unsigned int is_managed:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int needs_freset:1; /* Requires fundamental reset */
|
2009-01-17 03:54:43 +07:00
|
|
|
unsigned int state_saved:1;
|
2009-03-20 10:25:11 +07:00
|
|
|
unsigned int is_physfn:1;
|
2009-03-20 10:25:15 +07:00
|
|
|
unsigned int is_virtfn:1;
|
2009-07-28 03:37:48 +07:00
|
|
|
unsigned int reset_fn:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int is_hotplug_bridge:1;
|
2018-06-26 04:49:06 +07:00
|
|
|
unsigned int shpc_managed:1; /* SHPC owned by shpchp */
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int is_thunderbolt:1; /* Thunderbolt controller */
|
2018-08-16 16:28:48 +07:00
|
|
|
/*
|
|
|
|
* Devices marked being untrusted are the ones that can potentially
|
|
|
|
* execute DMA attacks and similar. They are typically connected
|
|
|
|
* through external ports such as Thunderbolt but not limited to
|
|
|
|
* that. When an IOMMU is enabled they should be getting full
|
|
|
|
* mappings to make sure they cannot access arbitrary memory.
|
|
|
|
*/
|
|
|
|
unsigned int untrusted:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int __aer_firmware_first_valid:1;
|
2010-05-18 13:35:16 +07:00
|
|
|
unsigned int __aer_firmware_first:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int broken_intx_masking:1; /* INTx masking can't be used */
|
|
|
|
unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
|
2014-10-27 12:21:42 +07:00
|
|
|
unsigned int irq_managed:1;
|
PCI: Add dev->has_secondary_link to track downstream PCIe links
A PCIe Port is an interface to a Link. A Root Port is a PCI-PCI bridge in
a Root Complex and has a Link on its secondary (downstream) side. For
other Ports, the Link may be on either the upstream (closer to the Root
Complex) or downstream side of the Port.
The usual topology has a Root Port connected to an Upstream Port. We
previously assumed this was the only possible topology, and that a
Downstream Port's Link was always on its downstream side, like this:
+---------------------+
+------+ | Downstream |
| Root | | Upstream Port +--Link--
| Port +--Link--+ Port |
+------+ | Downstream |
| Port +--Link--
+---------------------+
But systems do exist (see URL below) where the Root Port is connected to a
Downstream Port. In this case, a Downstream Port's Link may be on either
the upstream or downstream side:
+---------------------+
+------+ | Upstream |
| Root | | Downstream Port +--Link--
| Port +--Link--+ Port |
+------+ | Downstream |
| Port +--Link--
+---------------------+
We can't use the Port type to determine which side the Link is on, so add a
bit in struct pci_dev to keep track.
A Root Port's Link is always on the Port's secondary side. A component
(Endpoint or Port) on the other end of the Link obviously has the Link on
its upstream side. If that component is a Port, it is part of a Switch or
a Bridge. A Bridge has a PCI or PCI-X bus on its secondary side, not a
Link. The internal bus of a Switch connects the Port to another Port whose
Link is on the downstream side.
[bhelgaas: changelog, comment, cache "type", use if/else]
Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-05-21 14:05:02 +07:00
|
|
|
unsigned int has_secondary_link:1;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
|
|
|
|
unsigned int is_probed:1; /* Device probing in progress */
|
2018-09-20 23:27:17 +07:00
|
|
|
unsigned int link_active_reporting:1;/* Device capable of reporting link active */
|
2018-12-21 21:14:19 +07:00
|
|
|
unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_dev_flags_t dev_flags;
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-23 03:40:31 +07:00
|
|
|
atomic_t enable_cnt; /* pci_enable_device has been called */
|
2005-08-17 05:15:58 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
u32 saved_config_space[16]; /* Config space saved at suspend time */
|
2006-02-08 16:11:38 +07:00
|
|
|
struct hlist_head saved_cap_space;
|
2017-12-03 02:21:37 +07:00
|
|
|
struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
|
|
|
|
int rom_attr_enabled; /* Display of ROM attribute enabled? */
|
2005-04-17 05:20:36 +07:00
|
|
|
struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
|
2008-03-19 07:00:22 +07:00
|
|
|
struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
|
2016-06-12 02:13:38 +07:00
|
|
|
|
PCI: pciehp: Add quirk for Command Completed errata
Several PCIe hotplug controllers have errata that mean they do not set the
Command Completed bit unless writes to the Slot Command register change
"Control" bits. Command Completed is never set for writes that only change
software notification "Enable" bits. This results in timeouts like this:
pciehp 0000:00:1c.0:pcie004: Timeout on hotplug command 0x1038 (issued 65284 msec ago)
When this erratum is present, avoid these timeouts by marking commands
"completed" immediately unless they change the "Control" bits.
Here's the text of the Intel erratum CF118. We assume this applies to all
Intel parts:
CF118 PCIe Slot Status Register Command Completed bit not always
updated on any configuration write to the Slot Control
Register
Problem: For PCIe root ports (devices 0 - 10) supporting hot-plug,
the Slot Status Register (offset AAh) Command Completed
(bit[4]) status is updated under the following condition:
IOH will set Command Completed bit after delivering the new
commands written in the Slot Controller register (offset
A8h) to VPP. The IOH detects new commands written in Slot
Control register by checking the change of value for Power
Controller Control (bit[10]), Power Indicator Control
(bits[9:8]), Attention Indicator Control (bits[7:6]), or
Electromechanical Interlock Control (bit[11]) fields. Any
other configuration writes to the Slot Control register
without changing the values of these fields will not cause
Command Completed bit to be set.
The PCIe Base Specification Revision 2.0 or later describes
the “Slot Control Register” in section 7.8.10, as follows
(Reference section 7.8.10, Slot Control Register, Offset
18h). In hot-plug capable Downstream Ports, a write to the
Slot Control register must cause a hot-plug command to be
generated (see Section 6.7.3.2 for details on hot-plug
commands). A write to the Slot Control register in a
Downstream Port that is not hotplug capable must not cause a
hot-plug command to be executed.
The PCIe Spec intended that every write to the Slot Control
Register is a command and expected a command complete status
to abstract the VPP implementation specific nuances from the
OS software. IOH PCIe Slot Control Register implementation
is not fully conforming to the PCIe Specification in this
respect.
Implication: Software checking on the Command Completed status after
writing to the Slot Control register may time out.
Workaround: Software can read the Slot Control register and compare the
existing and new values to determine if it should check the
Command Completed status after writing to the Slot Control
register.
Per Sinan, the Qualcomm QDF2400 controller also does not set the Command
Completed bit unless writes to the Slot Command register change "Control"
bits.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Link: https://lkml.kernel.org/r/8770820b-85a0-172b-7230-3a44524e6c9f@molgen.mpg.de
Reported-by: Paul Menzel <pmenzel+linux-pci@molgen.mpg.de> # Lenovo X60
Tested-by: Paul Menzel <pmenzel+linux-pci@molgen.mpg.de> # Lenovo X60
Signed-off-by: Sinan Kaya <okaya@codeaurora.org> # Qcom quirk
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-05-04 06:39:38 +07:00
|
|
|
#ifdef CONFIG_HOTPLUG_PCI_PCIE
|
|
|
|
unsigned int broken_cmd_compl:1; /* No compl for some cmds */
|
|
|
|
#endif
|
2016-06-12 02:13:38 +07:00
|
|
|
#ifdef CONFIG_PCIE_PTM
|
|
|
|
unsigned int ptm_root:1;
|
|
|
|
unsigned int ptm_enabled:1;
|
2016-06-13 04:26:40 +07:00
|
|
|
u8 ptm_granularity;
|
2016-06-12 02:13:38 +07:00
|
|
|
#endif
|
2007-01-29 02:42:52 +07:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
2013-12-20 03:30:17 +07:00
|
|
|
const struct attribute_group **msi_irq_groups;
|
2007-01-29 02:42:52 +07:00
|
|
|
#endif
|
2008-03-05 23:52:39 +07:00
|
|
|
struct pci_vpd *vpd;
|
2011-10-30 22:35:08 +07:00
|
|
|
#ifdef CONFIG_PCI_ATS
|
2009-03-20 10:25:15 +07:00
|
|
|
union {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct pci_sriov *sriov; /* PF: SR-IOV info */
|
|
|
|
struct pci_dev *physfn; /* VF: related PF */
|
2009-03-20 10:25:15 +07:00
|
|
|
};
|
2015-07-18 03:27:34 +07:00
|
|
|
u16 ats_cap; /* ATS Capability offset */
|
|
|
|
u8 ats_stu; /* ATS Smallest Translation Unit */
|
2017-12-03 02:21:37 +07:00
|
|
|
atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
|
2017-05-30 23:25:49 +07:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_PRI
|
|
|
|
u32 pri_reqs_alloc; /* Number of PRI requests allocated */
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_PASID
|
|
|
|
u16 pasid_features;
|
PCI/P2PDMA: Support peer-to-peer memory
Some PCI devices may have memory mapped in a BAR space that's intended for
use in peer-to-peer transactions. To enable such transactions the memory
must be registered with ZONE_DEVICE pages so it can be used by DMA
interfaces in existing drivers.
Add an interface for other subsystems to find and allocate chunks of P2P
memory as necessary to facilitate transfers between two PCI peers:
struct pci_dev *pci_p2pmem_find[_many]();
int pci_p2pdma_distance[_many]();
void *pci_alloc_p2pmem();
The new interface requires a driver to collect a list of client devices
involved in the transaction then call pci_p2pmem_find() to obtain any
suitable P2P memory. Alternatively, if the caller knows a device which
provides P2P memory, they can use pci_p2pdma_distance() to determine if it
is usable. With a suitable p2pmem device, memory can then be allocated
with pci_alloc_p2pmem() for use in DMA transactions.
Depending on hardware, using peer-to-peer memory may reduce the bandwidth
of the transfer but can significantly reduce pressure on system memory.
This may be desirable in many cases: for example a system could be designed
with a small CPU connected to a PCIe switch by a small number of lanes
which would maximize the number of lanes available to connect to NVMe
devices.
The code is designed to only utilize the p2pmem device if all the devices
involved in a transfer are behind the same PCI bridge. This is because we
have no way of knowing whether peer-to-peer routing between PCIe Root Ports
is supported (PCIe r4.0, sec 1.3.1). Additionally, the benefits of P2P
transfers that go through the RC is limited to only reducing DRAM usage
and, in some cases, coding convenience. The PCI-SIG may be exploring
adding a new capability bit to advertise whether this is possible for
future hardware.
This commit includes significant rework and feedback from Christoph
Hellwig.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Logan Gunthorpe <logang@deltatee.com>
[bhelgaas: fold in fix from Keith Busch <keith.busch@intel.com>:
https://lore.kernel.org/linux-pci/20181012155920.15418-1-keith.busch@intel.com,
to address comment from Dan Carpenter <dan.carpenter@oracle.com>, fold in
https://lore.kernel.org/linux-pci/20181017160510.17926-1-logang@deltatee.com]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-10-05 04:27:35 +07:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_P2PDMA
|
|
|
|
struct pci_p2pdma *p2pdma;
|
2009-03-20 10:25:11 +07:00
|
|
|
#endif
|
2017-12-03 02:21:37 +07:00
|
|
|
phys_addr_t rom; /* Physical address if not from BAR */
|
|
|
|
size_t romlen; /* Length if not from BAR */
|
|
|
|
char *driver_override; /* Driver name to force a match */
|
2017-03-30 10:48:59 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned long priv_flags; /* Private flags for the PCI driver */
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2010-04-09 07:07:55 +07:00
|
|
|
static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
if (dev->is_virtfn)
|
|
|
|
dev = dev->physfn;
|
|
|
|
#endif
|
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
2013-05-25 20:48:30 +07:00
|
|
|
struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
|
2007-04-05 14:19:08 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
|
|
|
|
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
|
|
|
|
|
2006-12-13 05:55:59 +07:00
|
|
|
static inline int pci_channel_offline(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return (pdev->error_state != pci_channel_io_normal);
|
|
|
|
}
|
|
|
|
|
2012-02-24 10:18:59 +07:00
|
|
|
struct pci_host_bridge {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct device dev;
|
|
|
|
struct pci_bus *bus; /* Root bus */
|
|
|
|
struct pci_ops *ops;
|
|
|
|
void *sysdata;
|
|
|
|
int busnr;
|
2015-02-05 12:44:44 +07:00
|
|
|
struct list_head windows; /* resource_entry */
|
2019-05-03 21:05:32 +07:00
|
|
|
struct list_head dma_ranges; /* dma ranges resource list */
|
2017-12-03 02:21:37 +07:00
|
|
|
u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
|
2017-06-29 03:14:02 +07:00
|
|
|
int (*map_irq)(const struct pci_dev *, u8, u8);
|
2012-04-03 08:31:53 +07:00
|
|
|
void (*release_fn)(struct pci_host_bridge *);
|
2017-12-03 02:21:37 +07:00
|
|
|
void *release_data;
|
2016-11-25 17:57:09 +07:00
|
|
|
struct msi_controller *msi;
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int ignore_reset_delay:1; /* For entire hierarchy */
|
|
|
|
unsigned int no_ext_tags:1; /* No Extended Tags */
|
2018-03-10 00:21:25 +07:00
|
|
|
unsigned int native_aer:1; /* OS may use PCIe AER */
|
2018-05-24 05:22:19 +07:00
|
|
|
unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
|
2018-05-24 05:40:23 +07:00
|
|
|
unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
|
2018-03-10 00:21:25 +07:00
|
|
|
unsigned int native_pme:1; /* OS may use PCIe PME */
|
2018-04-17 22:58:09 +07:00
|
|
|
unsigned int native_ltr:1; /* OS may use PCIe LTR */
|
2019-06-15 07:23:57 +07:00
|
|
|
unsigned int preserve_config:1; /* Preserve FW resource setup */
|
|
|
|
|
2015-11-11 08:12:25 +07:00
|
|
|
/* Resource alignment requirements */
|
|
|
|
resource_size_t (*align_resource)(struct pci_dev *dev,
|
|
|
|
const struct resource *res,
|
|
|
|
resource_size_t start,
|
|
|
|
resource_size_t size,
|
|
|
|
resource_size_t align);
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned long private[0] ____cacheline_aligned;
|
2012-02-24 10:18:59 +07:00
|
|
|
};
|
2006-02-08 16:11:38 +07:00
|
|
|
|
2012-04-03 08:31:53 +07:00
|
|
|
#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
|
2015-11-11 08:12:25 +07:00
|
|
|
|
2016-11-25 17:57:10 +07:00
|
|
|
static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
|
|
|
|
{
|
|
|
|
return (void *)bridge->private;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
|
|
|
|
{
|
|
|
|
return container_of(priv, struct pci_host_bridge, private);
|
|
|
|
}
|
|
|
|
|
2016-11-25 17:57:11 +07:00
|
|
|
struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
|
2017-06-29 03:13:53 +07:00
|
|
|
struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
|
|
|
|
size_t priv);
|
2017-06-29 03:13:52 +07:00
|
|
|
void pci_free_host_bridge(struct pci_host_bridge *bridge);
|
2015-11-11 08:12:25 +07:00
|
|
|
struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
|
|
|
|
|
2012-04-03 08:31:53 +07:00
|
|
|
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
|
2017-12-03 02:21:37 +07:00
|
|
|
void (*release_fn)(struct pci_host_bridge *),
|
|
|
|
void *release_data);
|
2012-04-03 08:31:53 +07:00
|
|
|
|
ACPI / PCI: Set root bridge ACPI handle in advance
The ACPI handles of PCI root bridges need to be known to
acpi_bind_one(), so that it can create the appropriate
"firmware_node" and "physical_node" files for them, but currently
the way it gets to know those handles is not exactly straightforward
(to put it lightly).
This is how it works, roughly:
1. acpi_bus_scan() finds the handle of a PCI root bridge,
creates a struct acpi_device object for it and passes that
object to acpi_pci_root_add().
2. acpi_pci_root_add() creates a struct acpi_pci_root object,
populates its "device" field with its argument's address
(device->handle is the ACPI handle found in step 1).
3. The struct acpi_pci_root object created in step 2 is passed
to pci_acpi_scan_root() and used to get resources that are
passed to pci_create_root_bus().
4. pci_create_root_bus() creates a struct pci_host_bridge object
and passes its "dev" member to device_register().
5. platform_notify(), which for systems with ACPI is set to
acpi_platform_notify(), is called.
So far, so good. Now it starts to be "interesting".
6. acpi_find_bridge_device() is used to find the ACPI handle of
the given device (which is the PCI root bridge) and executes
acpi_pci_find_root_bridge(), among other things, for the
given device object.
7. acpi_pci_find_root_bridge() uses the name (sic!) of the given
device object to extract the segment and bus numbers of the PCI
root bridge and passes them to acpi_get_pci_rootbridge_handle().
8. acpi_get_pci_rootbridge_handle() browses the list of ACPI PCI
root bridges and finds the one that matches the given segment
and bus numbers. Its handle is then used to initialize the
ACPI handle of the PCI root bridge's device object by
acpi_bind_one(). However, this is *exactly* the ACPI handle we
started with in step 1.
Needless to say, this is quite embarassing, but it may be avoided
thanks to commit f3fd0c8 (ACPI: Allow ACPI handles of devices to be
initialized in advance), which makes it possible to initialize the
ACPI handle of a device before passing it to device_register().
Accordingly, add a new __weak routine, pcibios_root_bridge_prepare(),
defaulting to an empty implementation that can be replaced by the
interested architecutres (x86 and ia64 at the moment) with functions
that will set the root bridge's ACPI handle before its dev member is
passed to device_register(). Make both x86 and ia64 provide such
implementations of pcibios_root_bridge_prepare() and remove
acpi_pci_find_root_bridge() and acpi_get_pci_rootbridge_handle() that
aren't necessary any more.
Included is a fix for breakage on systems with non-ACPI PCI host
bridges from Bjorn Helgaas.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-01-10 04:33:37 +07:00
|
|
|
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
|
|
|
|
|
2010-02-24 00:24:36 +07:00
|
|
|
/*
|
|
|
|
* The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
|
|
|
|
* to P2P or CardBus bridge windows) go in a table. Additional ones (for
|
|
|
|
* buses below host bridges or subtractive decode bridges) go in the list.
|
|
|
|
* Use pci_bus_for_each_resource() to iterate through all the resources.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
|
|
|
|
* and there's no way to program the bridge with the details of the window.
|
|
|
|
* This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
|
|
|
|
* decode bit set, because they are explicit and can be programmed with _SRS.
|
|
|
|
*/
|
|
|
|
#define PCI_SUBTRACTIVE_DECODE 0x1
|
|
|
|
|
|
|
|
struct pci_bus_resource {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct list_head list;
|
|
|
|
struct resource *res;
|
|
|
|
unsigned int flags;
|
2010-02-24 00:24:36 +07:00
|
|
|
};
|
2005-07-29 01:37:33 +07:00
|
|
|
|
|
|
|
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
struct pci_bus {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct list_head node; /* Node in list of buses */
|
|
|
|
struct pci_bus *parent; /* Parent bus this bridge is on */
|
|
|
|
struct list_head children; /* List of child buses */
|
|
|
|
struct list_head devices; /* List of devices on this bus */
|
|
|
|
struct pci_dev *self; /* Bridge device as seen by parent */
|
|
|
|
struct list_head slots; /* List of slots on this bus;
|
2015-07-17 16:16:31 +07:00
|
|
|
protected by pci_slot_mutex */
|
2010-02-24 00:24:36 +07:00
|
|
|
struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
|
2017-12-03 02:21:37 +07:00
|
|
|
struct list_head resources; /* Address space routed to this bus */
|
|
|
|
struct resource busn_res; /* Bus numbers routed to this bus */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
struct pci_ops *ops; /* Configuration access functions */
|
2014-11-12 07:45:45 +07:00
|
|
|
struct msi_controller *msi; /* MSI controller */
|
2017-12-03 02:21:37 +07:00
|
|
|
void *sysdata; /* Hook for sys-specific extension */
|
|
|
|
struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned char number; /* Bus number */
|
|
|
|
unsigned char primary; /* Number of primary bridge */
|
2009-12-13 20:11:32 +07:00
|
|
|
unsigned char max_bus_speed; /* enum pci_bus_speed */
|
|
|
|
unsigned char cur_bus_speed; /* enum pci_bus_speed */
|
2014-09-29 21:29:26 +07:00
|
|
|
#ifdef CONFIG_PCI_DOMAINS_GENERIC
|
|
|
|
int domain_nr;
|
|
|
|
#endif
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
char name[48];
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
|
|
|
|
pci_bus_flags_t bus_flags; /* Inherited by child buses */
|
2005-04-17 05:20:36 +07:00
|
|
|
struct device *bridge;
|
2007-05-23 09:47:54 +07:00
|
|
|
struct device dev;
|
2017-12-03 02:21:37 +07:00
|
|
|
struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
|
|
|
|
struct bin_attribute *legacy_mem; /* Legacy mem */
|
2008-03-13 11:48:03 +07:00
|
|
|
unsigned int is_added:1;
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2007-05-23 09:47:54 +07:00
|
|
|
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2019-04-25 02:11:58 +07:00
|
|
|
static inline u16 pci_dev_id(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return PCI_DEVID(dev->bus->number, dev->devfn);
|
|
|
|
}
|
|
|
|
|
2009-03-21 03:55:55 +07:00
|
|
|
/*
|
2013-11-15 01:28:18 +07:00
|
|
|
* Returns true if the PCI bus is root (behind host-PCI bridge),
|
2009-03-21 03:55:55 +07:00
|
|
|
* false otherwise
|
2013-09-25 04:14:57 +07:00
|
|
|
*
|
|
|
|
* Some code assumes that "bus->self == NULL" means that bus is a root bus.
|
|
|
|
* This is incorrect because "virtual" buses added for SR-IOV (via
|
|
|
|
* virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
|
2009-03-21 03:55:55 +07:00
|
|
|
*/
|
|
|
|
static inline bool pci_is_root_bus(struct pci_bus *pbus)
|
|
|
|
{
|
|
|
|
return !(pbus->parent);
|
|
|
|
}
|
|
|
|
|
2014-05-04 11:23:37 +07:00
|
|
|
/**
|
|
|
|
* pci_is_bridge - check if the PCI device is a bridge
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* Return true if the PCI device is bridge whether it has subordinate
|
|
|
|
* or not.
|
|
|
|
*/
|
|
|
|
static inline bool pci_is_bridge(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
|
|
|
|
dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
|
|
|
|
}
|
|
|
|
|
2017-10-21 03:38:54 +07:00
|
|
|
#define for_each_pci_bridge(dev, bus) \
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) \
|
|
|
|
if (!pci_is_bridge(dev)) {} else
|
|
|
|
|
2013-11-07 00:11:48 +07:00
|
|
|
static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
dev = pci_physfn(dev);
|
|
|
|
if (pci_is_root_bus(dev->bus))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return dev->bus->self;
|
|
|
|
}
|
|
|
|
|
2015-03-04 00:52:11 +07:00
|
|
|
struct device *pci_get_host_bridge_device(struct pci_dev *dev);
|
|
|
|
void pci_put_host_bridge_device(struct device *dev);
|
|
|
|
|
2009-01-05 20:50:27 +07:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
|
|
|
|
{
|
|
|
|
return pci_dev->msi_enabled || pci_dev->msix_enabled;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
|
|
|
|
#endif
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Error values that may be returned by PCI functions */
|
2005-04-17 05:20:36 +07:00
|
|
|
#define PCIBIOS_SUCCESSFUL 0x00
|
|
|
|
#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
|
|
|
|
#define PCIBIOS_BAD_VENDOR_ID 0x83
|
|
|
|
#define PCIBIOS_DEVICE_NOT_FOUND 0x86
|
|
|
|
#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
|
|
|
|
#define PCIBIOS_SET_FAILED 0x88
|
|
|
|
#define PCIBIOS_BUFFER_TOO_SMALL 0x89
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Translate above to generic errno for passing back through non-PCI code */
|
2012-06-11 12:27:33 +07:00
|
|
|
static inline int pcibios_err_to_errno(int err)
|
|
|
|
{
|
|
|
|
if (err <= PCIBIOS_SUCCESSFUL)
|
|
|
|
return err; /* Assume already errno */
|
|
|
|
|
|
|
|
switch (err) {
|
|
|
|
case PCIBIOS_FUNC_NOT_SUPPORTED:
|
|
|
|
return -ENOENT;
|
|
|
|
case PCIBIOS_BAD_VENDOR_ID:
|
2014-05-21 12:23:30 +07:00
|
|
|
return -ENOTTY;
|
2012-06-11 12:27:33 +07:00
|
|
|
case PCIBIOS_DEVICE_NOT_FOUND:
|
|
|
|
return -ENODEV;
|
|
|
|
case PCIBIOS_BAD_REGISTER_NUMBER:
|
|
|
|
return -EFAULT;
|
|
|
|
case PCIBIOS_SET_FAILED:
|
|
|
|
return -EIO;
|
|
|
|
case PCIBIOS_BUFFER_TOO_SMALL:
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
2014-05-21 12:23:30 +07:00
|
|
|
return -ERANGE;
|
2012-06-11 12:27:33 +07:00
|
|
|
}
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Low-level architecture-dependent routines */
|
|
|
|
|
|
|
|
struct pci_ops {
|
2016-02-09 21:30:47 +07:00
|
|
|
int (*add_bus)(struct pci_bus *bus);
|
|
|
|
void (*remove_bus)(struct pci_bus *bus);
|
2015-01-10 09:34:39 +07:00
|
|
|
void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
|
2005-04-17 05:20:36 +07:00
|
|
|
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
|
|
|
|
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
|
|
|
|
};
|
|
|
|
|
2008-02-10 21:45:28 +07:00
|
|
|
/*
|
|
|
|
* ACPI needs to be able to access PCI config space before we've done a
|
|
|
|
* PCI bus scan and created pci_bus structures.
|
|
|
|
*/
|
2013-04-13 01:02:59 +07:00
|
|
|
int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
|
|
|
|
int reg, int len, u32 *val);
|
|
|
|
int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
|
|
|
|
int reg, int len, u32 val);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2018-04-03 21:40:54 +07:00
|
|
|
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-28 07:23:51 +07:00
|
|
|
typedef u64 pci_bus_addr_t;
|
|
|
|
#else
|
|
|
|
typedef u32 pci_bus_addr_t;
|
|
|
|
#endif
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
struct pci_bus_region {
|
2017-12-03 02:21:37 +07:00
|
|
|
pci_bus_addr_t start;
|
|
|
|
pci_bus_addr_t end;
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct pci_dynids {
|
2017-12-03 02:21:37 +07:00
|
|
|
spinlock_t lock; /* Protects list, index */
|
|
|
|
struct list_head list; /* For IDs added at runtime */
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2013-11-15 01:28:18 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
|
|
|
|
* a set of callbacks in struct pci_error_handlers, that device driver
|
|
|
|
* will be notified of PCI bus errors, and will be driven to recovery
|
|
|
|
* when an error occurs.
|
2005-11-17 06:10:41 +07:00
|
|
|
*/
|
|
|
|
|
|
|
|
typedef unsigned int __bitwise pci_ers_result_t;
|
|
|
|
|
|
|
|
enum pci_ers_result {
|
2017-12-03 02:21:37 +07:00
|
|
|
/* No result/none/not supported in device driver */
|
2005-11-17 06:10:41 +07:00
|
|
|
PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
|
|
|
|
|
|
|
|
/* Device driver can recover without slot reset */
|
|
|
|
PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Device driver wants slot to be reset */
|
2005-11-17 06:10:41 +07:00
|
|
|
PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
|
|
|
|
|
|
|
|
/* Device has completely failed, is unrecoverable */
|
|
|
|
PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
|
|
|
|
|
|
|
|
/* Device driver is fully recovered and operational */
|
|
|
|
PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
|
2012-11-17 18:47:18 +07:00
|
|
|
|
|
|
|
/* No AER capabilities registered for the driver */
|
|
|
|
PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
|
2005-11-17 06:10:41 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/* PCI bus error event callbacks */
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_error_handlers {
|
2005-11-17 06:10:41 +07:00
|
|
|
/* PCI bus error detected on this device */
|
|
|
|
pci_ers_result_t (*error_detected)(struct pci_dev *dev,
|
2008-01-31 06:21:33 +07:00
|
|
|
enum pci_channel_state error);
|
2005-11-17 06:10:41 +07:00
|
|
|
|
|
|
|
/* MMIO has been re-enabled, but not DMA */
|
|
|
|
pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
|
|
|
|
|
|
|
|
/* PCI slot has been reset */
|
|
|
|
pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
|
|
|
|
|
2014-05-02 23:40:42 +07:00
|
|
|
/* PCI function reset prepare or completed */
|
2017-06-01 18:10:38 +07:00
|
|
|
void (*reset_prepare)(struct pci_dev *dev);
|
|
|
|
void (*reset_done)(struct pci_dev *dev);
|
2014-05-02 23:40:42 +07:00
|
|
|
|
2005-11-17 06:10:41 +07:00
|
|
|
/* Device driver may resume normal operations */
|
|
|
|
void (*resume)(struct pci_dev *dev);
|
|
|
|
};
|
|
|
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
struct module;
|
2019-05-14 21:47:24 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct pci_driver - PCI driver structure
|
|
|
|
* @node: List of driver structures.
|
|
|
|
* @name: Driver name.
|
|
|
|
* @id_table: Pointer to table of device IDs the driver is
|
|
|
|
* interested in. Most drivers should export this
|
|
|
|
* table using MODULE_DEVICE_TABLE(pci,...).
|
|
|
|
* @probe: This probing function gets called (during execution
|
|
|
|
* of pci_register_driver() for already existing
|
|
|
|
* devices or later if a new device gets inserted) for
|
|
|
|
* all PCI devices which match the ID table and are not
|
|
|
|
* "owned" by the other drivers yet. This function gets
|
|
|
|
* passed a "struct pci_dev \*" for each device whose
|
|
|
|
* entry in the ID table matches the device. The probe
|
|
|
|
* function returns zero when the driver chooses to
|
|
|
|
* take "ownership" of the device or an error code
|
|
|
|
* (negative number) otherwise.
|
|
|
|
* The probe function always gets called from process
|
|
|
|
* context, so it can sleep.
|
|
|
|
* @remove: The remove() function gets called whenever a device
|
|
|
|
* being handled by this driver is removed (either during
|
|
|
|
* deregistration of the driver or when it's manually
|
|
|
|
* pulled out of a hot-pluggable slot).
|
|
|
|
* The remove function always gets called from process
|
|
|
|
* context, so it can sleep.
|
|
|
|
* @suspend: Put device into low power state.
|
|
|
|
* @suspend_late: Put device into low power state.
|
|
|
|
* @resume_early: Wake device from low power state.
|
|
|
|
* @resume: Wake device from low power state.
|
2019-06-13 17:10:36 +07:00
|
|
|
* (Please see Documentation/power/pci.rst for descriptions
|
2019-05-14 21:47:24 +07:00
|
|
|
* of PCI Power Management and the related functions.)
|
|
|
|
* @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
|
|
|
|
* Intended to stop any idling DMA operations.
|
|
|
|
* Useful for enabling wake-on-lan (NIC) or changing
|
|
|
|
* the power state of a device before reboot.
|
|
|
|
* e.g. drivers/net/e100.c.
|
|
|
|
* @sriov_configure: Optional driver callback to allow configuration of
|
|
|
|
* number of VFs to enable via sysfs "sriov_numvfs" file.
|
|
|
|
* @err_handler: See Documentation/PCI/pci-error-recovery.rst
|
|
|
|
* @groups: Sysfs attribute groups.
|
|
|
|
* @driver: Driver model structure.
|
|
|
|
* @dynids: List of dynamically added device IDs.
|
|
|
|
*/
|
2005-04-17 05:20:36 +07:00
|
|
|
struct pci_driver {
|
2017-12-03 02:21:37 +07:00
|
|
|
struct list_head node;
|
|
|
|
const char *name;
|
|
|
|
const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
|
|
|
|
int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
|
|
|
|
void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
|
|
|
|
int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
|
|
|
|
int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
|
|
|
|
int (*resume_early)(struct pci_dev *dev);
|
2018-12-01 23:07:11 +07:00
|
|
|
int (*resume)(struct pci_dev *dev); /* Device woken up */
|
|
|
|
void (*shutdown)(struct pci_dev *dev);
|
|
|
|
int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
|
2012-09-07 23:33:14 +07:00
|
|
|
const struct pci_error_handlers *err_handler;
|
2017-07-19 20:01:06 +07:00
|
|
|
const struct attribute_group **groups;
|
2005-04-17 05:20:36 +07:00
|
|
|
struct device_driver driver;
|
2017-12-03 02:21:37 +07:00
|
|
|
struct pci_dynids dynids;
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/**
|
2017-12-03 02:21:37 +07:00
|
|
|
* PCI_DEVICE - macro used to describe a specific PCI device
|
2005-04-17 05:20:36 +07:00
|
|
|
* @vend: the 16 bit PCI Vendor ID
|
|
|
|
* @dev: the 16 bit PCI Device ID
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
|
|
|
* specific device. The subvendor and subdevice fields will be set to
|
|
|
|
* PCI_ANY_ID.
|
|
|
|
*/
|
|
|
|
#define PCI_DEVICE(vend,dev) \
|
|
|
|
.vendor = (vend), .device = (dev), \
|
|
|
|
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
|
|
|
|
|
2012-11-14 21:44:26 +07:00
|
|
|
/**
|
2017-12-03 02:21:37 +07:00
|
|
|
* PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
|
2012-11-14 21:44:26 +07:00
|
|
|
* @vend: the 16 bit PCI Vendor ID
|
|
|
|
* @dev: the 16 bit PCI Device ID
|
|
|
|
* @subvend: the 16 bit PCI Subvendor ID
|
|
|
|
* @subdev: the 16 bit PCI Subdevice ID
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
|
|
|
* specific device with subsystem information.
|
|
|
|
*/
|
|
|
|
#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
|
|
|
|
.vendor = (vend), .device = (dev), \
|
|
|
|
.subvendor = (subvend), .subdevice = (subdev)
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/**
|
2017-12-03 02:21:37 +07:00
|
|
|
* PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
|
2005-04-17 05:20:36 +07:00
|
|
|
* @dev_class: the class, subclass, prog-if triple for this device
|
|
|
|
* @dev_class_mask: the class mask for this device
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
2005-07-29 01:37:33 +07:00
|
|
|
* specific PCI class. The vendor, device, subvendor, and subdevice
|
2005-04-17 05:20:36 +07:00
|
|
|
* fields will be set to PCI_ANY_ID.
|
|
|
|
*/
|
|
|
|
#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
|
|
|
|
.class = (dev_class), .class_mask = (dev_class_mask), \
|
|
|
|
.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
|
|
|
|
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
|
|
|
|
|
2006-12-05 06:14:45 +07:00
|
|
|
/**
|
2017-12-03 02:21:37 +07:00
|
|
|
* PCI_VDEVICE - macro used to describe a specific PCI device in short form
|
2014-04-01 04:58:39 +07:00
|
|
|
* @vend: the vendor name
|
|
|
|
* @dev: the 16 bit PCI Device ID
|
2006-12-05 06:14:45 +07:00
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
|
|
|
* specific PCI device. The subvendor, and subdevice fields will be set
|
|
|
|
* to PCI_ANY_ID. The macro allows the next field to follow as the device
|
|
|
|
* private data.
|
|
|
|
*/
|
2014-04-01 04:58:39 +07:00
|
|
|
#define PCI_VDEVICE(vend, dev) \
|
|
|
|
.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
|
|
|
|
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
|
2006-12-05 06:14:45 +07:00
|
|
|
|
2018-07-29 20:16:56 +07:00
|
|
|
/**
|
|
|
|
* PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
|
|
|
|
* @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
|
|
|
|
* @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
|
|
|
|
* @data: the driver data to be filled
|
|
|
|
*
|
|
|
|
* This macro is used to create a struct pci_device_id that matches a
|
|
|
|
* specific PCI device. The subvendor, and subdevice fields will be set
|
|
|
|
* to PCI_ANY_ID.
|
|
|
|
*/
|
|
|
|
#define PCI_DEVICE_DATA(vend, dev, data) \
|
|
|
|
.vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
|
|
|
|
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
|
|
|
|
.driver_data = (kernel_ulong_t)(data)
|
|
|
|
|
2016-02-06 03:57:47 +07:00
|
|
|
enum {
|
2017-12-03 02:21:37 +07:00
|
|
|
PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
|
|
|
|
PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
|
|
|
|
PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
|
|
|
|
PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
|
|
|
|
PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
|
2016-02-06 03:57:47 +07:00
|
|
|
PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
|
2017-12-03 02:21:37 +07:00
|
|
|
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
|
2016-02-06 03:57:47 +07:00
|
|
|
};
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* These external functions are only available when PCI support is enabled */
|
2005-04-17 05:20:36 +07:00
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
2016-02-06 03:57:47 +07:00
|
|
|
extern unsigned int pci_flags;
|
|
|
|
|
|
|
|
static inline void pci_set_flags(int flags) { pci_flags = flags; }
|
|
|
|
static inline void pci_add_flags(int flags) { pci_flags |= flags; }
|
|
|
|
static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
|
|
|
|
static inline int pci_has_flag(int flag) { return pci_flags & flag; }
|
|
|
|
|
2013-08-22 10:24:44 +07:00
|
|
|
void pcie_bus_configure_settings(struct pci_bus *bus);
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-21 03:20:54 +07:00
|
|
|
|
|
|
|
enum pcie_bus_config_types {
|
2017-12-03 02:21:37 +07:00
|
|
|
PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
|
|
|
|
PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
|
|
|
|
PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
|
|
|
|
PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
|
|
|
|
PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-21 03:20:54 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
extern enum pcie_bus_config_types pcie_bus_config;
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
extern struct bus_type pci_bus_type;
|
|
|
|
|
2013-11-15 01:28:18 +07:00
|
|
|
/* Do NOT directly access these two variables, unless you are arch-specific PCI
|
|
|
|
* code, or PCI core code. */
|
2017-12-03 02:21:37 +07:00
|
|
|
extern struct list_head pci_root_buses; /* List of all known PCI buses */
|
2013-11-15 01:28:18 +07:00
|
|
|
/* Some device drivers need know if PCI is initiated */
|
2013-04-13 01:02:59 +07:00
|
|
|
int no_pci_devices(void);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-11-04 11:39:31 +07:00
|
|
|
void pcibios_resource_survey_bus(struct pci_bus *bus);
|
2016-03-04 06:53:04 +07:00
|
|
|
void pcibios_bus_add_device(struct pci_dev *pdev);
|
2013-04-12 12:44:20 +07:00
|
|
|
void pcibios_add_bus(struct pci_bus *bus);
|
|
|
|
void pcibios_remove_bus(struct pci_bus *bus);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pcibios_fixup_bus(struct pci_bus *);
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pcibios_enable_device(struct pci_dev *, int mask);
|
2013-11-15 01:28:18 +07:00
|
|
|
/* Architecture-specific versions may override this (weak) */
|
2008-01-31 06:21:33 +07:00
|
|
|
char *pcibios_setup(char *str);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/* Used only when drivers/pci/setup.c is used */
|
2010-01-01 23:40:50 +07:00
|
|
|
resource_size_t pcibios_align_resource(void *, const struct resource *,
|
2010-01-01 23:40:49 +07:00
|
|
|
resource_size_t,
|
2006-06-13 07:06:02 +07:00
|
|
|
resource_size_t);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2009-12-09 13:52:13 +07:00
|
|
|
/* Weak but can be overriden by arch */
|
|
|
|
void pci_fixup_cardbus(struct pci_bus *);
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Generic PCI functions used internally */
|
|
|
|
|
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
These interfaces:
pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)
took a pci_dev, but they really depend only on the pci_bus. And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:
pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)
In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.
[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-10 13:54:40 +07:00
|
|
|
void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
|
2012-02-24 10:19:00 +07:00
|
|
|
struct resource *res);
|
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
These interfaces:
pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)
took a pci_dev, but they really depend only on the pci_bus. And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:
pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)
In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.
[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-10 13:54:40 +07:00
|
|
|
void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
|
2012-02-24 10:19:00 +07:00
|
|
|
struct pci_bus_region *region);
|
2009-07-11 04:39:53 +07:00
|
|
|
void pcibios_scan_specific_bus(int busn);
|
2013-04-13 01:02:59 +07:00
|
|
|
struct pci_bus *pci_find_bus(int domain, int busnr);
|
2009-02-04 06:45:26 +07:00
|
|
|
void pci_bus_add_devices(const struct pci_bus *bus);
|
2011-10-29 05:25:55 +07:00
|
|
|
struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
|
2011-10-29 05:25:45 +07:00
|
|
|
struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
|
|
|
|
struct pci_ops *ops, void *sysdata,
|
|
|
|
struct list_head *resources);
|
2018-01-31 03:56:52 +07:00
|
|
|
int pci_host_probe(struct pci_host_bridge *bridge);
|
2012-05-19 00:35:50 +07:00
|
|
|
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
|
|
|
|
int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
|
|
|
|
void pci_bus_release_busn_res(struct pci_bus *b);
|
2012-11-22 03:35:00 +07:00
|
|
|
struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
|
2017-12-03 02:21:37 +07:00
|
|
|
struct pci_ops *ops, void *sysdata,
|
|
|
|
struct list_head *resources);
|
2017-06-29 03:13:55 +07:00
|
|
|
int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
|
|
|
|
int busnr);
|
2009-12-13 20:11:32 +07:00
|
|
|
void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
|
2008-06-11 04:28:50 +07:00
|
|
|
struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
|
2008-10-21 06:40:52 +07:00
|
|
|
const char *name,
|
|
|
|
struct hotplug_slot *hotplug);
|
2008-06-11 04:28:50 +07:00
|
|
|
void pci_destroy_slot(struct pci_slot *slot);
|
2015-07-17 16:16:32 +07:00
|
|
|
#ifdef CONFIG_SYSFS
|
|
|
|
void pci_dev_assign_slot(struct pci_dev *dev);
|
|
|
|
#else
|
|
|
|
static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
|
|
|
|
#endif
|
2005-04-17 05:20:36 +07:00
|
|
|
int pci_scan_slot(struct pci_bus *bus, int devfn);
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
|
2005-09-06 06:31:03 +07:00
|
|
|
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
|
2005-04-17 05:20:36 +07:00
|
|
|
unsigned int pci_scan_child_bus(struct pci_bus *bus);
|
2014-05-30 10:01:03 +07:00
|
|
|
void pci_bus_add_device(struct pci_dev *dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_read_bridge_bases(struct pci_bus *child);
|
2008-01-31 06:21:33 +07:00
|
|
|
struct resource *pci_find_parent_resource(const struct pci_dev *dev,
|
|
|
|
struct resource *res);
|
PCI: Turn off Request Attributes to avoid Chelsio T5 Completion erratum
The Chelsio T5 has a PCIe compliance erratum that causes Malformed TLP or
Unexpected Completion errors in some systems, which may cause device access
timeouts.
Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same values
for the Attribute as were supplied in the header of the corresponding
Request, except as explicitly allowed when IDO is used."
Instead of copying the Attributes from the Request to the Completion, the
T5 always generates Completions with zero Attributes. The receiver of a
Completion whose Attributes don't match the Request may accept it (which
itself seems non-compliant based on sec 2.3.2), or it may handle it as a
Malformed TLP or an Unexpected Completion, which will probably lead to a
device access timeout.
Work around this by disabling "Relaxed Ordering" and "No Snoop" in the Root
Port so it always generate Requests with zero Attributes.
This does affect all other devices which are downstream of that Root Port,
but these are performance optimizations that should not make a functional
difference.
Note that Configuration Space accesses are never supposed to have TLP
Attributes, so we're safe waiting till after any Configuration Space
accesses to do the Root Port "fixup".
Based on original work by Casey Leedom <leedom@chelsio.com>
[bhelgaas: changelog, comments, rename to pci_find_pcie_root_port(), rework
to use pci_upstream_bridge() and check for Root Port device type, edit
diagnostics to clarify intent and devices affected]
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-10-18 21:25:04 +07:00
|
|
|
struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
|
2012-04-12 22:33:07 +07:00
|
|
|
u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
|
2005-04-17 05:20:36 +07:00
|
|
|
int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
|
2008-12-17 11:36:55 +07:00
|
|
|
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
|
2013-04-13 01:02:59 +07:00
|
|
|
struct pci_dev *pci_dev_get(struct pci_dev *dev);
|
|
|
|
void pci_dev_put(struct pci_dev *dev);
|
|
|
|
void pci_remove_bus(struct pci_bus *b);
|
|
|
|
void pci_stop_and_remove_bus_device(struct pci_dev *dev);
|
2014-01-10 21:22:18 +07:00
|
|
|
void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
|
2012-10-31 03:31:38 +07:00
|
|
|
void pci_stop_root_bus(struct pci_bus *bus);
|
|
|
|
void pci_remove_root_bus(struct pci_bus *bus);
|
2005-09-10 03:03:23 +07:00
|
|
|
void pci_setup_cardbus(struct pci_bus *bus);
|
2016-05-20 13:41:25 +07:00
|
|
|
void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_sort_breadthfirst(void);
|
2010-02-10 08:43:04 +07:00
|
|
|
#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
|
|
|
|
#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/* Generic PCI functions exported to card drivers */
|
|
|
|
|
2008-08-04 01:02:12 +07:00
|
|
|
enum pci_lost_interrupt_reason {
|
|
|
|
PCI_LOST_IRQ_NO_INFORMATION = 0,
|
|
|
|
PCI_LOST_IRQ_DISABLE_MSI,
|
|
|
|
PCI_LOST_IRQ_DISABLE_MSIX,
|
|
|
|
PCI_LOST_IRQ_DISABLE_ACPI,
|
|
|
|
};
|
|
|
|
enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
|
2008-01-31 06:21:33 +07:00
|
|
|
int pci_find_capability(struct pci_dev *dev, int cap);
|
|
|
|
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
|
|
|
|
int pci_find_ext_capability(struct pci_dev *dev, int cap);
|
2012-07-14 03:24:59 +07:00
|
|
|
int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
|
2008-01-31 06:21:33 +07:00
|
|
|
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
|
|
|
|
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
|
2006-10-17 06:20:21 +07:00
|
|
|
struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2006-10-22 00:24:12 +07:00
|
|
|
struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
|
2017-12-03 02:21:37 +07:00
|
|
|
struct pci_dev *from);
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int ss_vendor, unsigned int ss_device,
|
|
|
|
struct pci_dev *from);
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
|
2009-10-13 02:14:00 +07:00
|
|
|
struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
|
|
|
|
unsigned int devfn);
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
|
2005-04-17 05:20:36 +07:00
|
|
|
int pci_dev_present(const struct pci_device_id *ids);
|
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u8 *val);
|
|
|
|
int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u16 *val);
|
|
|
|
int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u32 *val);
|
|
|
|
int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u8 val);
|
|
|
|
int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u16 val);
|
|
|
|
int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, u32 val);
|
2015-01-10 09:34:39 +07:00
|
|
|
|
|
|
|
int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, int size, u32 *val);
|
|
|
|
int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, int size, u32 val);
|
|
|
|
int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, int size, u32 *val);
|
|
|
|
int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
|
|
|
|
int where, int size, u32 val);
|
|
|
|
|
2009-04-24 09:45:17 +07:00
|
|
|
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-02-08 02:32:33 +07:00
|
|
|
int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
|
|
|
|
int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
|
|
|
|
int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
|
|
|
|
int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
|
|
|
|
int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
|
|
|
|
int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
PCI: Add accessors for PCI Express Capability
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two
versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and
r1.1), some fields are optional, so the structure size depends on the
device type.
This patch adds functions to access this capability so drivers don't
have to be aware of the differences between v1 and v2. Note that these
new functions apply only to the "PCI Express Capability," not to any of
the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
Function pcie_capability_read_word/dword() reads the PCIe Capabilities
register and returns the value in the reference parameter "val". If
the PCIe Capabilities register is not implemented on the PCIe device,
"val" is set to 0.
Function pcie_capability_write_word/dword() writes the value to the
specified PCIe Capability register.
Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits
of a PCIe Capability register.
[bhelgaas: changelog, drop "pci_" prefixes, don't export
pcie_capability_reg_implemented()]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-24 16:20:05 +07:00
|
|
|
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
|
|
|
|
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
|
|
|
|
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
|
|
|
|
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
|
|
|
|
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
|
|
|
u16 clear, u16 set);
|
|
|
|
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
|
|
|
|
u32 clear, u32 set);
|
|
|
|
|
|
|
|
static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
|
|
|
|
u16 set)
|
|
|
|
{
|
|
|
|
return pcie_capability_clear_and_set_word(dev, pos, 0, set);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
|
|
|
|
u32 set)
|
|
|
|
{
|
|
|
|
return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
|
|
|
|
u16 clear)
|
|
|
|
{
|
|
|
|
return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
|
|
|
|
u32 clear)
|
|
|
|
{
|
|
|
|
return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
|
|
|
|
}
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* User-space driven config access */
|
2012-06-11 12:27:19 +07:00
|
|
|
int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
|
|
|
|
int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
|
|
|
|
int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
|
|
|
|
int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
|
|
|
|
int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
|
|
|
|
int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
|
|
|
|
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pci_enable_device(struct pci_dev *dev);
|
2007-12-20 11:28:08 +07:00
|
|
|
int __must_check pci_enable_device_io(struct pci_dev *dev);
|
|
|
|
int __must_check pci_enable_device_mem(struct pci_dev *dev);
|
2007-07-27 12:43:35 +07:00
|
|
|
int __must_check pci_reenable_device(struct pci_dev *);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 14:00:26 +07:00
|
|
|
int __must_check pcim_enable_device(struct pci_dev *pdev);
|
|
|
|
void pcim_pin_device(struct pci_dev *pdev);
|
|
|
|
|
2017-05-27 04:02:25 +07:00
|
|
|
static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
|
|
|
|
* writable and no quirk has marked the feature broken.
|
|
|
|
*/
|
|
|
|
return !pdev->broken_intx_masking;
|
|
|
|
}
|
|
|
|
|
2009-04-03 14:41:46 +07:00
|
|
|
static inline int pci_is_enabled(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return (atomic_read(&pdev->enable_cnt) > 0);
|
|
|
|
}
|
|
|
|
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 14:00:26 +07:00
|
|
|
static inline int pci_is_managed(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pdev->is_managed;
|
|
|
|
}
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_disable_device(struct pci_dev *dev);
|
2011-10-29 04:48:38 +07:00
|
|
|
|
|
|
|
extern unsigned int pcibios_max_latency;
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_set_master(struct pci_dev *dev);
|
2008-12-23 10:08:29 +07:00
|
|
|
void pci_clear_master(struct pci_dev *dev);
|
2011-10-29 04:48:38 +07:00
|
|
|
|
2007-04-07 04:39:36 +07:00
|
|
|
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
|
2009-09-22 15:34:48 +07:00
|
|
|
int pci_set_cacheline_size(struct pci_dev *dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
#define HAVE_PCI_SET_MWI
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pci_set_mwi(struct pci_dev *dev);
|
2017-12-12 13:40:56 +07:00
|
|
|
int __must_check pcim_set_mwi(struct pci_dev *dev);
|
2007-07-10 01:55:54 +07:00
|
|
|
int pci_try_set_mwi(struct pci_dev *dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_clear_mwi(struct pci_dev *dev);
|
2005-08-16 02:23:41 +07:00
|
|
|
void pci_intx(struct pci_dev *dev, int enable);
|
2011-11-04 15:46:00 +07:00
|
|
|
bool pci_check_and_mask_intx(struct pci_dev *dev);
|
|
|
|
bool pci_check_and_unmask_intx(struct pci_dev *dev);
|
2013-12-18 06:43:39 +07:00
|
|
|
int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
|
2013-08-06 17:18:36 +07:00
|
|
|
int pci_wait_for_pending_transaction(struct pci_dev *dev);
|
2007-05-15 18:59:13 +07:00
|
|
|
int pcix_get_max_mmrbc(struct pci_dev *dev);
|
|
|
|
int pcix_get_mmrbc(struct pci_dev *dev);
|
|
|
|
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
|
2007-08-14 17:43:48 +07:00
|
|
|
int pcie_get_readrq(struct pci_dev *dev);
|
2007-05-15 18:59:13 +07:00
|
|
|
int pcie_set_readrq(struct pci_dev *dev, int rq);
|
PCI: Set PCI-E Max Payload Size on fabric
On a given PCI-E fabric, each device, bridge, and root port can have a
different PCI-E maximum payload size. There is a sizable performance
boost for having the largest possible maximum payload size on each PCI-E
device. However, if improperly configured, fatal bus errors can occur.
Thus, it is important to ensure that PCI-E payloads sends by a device
are never larger than the MPS setting of all devices on the way to the
destination.
This can be achieved two ways:
- A conservative approach is to use the smallest common denominator of
the entire tree below a root complex for every device on that fabric.
This means for example that having a 128 bytes MPS USB controller on one
leg of a switch will dramatically reduce performances of a video card or
10GE adapter on another leg of that same switch.
It also means that any hierarchy supporting hotplug slots (including
expresscard or thunderbolt I suppose, dbl check that) will have to be
entirely clamped to 128 bytes since we cannot predict what will be
plugged into those slots, and we cannot change the MPS on a "live"
system.
- A more optimal way is possible, if it falls within a couple of
constraints:
* The top-level host bridge will never generate packets larger than the
smallest TLP (or if it can be controlled independently from its MPS at
least)
* The device will never generate packets larger than MPS (which can be
configured via MRRS)
* No support of direct PCI-E <-> PCI-E transfers between devices without
some additional code to specifically deal with that case
Then we can use an approach that basically ignores downstream requests
and focuses exclusively on upstream requests. In that case, all we need
to care about is that a device MPS is no larger than its parent MPS,
which allows us to keep all switches/bridges to the max MPS supported by
their parent and eventually the PHB.
In this case, your USB controller would no longer "starve" your 10GE
Ethernet and your hotplug slots won't affect your global MPS.
Additionally, the hotplugged devices themselves can be configured to a
larger MPS up to the value configured in the hotplug bridge.
To choose between the two available options, two PCI kernel boot args
have been added to the PCI calls. "pcie_bus_safe" will provide the
former behavior, while "pcie_bus_perf" will perform the latter behavior.
By default, the latter behavior is used.
NOTE: due to the location of the enablement, each arch will need to add
calls to this function. This patch only enables x86.
This patch includes a number of changes recommended by Benjamin
Herrenschmidt.
Tested-by: Jordan_Hargrave@dell.com
Signed-off-by: Jon Mason <mason@myri.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-21 03:20:54 +07:00
|
|
|
int pcie_get_mps(struct pci_dev *dev);
|
|
|
|
int pcie_set_mps(struct pci_dev *dev, int mps);
|
PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
Add pcie_bandwidth_available() to compute the bandwidth available to a
device. This may be limited by the device itself or by a slower upstream
link leading to the device.
The available bandwidth at each link along the path is computed as:
link_width * link_speed * (1 - encoding_overhead)
2.5 and 5.0 GT/s links use 8b/10b encoding, which reduces the raw bandwidth
available by 20%; 8.0 GT/s and faster links use 128b/130b encoding, which
reduces it by about 1.5%.
The result is in Mb/s, i.e., megabits/second, of raw bandwidth.
Also return the device with the slowest link and the speed and width of
that link.
Signed-off-by: Tal Gilboa <talgi@mellanox.com>
[bhelgaas: changelog, leave pcie_get_minimum_link() alone for now, return
bw directly, use pci_upstream_bridge(), check "next_bw <= bw" to find
uppermost limiting device, return speed/width of the limiting device]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2018-03-30 20:37:44 +07:00
|
|
|
u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
|
|
|
|
enum pci_bus_speed *speed,
|
|
|
|
enum pcie_link_width *width);
|
2018-03-30 20:56:47 +07:00
|
|
|
void pcie_print_link_status(struct pci_dev *dev);
|
2018-08-10 03:04:14 +07:00
|
|
|
bool pcie_has_flr(struct pci_dev *dev);
|
2018-02-28 03:14:08 +07:00
|
|
|
int pcie_flr(struct pci_dev *dev);
|
2012-01-05 02:23:56 +07:00
|
|
|
int __pci_reset_function_locked(struct pci_dev *dev);
|
2008-10-21 16:38:25 +07:00
|
|
|
int pci_reset_function(struct pci_dev *dev);
|
2017-08-02 08:11:02 +07:00
|
|
|
int pci_reset_function_locked(struct pci_dev *dev);
|
PCI: Add pci_try_reset_function(), pci_try_reset_slot(), pci_try_reset_bus()
When doing a function/slot/bus reset PCI grabs the device_lock for each
device to block things like suspend and driver probes, but call paths exist
where this lock may already be held. This creates an opportunity for
deadlock. For instance, vfio allows userspace to issue resets so long as
it owns the device(s). If a driver unbind .remove callback races with
userspace issuing a reset, we have a deadlock as userspace gets stuck
waiting on device_lock while another thread has device_lock and waits for
.remove to complete. To resolve this, we can make a version of the reset
interfaces which use trylock. With this, we can safely attempt a reset and
return error to userspace if there is contention.
[bhelgaas: the deadlock happens when A (userspace) has a file descriptor for
the device, and B waits in this path:
driver_detach
device_lock # take device_lock
__device_release_driver
pci_device_remove # pci_bus_type.remove
vfio_pci_remove # pci_driver .remove
vfio_del_group_dev
wait_event(vfio.release_q, !vfio_dev_present) # wait (holding device_lock)
Now B is stuck until A gives up the file descriptor. If A tries to acquire
device_lock for any reason, we deadlock because A is waiting for B to release
the lock, and B is waiting for A to release the file descriptor.]
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-17 05:14:31 +07:00
|
|
|
int pci_try_reset_function(struct pci_dev *dev);
|
2013-08-15 03:06:05 +07:00
|
|
|
int pci_probe_reset_slot(struct pci_slot *slot);
|
|
|
|
int pci_probe_reset_bus(struct pci_bus *bus);
|
2018-07-20 06:04:15 +07:00
|
|
|
int pci_reset_bus(struct pci_dev *dev);
|
2014-06-19 14:22:44 +07:00
|
|
|
void pci_reset_secondary_bus(struct pci_dev *dev);
|
|
|
|
void pcibios_reset_secondary_bus(struct pci_dev *dev);
|
2008-11-22 01:38:52 +07:00
|
|
|
void pci_update_resource(struct pci_dev *dev, int resno);
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
|
2011-07-26 03:08:39 +07:00
|
|
|
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
|
2017-10-25 02:40:26 +07:00
|
|
|
void pci_release_resource(struct pci_dev *dev, int resno);
|
|
|
|
int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
|
2006-12-18 08:31:06 +07:00
|
|
|
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
|
2013-12-01 08:34:37 +07:00
|
|
|
bool pci_device_is_present(struct pci_dev *pdev);
|
2015-04-13 21:23:36 +07:00
|
|
|
void pci_ignore_hotplug(struct pci_dev *dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-04-13 14:06:42 +07:00
|
|
|
int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
|
|
|
|
irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
|
|
|
|
const char *fmt, ...);
|
|
|
|
void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* ROM control related routines */
|
2008-09-23 23:25:10 +07:00
|
|
|
int pci_enable_rom(struct pci_dev *pdev);
|
|
|
|
void pci_disable_rom(struct pci_dev *pdev);
|
2005-08-09 11:20:10 +07:00
|
|
|
void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
|
2013-03-27 04:25:54 +07:00
|
|
|
void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/* Power management related routines */
|
|
|
|
int pci_save_state(struct pci_dev *dev);
|
2010-12-01 06:43:26 +07:00
|
|
|
void pci_restore_state(struct pci_dev *dev);
|
2011-05-10 23:02:27 +07:00
|
|
|
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
|
2014-12-04 04:40:31 +07:00
|
|
|
int pci_load_saved_state(struct pci_dev *dev,
|
|
|
|
struct pci_saved_state *state);
|
2011-05-10 23:02:27 +07:00
|
|
|
int pci_load_and_free_saved_state(struct pci_dev *dev,
|
|
|
|
struct pci_saved_state **state);
|
2013-12-18 06:43:45 +07:00
|
|
|
struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
|
|
|
|
struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
|
|
|
|
u16 cap);
|
|
|
|
int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
|
|
|
|
int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
|
|
|
|
u16 cap, unsigned int size);
|
2009-03-27 04:51:40 +07:00
|
|
|
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
|
2005-09-10 05:43:46 +07:00
|
|
|
int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
|
|
|
|
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
|
2008-07-19 19:39:24 +07:00
|
|
|
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
|
2008-08-08 05:14:24 +07:00
|
|
|
void pci_pme_active(struct pci_dev *dev, bool enable);
|
2017-06-24 06:57:35 +07:00
|
|
|
int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
|
2008-08-19 02:38:00 +07:00
|
|
|
int pci_wake_from_d3(struct pci_dev *dev, bool enable);
|
2008-07-07 08:35:26 +07:00
|
|
|
int pci_prepare_to_sleep(struct pci_dev *dev);
|
|
|
|
int pci_back_from_sleep(struct pci_dev *dev);
|
2010-02-18 05:44:09 +07:00
|
|
|
bool pci_dev_run_wake(struct pci_dev *dev);
|
2010-10-05 01:22:26 +07:00
|
|
|
bool pci_check_pme_status(struct pci_dev *dev);
|
|
|
|
void pci_pme_wakeup_bus(struct pci_bus *bus);
|
2016-06-02 15:17:12 +07:00
|
|
|
void pci_d3cold_enable(struct pci_dev *dev);
|
|
|
|
void pci_d3cold_disable(struct pci_dev *dev);
|
2017-08-15 10:23:23 +07:00
|
|
|
bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
|
2018-03-03 16:53:24 +07:00
|
|
|
void pci_wakeup_bus(struct pci_bus *bus);
|
|
|
|
void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
PCI: Add Virtual Channel to save/restore support
While we don't really have any infrastructure for making use of VC
support, the system BIOS can configure the topology to non-default
VC values prior to boot. This may be due to silicon bugs, desire to
reserve traffic classes, or perhaps just BIOS bugs. When we reset
devices, the VC configuration may return to default values, which can
be incompatible with devices upstream. For instance, Nvidia GRID
cards provide a PCIe switch and some number of GPUs, all supporting
VC. The power-on default for VC is to support TC0-7 across VC0,
however some platforms will only enable TC0/VC0 mapping across the
topology. When we do a secondary bus reset on the downstream switch
port, the GPU is reset to a TC0-7/VC0 mapping while the opposite end
of the link only enables TC0/VC0. If the GPU attempts to use TC1-7,
it fails.
This patch attempts to provide complete support for VC save/restore,
even beyond the minimally required use case above. This includes
save/restore and reload of the arbitration table, save/restore and
reload of the port arbitration tables, and re-enabling of the
channels for VC, VC9, and MFVC capabilities.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-18 06:43:51 +07:00
|
|
|
/* PCI Virtual Channel */
|
|
|
|
int pci_save_vc_state(struct pci_dev *dev);
|
|
|
|
void pci_restore_vc_state(struct pci_dev *dev);
|
|
|
|
void pci_allocate_vc_save_buffers(struct pci_dev *dev);
|
2011-01-14 23:53:04 +07:00
|
|
|
|
2010-01-27 00:10:03 +07:00
|
|
|
/* For use by arch with custom probe code */
|
|
|
|
void set_pcie_port_type(struct pci_dev *pdev);
|
|
|
|
void set_pcie_hotplug_bridge(struct pci_dev *pdev);
|
|
|
|
|
2007-07-17 11:27:10 +07:00
|
|
|
/* Functions for PCI Hotplug drivers to use */
|
2008-01-31 06:21:33 +07:00
|
|
|
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
|
2012-01-21 17:08:22 +07:00
|
|
|
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
|
2009-03-21 03:56:25 +07:00
|
|
|
unsigned int pci_rescan_bus(struct pci_bus *bus);
|
2014-01-10 21:22:18 +07:00
|
|
|
void pci_lock_rescan_remove(void);
|
|
|
|
void pci_unlock_rescan_remove(void);
|
2007-07-17 11:27:10 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Vital Product Data routines */
|
2008-12-19 00:17:16 +07:00
|
|
|
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
|
|
|
|
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
|
2016-04-16 01:00:11 +07:00
|
|
|
int pci_set_vpd_size(struct pci_dev *dev, size_t len);
|
2008-12-19 00:17:16 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
|
2011-11-22 01:54:13 +07:00
|
|
|
resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
|
2009-02-19 01:44:29 +07:00
|
|
|
void pci_bus_assign_resources(const struct pci_bus *bus);
|
2016-06-08 18:04:47 +07:00
|
|
|
void pci_bus_claim_resources(struct pci_bus *bus);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_bus_size_bridges(struct pci_bus *bus);
|
|
|
|
int pci_claim_resource(struct pci_dev *, int);
|
PCI: Add pci_claim_bridge_resource() to clip window if necessary
Add pci_claim_bridge_resource() to claim a PCI-PCI bridge window. This is
like regular pci_claim_resource(), except that if we fail to claim the
window, we check to see if we can reduce the size of the window and try
again.
This is for scenarios like this:
pci_bus 0000:00: root bus resource [mem 0xc0000000-0xffffffff]
pci 0000:00:01.0: bridge window [mem 0xbdf00000-0xddefffff 64bit pref]
pci 0000:01:00.0: reg 0x10: [mem 0xc0000000-0xcfffffff pref]
The 00:01.0 window is illegal: it starts before the host bridge window, so
we have to assume the [0xbdf00000-0xbfffffff] region is inaccessible. We
can make it legal by clipping it to [mem 0xc0000000-0xddefffff 64bit pref].
Previously we discarded the 00:01.0 window and tried to reassign that part
of the hierarchy from scratch. That is a problem because Linux doesn't
always assign things optimally. For example, in this case, BIOS put the
01:00.0 device in a prefetchable window below 4GB, but after 5b28541552ef,
Linux puts the prefetchable window above 4GB where the 32-bit 01:00.0
device can't use it.
Clipping the 00:01.0 window is less intrusive than completely reassigning
things and is sufficient to let us use most of the BIOS configuration. Of
course, it's possible that devices below 00:01.0 will no longer fit. If
that's the case, we'll have to reassign things. But that's a separate
problem.
[bhelgaas: changelog, split into separate patch]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik <kordikmarek@gmail.com>
Fixes: 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v3.16+
2015-01-16 05:21:49 +07:00
|
|
|
int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_assign_unassigned_resources(void);
|
2010-01-22 16:02:25 +07:00
|
|
|
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
|
2012-10-31 03:31:10 +07:00
|
|
|
void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
|
2013-07-23 04:37:18 +07:00
|
|
|
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
|
2017-10-25 02:40:26 +07:00
|
|
|
int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pdev_enable_device(struct pci_dev *);
|
2008-03-05 01:56:47 +07:00
|
|
|
int pci_enable_resources(struct pci_dev *, int mask);
|
2017-06-29 03:14:02 +07:00
|
|
|
void pci_assign_irq(struct pci_dev *dev);
|
2016-09-15 15:07:03 +07:00
|
|
|
struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
|
2005-04-17 05:20:36 +07:00
|
|
|
#define HAVE_PCI_REQ_REGIONS 2
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pci_request_regions(struct pci_dev *, const char *);
|
2008-10-23 09:55:31 +07:00
|
|
|
int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_release_regions(struct pci_dev *);
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pci_request_region(struct pci_dev *, int, const char *);
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_release_region(struct pci_dev *, int);
|
2006-12-18 08:31:06 +07:00
|
|
|
int pci_request_selected_regions(struct pci_dev *, int, const char *);
|
2008-10-23 09:55:31 +07:00
|
|
|
int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
|
2006-12-18 08:31:06 +07:00
|
|
|
void pci_release_selected_regions(struct pci_dev *, int);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
/* drivers/pci/bus.c */
|
2013-05-25 20:48:29 +07:00
|
|
|
struct pci_bus *pci_bus_get(struct pci_bus *bus);
|
|
|
|
void pci_bus_put(struct pci_bus *bus);
|
2011-10-29 05:25:35 +07:00
|
|
|
void pci_add_resource(struct list_head *resources, struct resource *res);
|
2012-02-24 10:19:00 +07:00
|
|
|
void pci_add_resource_offset(struct list_head *resources, struct resource *res,
|
|
|
|
resource_size_t offset);
|
2011-10-29 05:25:35 +07:00
|
|
|
void pci_free_resource_list(struct list_head *resources);
|
2016-05-29 06:09:16 +07:00
|
|
|
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
|
|
|
|
unsigned int flags);
|
2010-02-24 00:24:36 +07:00
|
|
|
struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
|
|
|
|
void pci_bus_remove_resources(struct pci_bus *bus);
|
2016-05-29 06:09:16 +07:00
|
|
|
int devm_request_pci_bus_resources(struct device *dev,
|
|
|
|
struct list_head *resources);
|
2010-02-24 00:24:36 +07:00
|
|
|
|
2018-09-01 00:34:14 +07:00
|
|
|
/* Temporary until new and working PCI SBR API in place */
|
|
|
|
int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
|
|
|
|
|
2010-02-24 00:24:31 +07:00
|
|
|
#define pci_bus_for_each_resource(bus, res, i) \
|
2010-02-24 00:24:36 +07:00
|
|
|
for (i = 0; \
|
|
|
|
(res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
|
|
|
|
i++)
|
2010-02-24 00:24:31 +07:00
|
|
|
|
2006-08-15 12:43:17 +07:00
|
|
|
int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
|
|
|
|
struct resource *res, resource_size_t size,
|
|
|
|
resource_size_t align, resource_size_t min,
|
2014-03-08 03:51:12 +07:00
|
|
|
unsigned long type_mask,
|
2010-01-01 23:40:50 +07:00
|
|
|
resource_size_t (*alignf)(void *,
|
|
|
|
const struct resource *,
|
2010-01-01 23:40:49 +07:00
|
|
|
resource_size_t,
|
|
|
|
resource_size_t),
|
2006-08-15 12:43:17 +07:00
|
|
|
void *alignf_data);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2014-09-29 21:29:30 +07:00
|
|
|
|
2018-03-15 01:15:52 +07:00
|
|
|
int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
|
|
|
|
resource_size_t size);
|
2016-05-12 05:34:51 +07:00
|
|
|
unsigned long pci_address_to_pio(phys_addr_t addr);
|
|
|
|
phys_addr_t pci_pio_to_address(unsigned long pio);
|
2014-09-29 21:29:30 +07:00
|
|
|
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
|
2018-07-19 03:40:26 +07:00
|
|
|
int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
|
|
|
|
phys_addr_t phys_addr);
|
2016-06-11 02:55:11 +07:00
|
|
|
void pci_unmap_iospace(struct resource *res);
|
2017-04-19 23:48:55 +07:00
|
|
|
void __iomem *devm_pci_remap_cfgspace(struct device *dev,
|
|
|
|
resource_size_t offset,
|
|
|
|
resource_size_t size);
|
|
|
|
void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
|
|
|
|
struct resource *res);
|
2014-09-29 21:29:30 +07:00
|
|
|
|
PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-28 07:23:51 +07:00
|
|
|
static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
|
2013-12-21 22:33:26 +07:00
|
|
|
{
|
|
|
|
struct pci_bus_region region;
|
|
|
|
|
|
|
|
pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
|
|
|
|
return region.start;
|
|
|
|
}
|
|
|
|
|
2005-10-28 04:12:54 +07:00
|
|
|
/* Proper probing supporting hot-pluggable devices */
|
2007-01-16 02:50:02 +07:00
|
|
|
int __must_check __pci_register_driver(struct pci_driver *, struct module *,
|
|
|
|
const char *mod_name);
|
2008-07-31 02:07:04 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
|
2008-07-31 02:07:04 +07:00
|
|
|
#define pci_register_driver(driver) \
|
|
|
|
__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
|
2005-10-28 04:12:54 +07:00
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
void pci_unregister_driver(struct pci_driver *dev);
|
2011-11-19 01:12:49 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* module_pci_driver() - Helper macro for registering a PCI driver
|
|
|
|
* @__pci_driver: pci_driver struct
|
|
|
|
*
|
|
|
|
* Helper macro for PCI drivers which do not do anything special in module
|
|
|
|
* init/exit. This eliminates a lot of boilerplate. Each module may only
|
|
|
|
* use this macro once, and calling it replaces module_init() and module_exit()
|
|
|
|
*/
|
|
|
|
#define module_pci_driver(__pci_driver) \
|
2017-12-03 02:21:37 +07:00
|
|
|
module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
|
2011-11-19 01:12:49 +07:00
|
|
|
|
2015-08-26 07:25:37 +07:00
|
|
|
/**
|
|
|
|
* builtin_pci_driver() - Helper macro for registering a PCI driver
|
|
|
|
* @__pci_driver: pci_driver struct
|
|
|
|
*
|
|
|
|
* Helper macro for PCI drivers which do not do anything special in their
|
|
|
|
* init code. This eliminates a lot of boilerplate. Each driver may only
|
|
|
|
* use this macro once, and calling it replaces device_initcall(...)
|
|
|
|
*/
|
|
|
|
#define builtin_pci_driver(__pci_driver) \
|
|
|
|
builtin_driver(__pci_driver, pci_register_driver)
|
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
|
2009-09-03 13:26:36 +07:00
|
|
|
int pci_add_dynid(struct pci_driver *drv,
|
|
|
|
unsigned int vendor, unsigned int device,
|
|
|
|
unsigned int subvendor, unsigned int subdevice,
|
|
|
|
unsigned int class, unsigned int class_mask,
|
|
|
|
unsigned long driver_data);
|
2008-01-31 06:21:33 +07:00
|
|
|
const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
|
|
|
|
struct pci_dev *dev);
|
|
|
|
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
|
|
|
|
int pass);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2009-06-16 12:34:38 +07:00
|
|
|
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
|
2005-08-18 11:33:01 +07:00
|
|
|
void *userdata);
|
2005-12-13 14:09:16 +07:00
|
|
|
int pci_cfg_space_size(struct pci_dev *dev);
|
2008-01-31 06:21:33 +07:00
|
|
|
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
|
2011-09-12 00:08:38 +07:00
|
|
|
void pci_setup_bridge(struct pci_bus *bus);
|
2012-09-12 05:59:45 +07:00
|
|
|
resource_size_t pcibios_window_alignment(struct pci_bus *bus,
|
|
|
|
unsigned long type);
|
2005-08-18 11:33:01 +07:00
|
|
|
|
2010-06-01 12:32:24 +07:00
|
|
|
#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
|
|
|
|
#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
|
|
|
|
|
2009-08-11 12:52:06 +07:00
|
|
|
int pci_set_vga_state(struct pci_dev *pdev, bool decode,
|
2010-06-01 12:32:24 +07:00
|
|
|
unsigned int command_bits, u32 flags);
|
2016-03-08 00:39:16 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
|
|
|
|
#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
|
|
|
|
#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
|
|
|
|
#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
|
2019-05-24 05:30:51 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Virtual interrupts allow for more interrupts to be allocated
|
|
|
|
* than the device has interrupts for. These are not programmed
|
|
|
|
* into the device's MSI-X table and must be handled by some
|
|
|
|
* other driver means.
|
|
|
|
*/
|
|
|
|
#define PCI_IRQ_VIRTUAL (1 << 4)
|
|
|
|
|
2016-08-11 21:11:04 +07:00
|
|
|
#define PCI_IRQ_ALL_TYPES \
|
|
|
|
(PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
|
2016-07-12 16:20:17 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* kmem_cache style wrapper around pci_alloc_consistent() */
|
|
|
|
|
|
|
|
#include <linux/dmapool.h>
|
|
|
|
|
|
|
|
#define pci_pool dma_pool
|
|
|
|
#define pci_pool_create(name, pdev, size, align, allocation) \
|
|
|
|
dma_pool_create(name, &pdev->dev, size, align, allocation)
|
|
|
|
#define pci_pool_destroy(pool) dma_pool_destroy(pool)
|
|
|
|
#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
|
2015-09-09 05:02:30 +07:00
|
|
|
#define pci_pool_zalloc(pool, flags, handle) \
|
|
|
|
dma_pool_zalloc(pool, flags, handle)
|
2005-04-17 05:20:36 +07:00
|
|
|
#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
|
|
|
|
|
|
|
|
struct msix_entry {
|
2017-12-03 02:21:37 +07:00
|
|
|
u32 vector; /* Kernel uses to write allocated vector */
|
|
|
|
u16 entry; /* Driver uses to specify entry, OS writes */
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2014-01-14 07:01:11 +07:00
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
|
|
int pci_msi_vec_count(struct pci_dev *dev);
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_disable_msi(struct pci_dev *dev);
|
2014-01-14 07:01:11 +07:00
|
|
|
int pci_msix_vec_count(struct pci_dev *dev);
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_disable_msix(struct pci_dev *dev);
|
|
|
|
void pci_restore_msi_state(struct pci_dev *dev);
|
|
|
|
int pci_msi_enabled(void);
|
2017-01-10 03:37:40 +07:00
|
|
|
int pci_enable_msi(struct pci_dev *dev);
|
2014-01-14 07:01:11 +07:00
|
|
|
int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
|
|
|
|
int minvec, int maxvec);
|
2014-02-13 21:25:02 +07:00
|
|
|
static inline int pci_enable_msix_exact(struct pci_dev *dev,
|
|
|
|
struct msix_entry *entries, int nvec)
|
|
|
|
{
|
|
|
|
int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
|
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
|
|
|
return 0;
|
|
|
|
}
|
2016-11-09 08:15:05 +07:00
|
|
|
int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
|
|
|
|
unsigned int max_vecs, unsigned int flags,
|
genirq/affinity: Add new callback for (re)calculating interrupt sets
The interrupt affinity spreading mechanism supports to spread out
affinities for one or more interrupt sets. A interrupt set contains one or
more interrupts. Each set is mapped to a specific functionality of a
device, e.g. general I/O queues and read I/O queus of multiqueue block
devices.
The number of interrupts per set is defined by the driver. It depends on
the total number of available interrupts for the device, which is
determined by the PCI capabilites and the availability of underlying CPU
resources, and the number of queues which the device provides and the
driver wants to instantiate.
The driver passes initial configuration for the interrupt allocation via a
pointer to struct irq_affinity.
Right now the allocation mechanism is complex as it requires to have a loop
in the driver to determine the maximum number of interrupts which are
provided by the PCI capabilities and the underlying CPU resources. This
loop would have to be replicated in every driver which wants to utilize
this mechanism. That's unwanted code duplication and error prone.
In order to move this into generic facilities it is required to have a
mechanism, which allows the recalculation of the interrupt sets and their
size, in the core code. As the core code does not have any knowledge about the
underlying device, a driver specific callback is required in struct
irq_affinity, which can be invoked by the core code. The callback gets the
number of available interupts as an argument, so the driver can calculate the
corresponding number and size of interrupt sets.
At the moment the struct irq_affinity pointer which is handed in from the
driver and passed through to several core functions is marked 'const', but for
the callback to be able to modify the data in the struct it's required to
remove the 'const' qualifier.
Add the optional callback to struct irq_affinity, which allows drivers to
recalculate the number and size of interrupt sets and remove the 'const'
qualifier.
For simple invocations, which do not supply a callback, a default callback
is installed, which just sets nr_sets to 1 and transfers the number of
spreadable vectors to the set_size array at index 0.
This is for now guarded by a check for nr_sets != 0 to keep the NVME driver
working until it is converted to the callback mechanism.
To make sure that the driver configuration is correct under all circumstances
the callback is invoked even when there are no interrupts for queues left,
i.e. the pre/post requirements already exhaust the numner of available
interrupts.
At the PCI layer irq_create_affinity_masks() has to be invoked even for the
case where the legacy interrupt is used. That ensures that the callback is
invoked and the device driver can adjust to that situation.
[ tglx: Fixed the simple case (no sets required). Moved the sanity check
for nr_sets after the invocation of the callback so it catches
broken drivers. Fixed the kernel doc comments for struct
irq_affinity and de-'This patch'-ed the changelog ]
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Bjorn Helgaas <helgaas@kernel.org>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: linux-block@vger.kernel.org
Cc: Sagi Grimberg <sagi@grimberg.me>
Cc: linux-nvme@lists.infradead.org
Cc: linux-pci@vger.kernel.org
Cc: Keith Busch <keith.busch@intel.com>
Cc: Sumit Saxena <sumit.saxena@broadcom.com>
Cc: Kashyap Desai <kashyap.desai@broadcom.com>
Cc: Shivasharan Srikanteshwara <shivasharan.srikanteshwara@broadcom.com>
Link: https://lkml.kernel.org/r/20190216172228.512444498@linutronix.de
2019-02-17 00:13:09 +07:00
|
|
|
struct irq_affinity *affd);
|
2016-11-09 08:15:05 +07:00
|
|
|
|
2016-07-12 16:20:17 +07:00
|
|
|
void pci_free_irq_vectors(struct pci_dev *dev);
|
|
|
|
int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
|
2016-09-14 21:18:51 +07:00
|
|
|
const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
|
2017-02-02 00:53:15 +07:00
|
|
|
int pci_irq_get_node(struct pci_dev *pdev, int vec);
|
2016-07-12 16:20:17 +07:00
|
|
|
|
2014-01-14 07:01:11 +07:00
|
|
|
#else
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
|
|
|
|
static inline void pci_disable_msi(struct pci_dev *dev) { }
|
|
|
|
static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
|
|
|
|
static inline void pci_disable_msix(struct pci_dev *dev) { }
|
|
|
|
static inline void pci_restore_msi_state(struct pci_dev *dev) { }
|
|
|
|
static inline int pci_msi_enabled(void) { return 0; }
|
2017-01-10 03:37:40 +07:00
|
|
|
static inline int pci_enable_msi(struct pci_dev *dev)
|
2014-02-13 21:25:02 +07:00
|
|
|
{ return -ENOSYS; }
|
2013-12-30 14:28:16 +07:00
|
|
|
static inline int pci_enable_msix_range(struct pci_dev *dev,
|
2017-12-03 02:21:37 +07:00
|
|
|
struct msix_entry *entries, int minvec, int maxvec)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return -ENOSYS; }
|
2014-02-13 21:25:02 +07:00
|
|
|
static inline int pci_enable_msix_exact(struct pci_dev *dev,
|
2017-12-03 02:21:37 +07:00
|
|
|
struct msix_entry *entries, int nvec)
|
2014-02-13 21:25:02 +07:00
|
|
|
{ return -ENOSYS; }
|
2016-11-09 08:15:05 +07:00
|
|
|
|
|
|
|
static inline int
|
|
|
|
pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
|
|
|
|
unsigned int max_vecs, unsigned int flags,
|
genirq/affinity: Add new callback for (re)calculating interrupt sets
The interrupt affinity spreading mechanism supports to spread out
affinities for one or more interrupt sets. A interrupt set contains one or
more interrupts. Each set is mapped to a specific functionality of a
device, e.g. general I/O queues and read I/O queus of multiqueue block
devices.
The number of interrupts per set is defined by the driver. It depends on
the total number of available interrupts for the device, which is
determined by the PCI capabilites and the availability of underlying CPU
resources, and the number of queues which the device provides and the
driver wants to instantiate.
The driver passes initial configuration for the interrupt allocation via a
pointer to struct irq_affinity.
Right now the allocation mechanism is complex as it requires to have a loop
in the driver to determine the maximum number of interrupts which are
provided by the PCI capabilities and the underlying CPU resources. This
loop would have to be replicated in every driver which wants to utilize
this mechanism. That's unwanted code duplication and error prone.
In order to move this into generic facilities it is required to have a
mechanism, which allows the recalculation of the interrupt sets and their
size, in the core code. As the core code does not have any knowledge about the
underlying device, a driver specific callback is required in struct
irq_affinity, which can be invoked by the core code. The callback gets the
number of available interupts as an argument, so the driver can calculate the
corresponding number and size of interrupt sets.
At the moment the struct irq_affinity pointer which is handed in from the
driver and passed through to several core functions is marked 'const', but for
the callback to be able to modify the data in the struct it's required to
remove the 'const' qualifier.
Add the optional callback to struct irq_affinity, which allows drivers to
recalculate the number and size of interrupt sets and remove the 'const'
qualifier.
For simple invocations, which do not supply a callback, a default callback
is installed, which just sets nr_sets to 1 and transfers the number of
spreadable vectors to the set_size array at index 0.
This is for now guarded by a check for nr_sets != 0 to keep the NVME driver
working until it is converted to the callback mechanism.
To make sure that the driver configuration is correct under all circumstances
the callback is invoked even when there are no interrupts for queues left,
i.e. the pre/post requirements already exhaust the numner of available
interrupts.
At the PCI layer irq_create_affinity_masks() has to be invoked even for the
case where the legacy interrupt is used. That ensures that the callback is
invoked and the device driver can adjust to that situation.
[ tglx: Fixed the simple case (no sets required). Moved the sanity check
for nr_sets after the invocation of the callback so it catches
broken drivers. Fixed the kernel doc comments for struct
irq_affinity and de-'This patch'-ed the changelog ]
Signed-off-by: Ming Lei <ming.lei@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Bjorn Helgaas <helgaas@kernel.org>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: linux-block@vger.kernel.org
Cc: Sagi Grimberg <sagi@grimberg.me>
Cc: linux-nvme@lists.infradead.org
Cc: linux-pci@vger.kernel.org
Cc: Keith Busch <keith.busch@intel.com>
Cc: Sumit Saxena <sumit.saxena@broadcom.com>
Cc: Kashyap Desai <kashyap.desai@broadcom.com>
Cc: Shivasharan Srikanteshwara <shivasharan.srikanteshwara@broadcom.com>
Link: https://lkml.kernel.org/r/20190216172228.512444498@linutronix.de
2019-02-17 00:13:09 +07:00
|
|
|
struct irq_affinity *aff_desc)
|
2016-07-12 16:20:17 +07:00
|
|
|
{
|
2017-05-20 23:59:54 +07:00
|
|
|
if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
|
|
|
|
return 1;
|
|
|
|
return -ENOSPC;
|
2016-07-12 16:20:17 +07:00
|
|
|
}
|
2016-11-09 08:15:05 +07:00
|
|
|
|
2016-07-12 16:20:17 +07:00
|
|
|
static inline void pci_free_irq_vectors(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
|
|
|
|
{
|
|
|
|
if (WARN_ON_ONCE(nr > 0))
|
|
|
|
return -EINVAL;
|
|
|
|
return dev->irq;
|
|
|
|
}
|
2016-09-14 21:18:51 +07:00
|
|
|
static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
|
|
|
|
int vec)
|
|
|
|
{
|
|
|
|
return cpu_possible_mask;
|
|
|
|
}
|
2017-02-02 00:53:15 +07:00
|
|
|
|
|
|
|
static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
|
|
|
|
{
|
|
|
|
return first_online_node;
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif
|
|
|
|
|
2016-11-09 08:15:05 +07:00
|
|
|
static inline int
|
|
|
|
pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
|
|
|
|
unsigned int max_vecs, unsigned int flags)
|
|
|
|
{
|
|
|
|
return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
|
|
|
|
NULL);
|
|
|
|
}
|
|
|
|
|
2017-08-16 02:02:17 +07:00
|
|
|
/**
|
|
|
|
* pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
|
|
|
|
* @d: the INTx IRQ domain
|
|
|
|
* @node: the DT node for the device whose interrupt we're translating
|
|
|
|
* @intspec: the interrupt specifier data from the DT
|
|
|
|
* @intsize: the number of entries in @intspec
|
|
|
|
* @out_hwirq: pointer at which to write the hwirq number
|
|
|
|
* @out_type: pointer at which to write the interrupt type
|
|
|
|
*
|
|
|
|
* Translate a PCI INTx interrupt number from device tree in the range 1-4, as
|
|
|
|
* stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
|
|
|
|
* 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
|
|
|
|
* INTx value to obtain the hwirq number.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
|
|
|
|
*/
|
|
|
|
static inline int pci_irqd_intx_xlate(struct irq_domain *d,
|
|
|
|
struct device_node *node,
|
|
|
|
const u32 *intspec,
|
|
|
|
unsigned int intsize,
|
|
|
|
unsigned long *out_hwirq,
|
|
|
|
unsigned int *out_type)
|
|
|
|
{
|
|
|
|
const u32 intx = intspec[0];
|
|
|
|
|
|
|
|
if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
*out_hwirq = intx - PCI_INTERRUPT_INTA;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-15 06:07:22 +07:00
|
|
|
#ifdef CONFIG_PCIEPORTBUS
|
2011-01-07 06:55:09 +07:00
|
|
|
extern bool pcie_ports_disabled;
|
2018-05-24 05:24:08 +07:00
|
|
|
extern bool pcie_ports_native;
|
2011-01-15 06:07:22 +07:00
|
|
|
#else
|
|
|
|
#define pcie_ports_disabled true
|
2018-05-24 05:24:08 +07:00
|
|
|
#define pcie_ports_native false
|
2011-01-15 06:07:22 +07:00
|
|
|
#endif
|
2011-01-07 06:55:09 +07:00
|
|
|
|
2014-01-14 07:01:11 +07:00
|
|
|
#ifdef CONFIG_PCIEASPM
|
2013-04-13 01:02:59 +07:00
|
|
|
bool pcie_aspm_support_enabled(void);
|
2014-01-14 07:01:11 +07:00
|
|
|
#else
|
|
|
|
static inline bool pcie_aspm_support_enabled(void) { return false; }
|
2008-11-11 05:30:55 +07:00
|
|
|
#endif
|
|
|
|
|
2011-01-07 06:55:09 +07:00
|
|
|
#ifdef CONFIG_PCIEAER
|
|
|
|
bool pci_aer_available(void);
|
|
|
|
#else
|
|
|
|
static inline bool pci_aer_available(void) { return false; }
|
|
|
|
#endif
|
|
|
|
|
2014-01-14 07:01:11 +07:00
|
|
|
#ifdef CONFIG_PCIE_ECRC
|
2013-04-13 01:02:59 +07:00
|
|
|
void pcie_set_ecrc_checking(struct pci_dev *dev);
|
|
|
|
void pcie_ecrc_get_policy(char *str);
|
2014-01-14 07:01:11 +07:00
|
|
|
#else
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
|
|
|
|
static inline void pcie_ecrc_get_policy(char *str) { }
|
2009-04-23 05:52:09 +07:00
|
|
|
#endif
|
|
|
|
|
2018-05-11 05:56:02 +07:00
|
|
|
bool pci_ats_disabled(void);
|
|
|
|
|
2016-06-13 23:01:51 +07:00
|
|
|
#ifdef CONFIG_PCIE_PTM
|
|
|
|
int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
|
|
|
|
#else
|
|
|
|
static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
|
|
|
|
{ return -EINVAL; }
|
|
|
|
#endif
|
|
|
|
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_cfg_access_lock(struct pci_dev *dev);
|
|
|
|
bool pci_cfg_access_trylock(struct pci_dev *dev);
|
|
|
|
void pci_cfg_access_unlock(struct pci_dev *dev);
|
2005-09-27 15:21:55 +07:00
|
|
|
|
2005-07-29 01:37:33 +07:00
|
|
|
/*
|
|
|
|
* PCI domain support. Sometimes called PCI segment (eg by ACPI),
|
2013-11-15 01:28:18 +07:00
|
|
|
* a PCI domain is defined to be a set of PCI buses which share
|
2005-07-29 01:37:33 +07:00
|
|
|
* configuration space.
|
|
|
|
*/
|
2007-10-12 03:57:27 +07:00
|
|
|
#ifdef CONFIG_PCI_DOMAINS
|
|
|
|
extern int pci_domains_supported;
|
|
|
|
#else
|
|
|
|
enum { pci_domains_supported = 0 };
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
|
|
|
|
static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
|
2007-10-12 03:57:27 +07:00
|
|
|
#endif /* CONFIG_PCI_DOMAINS */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2014-09-29 21:29:26 +07:00
|
|
|
/*
|
|
|
|
* Generic implementation for PCI domain support. If your
|
|
|
|
* architecture does not need custom management of PCI
|
|
|
|
* domains then this implementation will be used
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_PCI_DOMAINS_GENERIC
|
|
|
|
static inline int pci_domain_nr(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
return bus->domain_nr;
|
|
|
|
}
|
2016-06-11 03:36:26 +07:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
|
2014-09-29 21:29:26 +07:00
|
|
|
#else
|
2016-06-11 03:36:26 +07:00
|
|
|
static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
|
|
|
|
{ return 0; }
|
|
|
|
#endif
|
2016-06-11 02:55:14 +07:00
|
|
|
int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
|
2014-09-29 21:29:26 +07:00
|
|
|
#endif
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Some architectures require additional setup to direct VGA traffic */
|
2010-02-03 05:38:13 +07:00
|
|
|
typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
|
2017-12-03 02:21:37 +07:00
|
|
|
unsigned int command_bits, u32 flags);
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_register_set_vga_state(arch_set_vga_state_t func);
|
2010-02-03 05:38:13 +07:00
|
|
|
|
2016-06-07 14:44:01 +07:00
|
|
|
static inline int
|
|
|
|
pci_request_io_regions(struct pci_dev *pdev, const char *name)
|
|
|
|
{
|
|
|
|
return pci_request_selected_regions(pdev,
|
|
|
|
pci_select_bars(pdev, IORESOURCE_IO), name);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
pci_release_io_regions(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pci_release_selected_regions(pdev,
|
|
|
|
pci_select_bars(pdev, IORESOURCE_IO));
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int
|
|
|
|
pci_request_mem_regions(struct pci_dev *pdev, const char *name)
|
|
|
|
{
|
|
|
|
return pci_request_selected_regions(pdev,
|
|
|
|
pci_select_bars(pdev, IORESOURCE_MEM), name);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
pci_release_mem_regions(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pci_release_selected_regions(pdev,
|
|
|
|
pci_select_bars(pdev, IORESOURCE_MEM));
|
|
|
|
}
|
|
|
|
|
2005-07-29 01:37:33 +07:00
|
|
|
#else /* CONFIG_PCI is not enabled */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2016-02-06 03:57:47 +07:00
|
|
|
static inline void pci_set_flags(int flags) { }
|
|
|
|
static inline void pci_add_flags(int flags) { }
|
|
|
|
static inline void pci_clear_flags(int flags) { }
|
|
|
|
static inline int pci_has_flag(int flag) { return 0; }
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/*
|
2017-12-03 02:21:37 +07:00
|
|
|
* If the system does not have PCI, clearly these return errors. Define
|
|
|
|
* these as simple inline functions to avoid hair in drivers.
|
2005-04-17 05:20:36 +07:00
|
|
|
*/
|
2008-01-31 06:21:33 +07:00
|
|
|
#define _PCI_NOP(o, s, t) \
|
|
|
|
static inline int pci_##o##_config_##s(struct pci_dev *dev, \
|
|
|
|
int where, t val) \
|
2005-04-17 05:20:36 +07:00
|
|
|
{ return PCIBIOS_FUNC_NOT_SUPPORTED; }
|
2008-01-31 06:21:33 +07:00
|
|
|
|
|
|
|
#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
|
|
|
|
_PCI_NOP(o, word, u16 x) \
|
|
|
|
_PCI_NOP(o, dword, u32 x)
|
2005-04-17 05:20:36 +07:00
|
|
|
_PCI_NOP_ALL(read, *)
|
|
|
|
_PCI_NOP_ALL(write,)
|
|
|
|
|
2006-10-22 00:24:12 +07:00
|
|
|
static inline struct pci_dev *pci_get_device(unsigned int vendor,
|
2008-01-31 06:21:33 +07:00
|
|
|
unsigned int device,
|
|
|
|
struct pci_dev *from)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return NULL; }
|
2006-10-22 00:24:12 +07:00
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
|
|
|
|
unsigned int device,
|
|
|
|
unsigned int ss_vendor,
|
|
|
|
unsigned int ss_device,
|
2008-08-26 22:20:34 +07:00
|
|
|
struct pci_dev *from)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return NULL; }
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline struct pci_dev *pci_get_class(unsigned int class,
|
|
|
|
struct pci_dev *from)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return NULL; }
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
#define pci_dev_present(ids) (0)
|
2007-07-16 13:39:39 +07:00
|
|
|
#define no_pci_devices() (1)
|
2005-04-17 05:20:36 +07:00
|
|
|
#define pci_dev_put(dev) do { } while (0)
|
|
|
|
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline void pci_set_master(struct pci_dev *dev) { }
|
|
|
|
static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
|
|
|
|
static inline void pci_disable_device(struct pci_dev *dev) { }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_assign_resource(struct pci_dev *dev, int i)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return -EBUSY; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int __pci_register_driver(struct pci_driver *drv,
|
|
|
|
struct module *owner)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_register_driver(struct pci_driver *drv)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
|
|
|
static inline void pci_unregister_driver(struct pci_driver *drv) { }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_find_capability(struct pci_dev *dev, int cap)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
|
|
|
|
int cap)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2008-01-31 06:21:33 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Power management related routines */
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline int pci_save_state(struct pci_dev *dev) { return 0; }
|
|
|
|
static inline void pci_restore_state(struct pci_dev *dev) { }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2011-02-15 03:27:50 +07:00
|
|
|
static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline pci_power_t pci_choose_state(struct pci_dev *dev,
|
|
|
|
pm_message_t state)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return PCI_D0; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
|
|
|
|
int enable)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2011-01-11 03:46:36 +07:00
|
|
|
|
2016-09-15 15:07:03 +07:00
|
|
|
static inline struct resource *pci_find_resource(struct pci_dev *dev,
|
|
|
|
struct resource *res)
|
|
|
|
{ return NULL; }
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return -EIO; }
|
|
|
|
static inline void pci_release_regions(struct pci_dev *dev) { }
|
2007-04-02 00:13:58 +07:00
|
|
|
|
2016-05-12 05:34:51 +07:00
|
|
|
static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
|
|
|
|
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline void pci_block_cfg_access(struct pci_dev *dev) { }
|
2011-11-04 15:45:59 +07:00
|
|
|
static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
|
|
|
|
{ return 0; }
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
|
2005-09-27 15:21:55 +07:00
|
|
|
|
2007-07-02 02:06:37 +07:00
|
|
|
static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
|
|
|
|
{ return NULL; }
|
|
|
|
static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
|
|
|
|
unsigned int devfn)
|
|
|
|
{ return NULL; }
|
2017-12-07 03:55:05 +07:00
|
|
|
static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
|
|
|
|
unsigned int bus, unsigned int devfn)
|
|
|
|
{ return NULL; }
|
2007-07-02 02:06:37 +07:00
|
|
|
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
|
|
|
|
static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
|
2012-06-11 12:26:55 +07:00
|
|
|
|
2010-02-10 08:43:04 +07:00
|
|
|
#define dev_is_pci(d) (false)
|
|
|
|
#define dev_is_pf(d) (false)
|
2017-09-11 19:29:15 +07:00
|
|
|
static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
|
|
|
|
{ return false; }
|
2018-01-19 16:39:06 +07:00
|
|
|
static inline int pci_irqd_intx_xlate(struct irq_domain *d,
|
|
|
|
struct device_node *node,
|
|
|
|
const u32 *intspec,
|
|
|
|
unsigned int intsize,
|
|
|
|
unsigned long *out_hwirq,
|
|
|
|
unsigned int *out_type)
|
|
|
|
{ return -EINVAL; }
|
2018-10-11 00:09:27 +07:00
|
|
|
|
|
|
|
static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
|
|
|
|
struct pci_dev *dev)
|
|
|
|
{ return NULL; }
|
2019-04-18 01:24:41 +07:00
|
|
|
static inline bool pci_ats_disabled(void) { return true; }
|
2005-07-29 01:37:33 +07:00
|
|
|
#endif /* CONFIG_PCI */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2019-04-18 01:24:40 +07:00
|
|
|
#ifdef CONFIG_PCI_ATS
|
|
|
|
/* Address Translation Service */
|
|
|
|
void pci_ats_init(struct pci_dev *dev);
|
|
|
|
int pci_enable_ats(struct pci_dev *dev, int ps);
|
|
|
|
void pci_disable_ats(struct pci_dev *dev);
|
|
|
|
int pci_ats_queue_depth(struct pci_dev *dev);
|
|
|
|
int pci_ats_page_aligned(struct pci_dev *dev);
|
|
|
|
#else
|
|
|
|
static inline void pci_ats_init(struct pci_dev *d) { }
|
|
|
|
static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
|
|
|
|
static inline void pci_disable_ats(struct pci_dev *d) { }
|
|
|
|
static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
|
|
|
|
static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
|
|
|
|
#endif
|
|
|
|
|
2005-07-29 01:37:33 +07:00
|
|
|
/* Include architecture-dependent settings and functions */
|
|
|
|
|
|
|
|
#include <asm/pci.h>
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-04-12 19:25:59 +07:00
|
|
|
/* These two functions provide almost identical functionality. Depennding
|
|
|
|
* on the architecture, one will be implemented as a wrapper around the
|
|
|
|
* other (in drivers/pci/mmap.c).
|
|
|
|
*
|
|
|
|
* pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
|
|
|
|
* is expected to be an offset within that region.
|
|
|
|
*
|
|
|
|
* pci_mmap_page_range() is the legacy architecture-specific interface,
|
|
|
|
* which accepts a "user visible" resource address converted by
|
|
|
|
* pci_resource_to_user(), as used in the legacy mmap() interface in
|
|
|
|
* /proc/bus/pci/.
|
|
|
|
*/
|
|
|
|
int pci_mmap_resource_range(struct pci_dev *dev, int bar,
|
|
|
|
struct vm_area_struct *vma,
|
|
|
|
enum pci_mmap_state mmap_state, int write_combine);
|
2017-04-12 19:25:58 +07:00
|
|
|
int pci_mmap_page_range(struct pci_dev *pdev, int bar,
|
|
|
|
struct vm_area_struct *vma,
|
2017-04-12 19:25:55 +07:00
|
|
|
enum pci_mmap_state mmap_state, int write_combine);
|
|
|
|
|
2017-04-12 19:25:54 +07:00
|
|
|
#ifndef arch_can_pci_mmap_wc
|
|
|
|
#define arch_can_pci_mmap_wc() 0
|
|
|
|
#endif
|
2017-04-12 19:26:08 +07:00
|
|
|
|
2017-04-12 19:25:56 +07:00
|
|
|
#ifndef arch_can_pci_mmap_io
|
|
|
|
#define arch_can_pci_mmap_io() 0
|
2017-04-12 19:26:08 +07:00
|
|
|
#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
|
|
|
|
#else
|
|
|
|
int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
|
2017-04-12 19:25:56 +07:00
|
|
|
#endif
|
2017-04-12 19:25:54 +07:00
|
|
|
|
2016-02-17 04:56:21 +07:00
|
|
|
#ifndef pci_root_bus_fwnode
|
|
|
|
#define pci_root_bus_fwnode(bus) NULL
|
|
|
|
#endif
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/*
|
|
|
|
* These helpers provide future and backwards compatibility
|
|
|
|
* for accessing popular PCI BAR info
|
|
|
|
*/
|
2008-01-31 06:21:33 +07:00
|
|
|
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
|
|
|
|
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
|
|
|
|
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
|
2005-04-17 05:20:36 +07:00
|
|
|
#define pci_resource_len(dev,bar) \
|
2008-01-31 06:21:33 +07:00
|
|
|
((pci_resource_start((dev), (bar)) == 0 && \
|
|
|
|
pci_resource_end((dev), (bar)) == \
|
|
|
|
pci_resource_start((dev), (bar))) ? 0 : \
|
|
|
|
\
|
|
|
|
(pci_resource_end((dev), (bar)) - \
|
|
|
|
pci_resource_start((dev), (bar)) + 1))
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/*
|
|
|
|
* Similar to the helpers above, these manipulate per-pci_dev
|
2005-04-17 05:20:36 +07:00
|
|
|
* driver-specific data. They are really just a wrapper around
|
|
|
|
* the generic device structure functions of these calls.
|
|
|
|
*/
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline void *pci_get_drvdata(struct pci_dev *pdev)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
return dev_get_drvdata(&pdev->dev);
|
|
|
|
}
|
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
dev_set_drvdata(&pdev->dev, data);
|
|
|
|
}
|
|
|
|
|
2009-06-24 19:22:30 +07:00
|
|
|
static inline const char *pci_name(const struct pci_dev *pdev)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2008-07-03 23:49:39 +07:00
|
|
|
return dev_name(&pdev->dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2005-05-13 14:44:10 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/*
|
|
|
|
* Some archs don't want to expose struct resource to userland as-is
|
2005-05-13 14:44:10 +07:00
|
|
|
* in sysfs and /proc
|
|
|
|
*/
|
2016-06-18 02:43:34 +07:00
|
|
|
#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
|
|
|
|
void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
|
|
|
const struct resource *rsrc,
|
|
|
|
resource_size_t *start, resource_size_t *end);
|
|
|
|
#else
|
2005-05-13 14:44:10 +07:00
|
|
|
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
2008-01-31 06:21:33 +07:00
|
|
|
const struct resource *rsrc, resource_size_t *start,
|
2006-06-13 07:06:02 +07:00
|
|
|
resource_size_t *end)
|
2005-05-13 14:44:10 +07:00
|
|
|
{
|
|
|
|
*start = rsrc->start;
|
|
|
|
*end = rsrc->end;
|
|
|
|
}
|
|
|
|
#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
|
|
|
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/*
|
2017-12-03 02:21:37 +07:00
|
|
|
* The world is not perfect and supplies us with broken PCI devices.
|
|
|
|
* For at least a part of these bugs we need a work-around, so both
|
|
|
|
* generic (drivers/pci/quirks.c) and per-architecture code can define
|
|
|
|
* fixup hooks to be called for particular buggy devices.
|
2005-04-17 05:20:36 +07:00
|
|
|
*/
|
|
|
|
|
|
|
|
struct pci_fixup {
|
2017-12-03 02:21:37 +07:00
|
|
|
u16 vendor; /* Or PCI_ANY_ID */
|
|
|
|
u16 device; /* Or PCI_ANY_ID */
|
|
|
|
u32 class; /* Or PCI_ANY_ID */
|
2012-02-24 14:46:49 +07:00
|
|
|
unsigned int class_shift; /* should be 0, 8, 16 */
|
2018-08-22 11:56:18 +07:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
|
|
|
|
int hook_offset;
|
|
|
|
#else
|
2005-04-17 05:20:36 +07:00
|
|
|
void (*hook)(struct pci_dev *dev);
|
2018-08-22 11:56:18 +07:00
|
|
|
#endif
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
enum pci_fixup_pass {
|
|
|
|
pci_fixup_early, /* Before probing BARs */
|
|
|
|
pci_fixup_header, /* After reading configuration header */
|
|
|
|
pci_fixup_final, /* Final phase of device fixups */
|
|
|
|
pci_fixup_enable, /* pci_enable_device() time */
|
2008-05-16 02:51:31 +07:00
|
|
|
pci_fixup_resume, /* pci_device_resume() */
|
2014-06-04 03:04:09 +07:00
|
|
|
pci_fixup_suspend, /* pci_device_suspend() */
|
2008-05-16 02:51:31 +07:00
|
|
|
pci_fixup_resume_early, /* pci_device_resume_early() */
|
2014-06-04 03:04:09 +07:00
|
|
|
pci_fixup_suspend_late, /* pci_device_suspend_late() */
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
2018-08-22 11:56:18 +07:00
|
|
|
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
|
|
|
|
#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
__ADDRESSABLE(hook) \
|
|
|
|
asm(".section " #sec ", \"a\" \n" \
|
|
|
|
".balign 16 \n" \
|
|
|
|
".short " #vendor ", " #device " \n" \
|
|
|
|
".long " #class ", " #class_shift " \n" \
|
|
|
|
".long " #hook " - . \n" \
|
|
|
|
".previous \n");
|
|
|
|
#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
__DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
|
|
|
|
class_shift, hook)
|
|
|
|
#else
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Anonymous variables would be nice... */
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
2013-11-11 20:40:35 +07:00
|
|
|
static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
|
2012-02-24 14:46:49 +07:00
|
|
|
__attribute__((__section__(#section), aligned((sizeof(void *))))) \
|
|
|
|
= { vendor, device, class, class_shift, hook };
|
2018-08-22 11:56:18 +07:00
|
|
|
#endif
|
2012-02-24 14:46:49 +07:00
|
|
|
|
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
|
2017-12-03 02:21:37 +07:00
|
|
|
resume##hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
|
2017-12-03 02:21:37 +07:00
|
|
|
resume_early##hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
|
2017-12-03 02:21:37 +07:00
|
|
|
suspend##hook, vendor, device, class, class_shift, hook)
|
2014-06-04 03:04:09 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
|
|
|
|
class_shift, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
|
2017-12-03 02:21:37 +07:00
|
|
|
suspend_late##hook, vendor, device, class, class_shift, hook)
|
2012-02-24 14:46:49 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2005-04-17 05:20:36 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2005-04-17 05:20:36 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2005-04-17 05:20:36 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
|
2013-11-11 20:40:35 +07:00
|
|
|
hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2006-12-05 06:14:45 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
|
2017-12-03 02:21:37 +07:00
|
|
|
resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2008-05-16 02:51:31 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
|
2017-12-03 02:21:37 +07:00
|
|
|
resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2008-05-16 02:51:31 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
|
2017-12-03 02:21:37 +07:00
|
|
|
suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2014-06-04 03:04:09 +07:00
|
|
|
#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
|
|
|
|
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
|
2017-12-03 02:21:37 +07:00
|
|
|
suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-01-03 04:57:24 +07:00
|
|
|
#ifdef CONFIG_PCI_QUIRKS
|
2005-04-17 05:20:36 +07:00
|
|
|
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
|
2010-01-03 04:57:24 +07:00
|
|
|
#else
|
|
|
|
static inline void pci_fixup_device(enum pci_fixup_pass pass,
|
2014-01-14 07:15:01 +07:00
|
|
|
struct pci_dev *dev) { }
|
2010-01-03 04:57:24 +07:00
|
|
|
#endif
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2008-01-31 06:21:33 +07:00
|
|
|
void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
|
2007-02-11 22:41:31 +07:00
|
|
|
void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
|
2008-01-31 06:21:33 +07:00
|
|
|
void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
|
2012-01-05 06:50:02 +07:00
|
|
|
int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
|
|
|
|
int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
|
2008-03-12 13:26:34 +07:00
|
|
|
const char *name);
|
2012-01-05 06:50:02 +07:00
|
|
|
void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
|
2007-02-11 22:41:31 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
extern int pci_pci_problems;
|
2006-10-01 13:27:03 +07:00
|
|
|
#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
|
2005-04-17 05:20:36 +07:00
|
|
|
#define PCIPCI_TRITON 2
|
|
|
|
#define PCIPCI_NATOMA 4
|
|
|
|
#define PCIPCI_VIAETBF 8
|
|
|
|
#define PCIPCI_VSFX 16
|
2006-10-01 13:27:03 +07:00
|
|
|
#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
|
|
|
|
#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2007-02-06 07:36:06 +07:00
|
|
|
extern unsigned long pci_cardbus_io_size;
|
|
|
|
extern unsigned long pci_cardbus_mem_size;
|
2012-11-22 03:35:00 +07:00
|
|
|
extern u8 pci_dfl_cache_line_size;
|
2009-10-27 03:20:44 +07:00
|
|
|
extern u8 pci_cache_line_size;
|
2007-02-06 07:36:06 +07:00
|
|
|
|
2009-09-10 04:09:24 +07:00
|
|
|
extern unsigned long pci_hotplug_io_size;
|
|
|
|
extern unsigned long pci_hotplug_mem_size;
|
2016-07-22 10:40:28 +07:00
|
|
|
extern unsigned long pci_hotplug_bus_size;
|
2009-09-10 04:09:24 +07:00
|
|
|
|
2013-11-15 01:28:18 +07:00
|
|
|
/* Architecture-specific versions may override these (weak) */
|
2008-05-06 01:25:47 +07:00
|
|
|
void pcibios_disable_device(struct pci_dev *dev);
|
2011-10-29 04:47:35 +07:00
|
|
|
void pcibios_set_master(struct pci_dev *dev);
|
2008-05-06 01:25:47 +07:00
|
|
|
int pcibios_set_pcie_reset_state(struct pci_dev *dev,
|
|
|
|
enum pcie_reset_state state);
|
2012-12-06 04:33:27 +07:00
|
|
|
int pcibios_add_device(struct pci_dev *dev);
|
2013-06-05 00:18:14 +07:00
|
|
|
void pcibios_release_device(struct pci_dev *dev);
|
2018-12-20 05:46:56 +07:00
|
|
|
#ifdef CONFIG_PCI
|
2014-05-06 10:29:52 +07:00
|
|
|
void pcibios_penalize_isa_irq(int irq, int active);
|
2018-12-20 05:46:56 +07:00
|
|
|
#else
|
|
|
|
static inline void pcibios_penalize_isa_irq(int irq, int active) {}
|
|
|
|
#endif
|
2015-06-10 15:54:58 +07:00
|
|
|
int pcibios_alloc_irq(struct pci_dev *dev);
|
|
|
|
void pcibios_free_irq(struct pci_dev *dev);
|
2018-03-31 05:39:31 +07:00
|
|
|
resource_size_t pcibios_default_alignment(void);
|
2007-05-08 09:03:07 +07:00
|
|
|
|
2013-08-20 21:41:02 +07:00
|
|
|
#ifdef CONFIG_HIBERNATE_CALLBACKS
|
|
|
|
extern struct dev_pm_ops pcibios_pm_ops;
|
|
|
|
#endif
|
|
|
|
|
2016-06-11 02:55:13 +07:00
|
|
|
#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
|
2013-04-13 01:02:59 +07:00
|
|
|
void __init pci_mmcfg_early_init(void);
|
|
|
|
void __init pci_mmcfg_late_init(void);
|
2008-02-15 16:27:20 +07:00
|
|
|
#else
|
2008-02-29 14:56:50 +07:00
|
|
|
static inline void pci_mmcfg_early_init(void) { }
|
2008-02-15 16:27:20 +07:00
|
|
|
static inline void pci_mmcfg_late_init(void) { }
|
|
|
|
#endif
|
|
|
|
|
2012-10-30 13:26:18 +07:00
|
|
|
int pci_ext_cfg_avail(void);
|
2008-11-11 05:30:50 +07:00
|
|
|
|
2008-12-02 05:30:30 +07:00
|
|
|
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
|
2015-08-25 02:13:23 +07:00
|
|
|
void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
|
2008-09-29 06:36:11 +07:00
|
|
|
|
2009-03-20 10:25:15 +07:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
2015-03-25 15:23:48 +07:00
|
|
|
int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
|
|
|
|
int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
|
|
|
|
|
2013-04-13 01:02:59 +07:00
|
|
|
int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
|
|
|
|
void pci_disable_sriov(struct pci_dev *dev);
|
2017-09-27 00:53:23 +07:00
|
|
|
int pci_iov_add_virtfn(struct pci_dev *dev, int id);
|
|
|
|
void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
|
2013-04-13 01:02:59 +07:00
|
|
|
int pci_num_vf(struct pci_dev *dev);
|
2013-04-25 11:42:29 +07:00
|
|
|
int pci_vfs_assigned(struct pci_dev *dev);
|
2013-04-13 01:02:59 +07:00
|
|
|
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
|
|
|
|
int pci_sriov_get_totalvfs(struct pci_dev *dev);
|
2018-04-22 03:23:09 +07:00
|
|
|
int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
|
2015-03-25 15:23:44 +07:00
|
|
|
resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
|
2017-11-09 21:00:35 +07:00
|
|
|
void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
|
2018-03-31 05:39:31 +07:00
|
|
|
|
|
|
|
/* Arch may override these (weak) */
|
|
|
|
int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
|
|
|
|
int pcibios_sriov_disable(struct pci_dev *pdev);
|
|
|
|
resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
|
2009-03-20 10:25:15 +07:00
|
|
|
#else
|
2015-03-25 15:23:48 +07:00
|
|
|
static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
|
|
|
|
{
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
|
|
|
|
{
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
2009-03-20 10:25:15 +07:00
|
|
|
static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return -ENODEV; }
|
2017-09-27 00:53:23 +07:00
|
|
|
static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
|
2016-03-04 06:53:03 +07:00
|
|
|
{
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
|
2017-09-27 00:53:23 +07:00
|
|
|
int id) { }
|
2014-01-14 07:15:01 +07:00
|
|
|
static inline void pci_disable_sriov(struct pci_dev *dev) { }
|
|
|
|
static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
|
2013-04-25 11:42:29 +07:00
|
|
|
static inline int pci_vfs_assigned(struct pci_dev *dev)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2012-11-06 03:20:37 +07:00
|
|
|
static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2012-11-06 03:20:37 +07:00
|
|
|
static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
|
2014-01-14 07:15:01 +07:00
|
|
|
{ return 0; }
|
2018-04-22 03:23:09 +07:00
|
|
|
#define pci_sriov_configure_simple NULL
|
2015-03-25 15:23:44 +07:00
|
|
|
static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
|
|
|
|
{ return 0; }
|
2017-11-09 21:00:35 +07:00
|
|
|
static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
|
2009-03-20 10:25:15 +07:00
|
|
|
#endif
|
|
|
|
|
2009-06-16 09:01:25 +07:00
|
|
|
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_hp_create_module_link(struct pci_slot *pci_slot);
|
|
|
|
void pci_hp_remove_module_link(struct pci_slot *pci_slot);
|
2009-06-16 09:01:25 +07:00
|
|
|
#endif
|
|
|
|
|
2009-11-11 12:29:54 +07:00
|
|
|
/**
|
|
|
|
* pci_pcie_cap - get the saved PCIe capability offset
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
|
|
|
* PCIe capability offset is calculated at PCI device initialization
|
|
|
|
* time and saved in the data structure. This function returns saved
|
|
|
|
* PCIe capability offset. Using this instead of pci_find_capability()
|
|
|
|
* reduces unnecessary search in the PCI configuration space. If you
|
|
|
|
* need to calculate PCIe capability offset from raw device for some
|
|
|
|
* reasons, please use pci_find_capability() instead.
|
|
|
|
*/
|
|
|
|
static inline int pci_pcie_cap(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return dev->pcie_cap;
|
|
|
|
}
|
|
|
|
|
2009-11-11 12:35:22 +07:00
|
|
|
/**
|
|
|
|
* pci_is_pcie - check if the PCI device is PCI Express capable
|
|
|
|
* @dev: PCI device
|
|
|
|
*
|
2013-09-04 03:31:05 +07:00
|
|
|
* Returns: true if the PCI device is PCI Express capable, false otherwise.
|
2009-11-11 12:35:22 +07:00
|
|
|
*/
|
|
|
|
static inline bool pci_is_pcie(struct pci_dev *dev)
|
|
|
|
{
|
2013-09-04 03:31:05 +07:00
|
|
|
return pci_pcie_cap(dev);
|
2009-11-11 12:35:22 +07:00
|
|
|
}
|
|
|
|
|
2013-01-26 07:55:39 +07:00
|
|
|
/**
|
|
|
|
* pcie_caps_reg - get the PCIe Capabilities Register
|
|
|
|
* @dev: PCI device
|
|
|
|
*/
|
|
|
|
static inline u16 pcie_caps_reg(const struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return dev->pcie_flags_reg;
|
|
|
|
}
|
|
|
|
|
2012-07-24 16:20:02 +07:00
|
|
|
/**
|
|
|
|
* pci_pcie_type - get the PCIe device/port type
|
|
|
|
* @dev: PCI device
|
|
|
|
*/
|
|
|
|
static inline int pci_pcie_type(const struct pci_dev *dev)
|
|
|
|
{
|
2013-01-26 07:55:45 +07:00
|
|
|
return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
|
2012-07-24 16:20:02 +07:00
|
|
|
}
|
|
|
|
|
2016-11-03 05:35:51 +07:00
|
|
|
static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
while (1) {
|
|
|
|
if (!pci_is_pcie(dev))
|
|
|
|
break;
|
|
|
|
if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
|
|
|
|
return dev;
|
|
|
|
if (!dev->bus->self)
|
|
|
|
break;
|
|
|
|
dev = dev->bus->self;
|
|
|
|
}
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2009-12-05 03:15:21 +07:00
|
|
|
void pci_request_acs(void);
|
2012-06-11 12:27:07 +07:00
|
|
|
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
|
|
|
|
bool pci_acs_path_enabled(struct pci_dev *start,
|
|
|
|
struct pci_dev *end, u16 acs_flags);
|
2018-01-05 07:44:59 +07:00
|
|
|
int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
|
2010-02-26 21:04:39 +07:00
|
|
|
|
2010-02-26 21:04:40 +07:00
|
|
|
#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
|
2014-09-06 10:19:10 +07:00
|
|
|
#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
|
2010-02-26 21:04:40 +07:00
|
|
|
|
|
|
|
/* Large Resource Data Type Tag Item Names */
|
|
|
|
#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
|
|
|
|
#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
|
|
|
|
#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
|
|
|
|
|
|
|
|
#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
|
|
|
|
#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
|
|
|
|
#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
|
|
|
|
|
|
|
|
/* Small Resource Data Type Tag Item Names */
|
2016-02-15 15:41:59 +07:00
|
|
|
#define PCI_VPD_STIN_END 0x0f /* End */
|
2010-02-26 21:04:40 +07:00
|
|
|
|
2016-02-15 15:41:59 +07:00
|
|
|
#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
|
2010-02-26 21:04:40 +07:00
|
|
|
|
|
|
|
#define PCI_VPD_SRDT_TIN_MASK 0x78
|
|
|
|
#define PCI_VPD_SRDT_LEN_MASK 0x07
|
2016-02-15 15:41:59 +07:00
|
|
|
#define PCI_VPD_LRDT_TIN_MASK 0x7f
|
2010-02-26 21:04:40 +07:00
|
|
|
|
|
|
|
#define PCI_VPD_LRDT_TAG_SIZE 3
|
|
|
|
#define PCI_VPD_SRDT_TAG_SIZE 1
|
2010-02-26 21:04:39 +07:00
|
|
|
|
2010-02-26 21:04:42 +07:00
|
|
|
#define PCI_VPD_INFO_FLD_HDR_SIZE 3
|
|
|
|
|
2010-02-26 21:04:43 +07:00
|
|
|
#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
|
|
|
|
#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
|
|
|
|
#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
|
2011-03-09 23:58:21 +07:00
|
|
|
#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
|
2010-02-26 21:04:43 +07:00
|
|
|
|
2010-02-26 21:04:39 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
|
|
|
|
* @lrdt: Pointer to the beginning of the Large Resource Data Type tag
|
|
|
|
*
|
|
|
|
* Returns the extracted Large Resource Data Type length.
|
|
|
|
*/
|
|
|
|
static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
|
|
|
|
{
|
|
|
|
return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
|
|
|
|
}
|
|
|
|
|
2016-02-15 15:41:59 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
|
|
|
|
* @lrdt: Pointer to the beginning of the Large Resource Data Type tag
|
|
|
|
*
|
|
|
|
* Returns the extracted Large Resource Data Type Tag item.
|
|
|
|
*/
|
|
|
|
static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
|
|
|
|
{
|
2017-12-03 02:21:37 +07:00
|
|
|
return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
|
2016-02-15 15:41:59 +07:00
|
|
|
}
|
|
|
|
|
2010-02-26 21:04:40 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_srdt_size - Extracts the Small Resource Data Type length
|
2017-09-02 04:35:20 +07:00
|
|
|
* @srdt: Pointer to the beginning of the Small Resource Data Type tag
|
2010-02-26 21:04:40 +07:00
|
|
|
*
|
|
|
|
* Returns the extracted Small Resource Data Type length.
|
|
|
|
*/
|
|
|
|
static inline u8 pci_vpd_srdt_size(const u8 *srdt)
|
|
|
|
{
|
|
|
|
return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
|
|
|
|
}
|
|
|
|
|
2016-02-15 15:41:59 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
|
2017-09-02 04:35:20 +07:00
|
|
|
* @srdt: Pointer to the beginning of the Small Resource Data Type tag
|
2016-02-15 15:41:59 +07:00
|
|
|
*
|
|
|
|
* Returns the extracted Small Resource Data Type Tag Item.
|
|
|
|
*/
|
|
|
|
static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
|
|
|
|
{
|
|
|
|
return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
|
|
|
|
}
|
|
|
|
|
2010-02-26 21:04:42 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_info_field_size - Extracts the information field length
|
2019-05-14 21:47:24 +07:00
|
|
|
* @info_field: Pointer to the beginning of an information field header
|
2010-02-26 21:04:42 +07:00
|
|
|
*
|
|
|
|
* Returns the extracted information field length.
|
|
|
|
*/
|
|
|
|
static inline u8 pci_vpd_info_field_size(const u8 *info_field)
|
|
|
|
{
|
|
|
|
return info_field[2];
|
|
|
|
}
|
|
|
|
|
2010-02-26 21:04:41 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_find_tag - Locates the Resource Data Type tag provided
|
|
|
|
* @buf: Pointer to buffered vpd data
|
|
|
|
* @off: The offset into the buffer at which to begin the search
|
|
|
|
* @len: The length of the vpd buffer
|
|
|
|
* @rdt: The Resource Data Type to search for
|
|
|
|
*
|
|
|
|
* Returns the index where the Resource Data Type was found or
|
|
|
|
* -ENOENT otherwise.
|
|
|
|
*/
|
|
|
|
int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
|
|
|
|
|
2010-02-26 21:04:43 +07:00
|
|
|
/**
|
|
|
|
* pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
|
|
|
|
* @buf: Pointer to buffered vpd data
|
|
|
|
* @off: The offset into the buffer at which to begin the search
|
|
|
|
* @len: The length of the buffer area, relative to off, in which to search
|
|
|
|
* @kw: The keyword to search for
|
|
|
|
*
|
|
|
|
* Returns the index where the information field keyword was found or
|
|
|
|
* -ENOENT otherwise.
|
|
|
|
*/
|
|
|
|
int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
|
|
|
|
unsigned int len, const char *kw);
|
|
|
|
|
2011-04-11 08:37:07 +07:00
|
|
|
/* PCI <-> OF binding helpers */
|
|
|
|
#ifdef CONFIG_OF
|
|
|
|
struct device_node;
|
2015-07-28 20:46:12 +07:00
|
|
|
struct irq_domain;
|
2013-04-13 01:02:59 +07:00
|
|
|
void pci_set_of_node(struct pci_dev *dev);
|
|
|
|
void pci_release_of_node(struct pci_dev *dev);
|
|
|
|
void pci_set_bus_of_node(struct pci_bus *bus);
|
|
|
|
void pci_release_bus_of_node(struct pci_bus *bus);
|
2015-07-28 20:46:12 +07:00
|
|
|
struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
|
2018-01-31 03:56:50 +07:00
|
|
|
int pci_parse_request_of_pci_ranges(struct device *dev,
|
|
|
|
struct list_head *resources,
|
|
|
|
struct resource **bus_range);
|
2011-04-11 08:37:07 +07:00
|
|
|
|
|
|
|
/* Arch may override this (weak) */
|
2013-04-17 23:31:34 +07:00
|
|
|
struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
|
2011-04-11 08:37:07 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
#else /* CONFIG_OF */
|
2011-04-11 08:37:07 +07:00
|
|
|
static inline void pci_set_of_node(struct pci_dev *dev) { }
|
|
|
|
static inline void pci_release_of_node(struct pci_dev *dev) { }
|
|
|
|
static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
|
|
|
|
static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
|
2015-07-28 20:46:12 +07:00
|
|
|
static inline struct irq_domain *
|
|
|
|
pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
|
2018-01-31 03:56:50 +07:00
|
|
|
static inline int pci_parse_request_of_pci_ranges(struct device *dev,
|
|
|
|
struct list_head *resources,
|
|
|
|
struct resource **bus_range)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-04-11 08:37:07 +07:00
|
|
|
#endif /* CONFIG_OF */
|
|
|
|
|
2018-03-18 19:58:06 +07:00
|
|
|
static inline struct device_node *
|
|
|
|
pci_device_to_OF_node(const struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pdev ? pdev->dev.of_node : NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
return bus ? bus->dev.of_node : NULL;
|
|
|
|
}
|
|
|
|
|
2015-12-10 23:55:27 +07:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
|
|
|
|
|
|
|
|
void
|
|
|
|
pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
|
|
|
|
#else
|
|
|
|
static inline struct irq_domain *
|
|
|
|
pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
|
|
|
|
#endif
|
|
|
|
|
powerpc/eeh: Introduce EEH device
Original EEH implementation depends on struct pci_dn heavily. However,
EEH shouldn't depend on that actually because EEH needn't share much
information with other PCI components. That's to say, EEH should have
worked independently.
The patch introduces struct eeh_dev so that EEH core components needn't
be working based on struct pci_dn in future. Also, struct pci_dn, struct
eeh_dev instances are created in dynamic fasion and the binding with EEH
device, OF node, PCI device is implemented as well.
The EEH devices are created after PHBs are detected and initialized, but
PCI emunation hasn't started yet. Apart from that, PHB might be created
dynamically through DLPAR component and the EEH devices should be creatd
as well. Another case might be OF node is created dynamically by DR
(Dynamic Reconfiguration), which has been defined by PAPR. For those OF
nodes created by DR, EEH devices should be also created accordingly. The
binding between EEH device and OF node is done while the EEH device is
initially created.
The binding between EEH device and PCI device should be done after PCI
emunation is done. Besides, PCI hotplug also needs the binding so that
the EEH devices could be traced from the newly coming PCI buses or PCI
devices.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-02-28 03:04:04 +07:00
|
|
|
#ifdef CONFIG_EEH
|
|
|
|
static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return pdev->dev.archdata.edev;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-02-25 02:43:45 +07:00
|
|
|
void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
|
2016-03-03 21:38:02 +07:00
|
|
|
bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
|
2014-05-23 06:07:30 +07:00
|
|
|
int pci_for_each_dma_alias(struct pci_dev *pdev,
|
|
|
|
int (*fn)(struct pci_dev *pdev,
|
|
|
|
u16 alias, void *data), void *data);
|
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Helper functions for operation of device flag */
|
2014-09-09 09:21:25 +07:00
|
|
|
static inline void pci_set_dev_assigned(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
|
|
|
|
}
|
|
|
|
static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
|
|
|
|
}
|
|
|
|
static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
|
|
|
|
}
|
2015-05-27 04:11:44 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_ari_enabled - query ARI forwarding status
|
|
|
|
* @bus: the PCI bus
|
|
|
|
*
|
|
|
|
* Returns true if ARI forwarding is enabled.
|
|
|
|
*/
|
|
|
|
static inline bool pci_ari_enabled(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
return bus->self && bus->self->ari_enabled;
|
|
|
|
}
|
2016-03-07 23:40:02 +07:00
|
|
|
|
PCI: Recognize Thunderbolt devices
Detect on probe whether a PCI device is part of a Thunderbolt controller.
Intel uses a Vendor-Specific Extended Capability (VSEC) with ID 0x1234
on such devices. Detect presence of this VSEC and cache it in a newly
added is_thunderbolt bit in struct pci_dev.
Also, add a helper to check whether a given PCI device is situated on a
Thunderbolt daisy chain (i.e., below a PCI device with is_thunderbolt
set).
The necessity arises from the following:
* If an external Thunderbolt GPU is connected to a dual GPU laptop,
that GPU is currently registered with vga_switcheroo even though it
can neither drive the laptop's panel nor be powered off by the
platform. To vga_switcheroo it will appear as if two discrete
GPUs are present. As a result, when the external GPU is runtime
suspended, vga_switcheroo will cut power to the internal discrete GPU
which may not be runtime suspended at all at this moment. The
solution is to not register external GPUs with vga_switcheroo, which
necessitates a way to recognize if they're on a Thunderbolt daisy
chain.
* Dual GPU MacBook Pros introduced 2011+ can no longer switch external
DisplayPort ports between GPUs. (They're no longer just used for DP
but have become combined DP/Thunderbolt ports.) The driver to switch
the ports, drivers/platform/x86/apple-gmux.c, needs to detect presence
of a Thunderbolt controller and, if found, keep external ports
permanently switched to the discrete GPU.
v2: Make kerneldoc for pci_is_thunderbolt_attached() more precise,
drop portion of commit message pertaining to separate series.
(Bjorn Helgaas)
Cc: Andreas Noever <andreas.noever@gmail.com>
Cc: Michael Jamet <michael.jamet@intel.com>
Cc: Tomas Winkler <tomas.winkler@intel.com>
Cc: Amir Levy <amir.jer.levy@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Link: http://patchwork.freedesktop.org/patch/msgid/0ab165a4a35c0b60f29d4c306c653ead14fcd8f9.1489145162.git.lukas@wunner.de
2017-03-11 03:23:45 +07:00
|
|
|
/**
|
|
|
|
* pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
|
|
|
|
* @pdev: PCI device to check
|
|
|
|
*
|
|
|
|
* Walk upwards from @pdev and check for each encountered bridge if it's part
|
|
|
|
* of a Thunderbolt controller. Reaching the host bridge means @pdev is not
|
|
|
|
* Thunderbolt-attached. (But rather soldered to the mainboard usually.)
|
|
|
|
*/
|
|
|
|
static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_dev *parent = pdev;
|
|
|
|
|
|
|
|
if (pdev->is_thunderbolt)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
while ((parent = pci_upstream_bridge(parent)))
|
|
|
|
if (parent->is_thunderbolt)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-05-18 04:44:15 +07:00
|
|
|
#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
|
2018-02-08 19:20:35 +07:00
|
|
|
void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
|
|
|
|
#endif
|
2018-01-05 23:45:47 +07:00
|
|
|
|
2017-12-03 02:21:37 +07:00
|
|
|
/* Provide the legacy pci_dma_* API */
|
2016-03-07 23:40:02 +07:00
|
|
|
#include <linux/pci-dma-compat.h>
|
|
|
|
|
2018-01-19 01:55:24 +07:00
|
|
|
#define pci_printk(level, pdev, fmt, arg...) \
|
|
|
|
dev_printk(level, &(pdev)->dev, fmt, ##arg)
|
|
|
|
|
|
|
|
#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
|
|
|
|
#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
|
|
|
|
|
2019-03-30 21:41:35 +07:00
|
|
|
#define pci_notice_ratelimited(pdev, fmt, arg...) \
|
|
|
|
dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif /* LINUX_PCI_H */
|