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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
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/*
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* ALSA SoC TWL6040 codec driver
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*
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* Author: Misael Lopez Cruz <x0052729@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __TWL6040_H__
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#define __TWL6040_H__
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#define TWL6040_REG_ASICID 0x01
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#define TWL6040_REG_ASICREV 0x02
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#define TWL6040_REG_INTID 0x03
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#define TWL6040_REG_INTMR 0x04
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#define TWL6040_REG_NCPCTL 0x05
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#define TWL6040_REG_LDOCTL 0x06
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#define TWL6040_REG_HPPLLCTL 0x07
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#define TWL6040_REG_LPPLLCTL 0x08
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#define TWL6040_REG_LPPLLDIV 0x09
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#define TWL6040_REG_AMICBCTL 0x0A
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#define TWL6040_REG_DMICBCTL 0x0B
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#define TWL6040_REG_MICLCTL 0x0C
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#define TWL6040_REG_MICRCTL 0x0D
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#define TWL6040_REG_MICGAIN 0x0E
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#define TWL6040_REG_LINEGAIN 0x0F
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#define TWL6040_REG_HSLCTL 0x10
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#define TWL6040_REG_HSRCTL 0x11
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#define TWL6040_REG_HSGAIN 0x12
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#define TWL6040_REG_EARCTL 0x13
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#define TWL6040_REG_HFLCTL 0x14
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#define TWL6040_REG_HFLGAIN 0x15
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#define TWL6040_REG_HFRCTL 0x16
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#define TWL6040_REG_HFRGAIN 0x17
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#define TWL6040_REG_VIBCTLL 0x18
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#define TWL6040_REG_VIBDATL 0x19
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#define TWL6040_REG_VIBCTLR 0x1A
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#define TWL6040_REG_VIBDATR 0x1B
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#define TWL6040_REG_HKCTL1 0x1C
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#define TWL6040_REG_HKCTL2 0x1D
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#define TWL6040_REG_GPOCTL 0x1E
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#define TWL6040_REG_ALB 0x1F
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#define TWL6040_REG_DLB 0x20
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#define TWL6040_REG_TRIM1 0x28
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#define TWL6040_REG_TRIM2 0x29
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#define TWL6040_REG_TRIM3 0x2A
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#define TWL6040_REG_HSOTRIM 0x2B
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#define TWL6040_REG_HFOTRIM 0x2C
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#define TWL6040_REG_ACCCTL 0x2D
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#define TWL6040_REG_STATUS 0x2E
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#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1)
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#define TWL6040_VIOREGNUM 18
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#define TWL6040_VDDREGNUM 21
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/* INTID (0x03) fields */
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#define TWL6040_THINT 0x01
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#define TWL6040_PLUGINT 0x02
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#define TWL6040_UNPLUGINT 0x04
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#define TWL6040_HOOKINT 0x08
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#define TWL6040_HFINT 0x10
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#define TWL6040_VIBINT 0x20
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#define TWL6040_READYINT 0x40
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/* INTMR (0x04) fields */
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#define TWL6040_READYMSK 0x40
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#define TWL6040_ALLINT_MSK 0x7B
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/* NCPCTL (0x05) fields */
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#define TWL6040_NCPENA 0x01
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#define TWL6040_NCPOPEN 0x40
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/* LDOCTL (0x06) fields */
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#define TWL6040_LSLDOENA 0x01
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#define TWL6040_HSLDOENA 0x04
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#define TWL6040_REFENA 0x40
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#define TWL6040_OSCENA 0x80
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/* HPPLLCTL (0x07) fields */
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#define TWL6040_HPLLENA 0x01
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#define TWL6040_HPLLRST 0x02
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#define TWL6040_HPLLBP 0x04
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#define TWL6040_HPLLSQRENA 0x08
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#define TWL6040_HPLLSQRBP 0x10
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#define TWL6040_MCLK_12000KHZ (0 << 5)
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#define TWL6040_MCLK_19200KHZ (1 << 5)
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#define TWL6040_MCLK_26000KHZ (2 << 5)
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#define TWL6040_MCLK_38400KHZ (3 << 5)
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#define TWL6040_MCLK_MSK 0x60
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/* LPPLLCTL (0x08) fields */
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#define TWL6040_LPLLENA 0x01
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#define TWL6040_LPLLRST 0x02
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#define TWL6040_LPLLSEL 0x04
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#define TWL6040_LPLLFIN 0x08
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#define TWL6040_HPLLSEL 0x10
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/* HSLCTL (0x10) fields */
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#define TWL6040_HSDACMODEL 0x02
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#define TWL6040_HSDRVMODEL 0x08
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/* HSRCTL (0x11) fields */
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#define TWL6040_HSDACMODER 0x02
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#define TWL6040_HSDRVMODER 0x08
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/* ACCCTL (0x2D) fields */
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#define TWL6040_RESETSPLIT 0x04
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#define TWL6040_SYSCLK_SEL_LPPLL 1
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#define TWL6040_SYSCLK_SEL_HPPLL 2
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#define TWL6040_HPPLL_ID 1
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#define TWL6040_LPPLL_ID 2
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extern struct snd_soc_dai twl6040_dai;
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extern struct snd_soc_codec_device soc_codec_dev_twl6040;
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#endif /* End of __TWL6040_H__ */
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