2019-06-04 15:11:33 +07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2009-01-04 05:23:10 +07:00
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/*
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2011-04-28 05:24:21 +07:00
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* Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved.
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2009-01-04 05:23:10 +07:00
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* Description:
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* This file is derived from arch/powerpc/kvm/44x_emulate.c,
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* by Hollis Blanchard <hollisb@us.ibm.com>.
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*/
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#include <asm/kvm_ppc.h>
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#include <asm/disassemble.h>
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2012-02-15 20:28:48 +07:00
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#include <asm/dbell.h>
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2015-09-25 22:02:23 +07:00
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#include <asm/reg_booke.h>
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2009-01-04 05:23:10 +07:00
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#include "booke.h"
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2011-12-20 22:34:29 +07:00
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#include "e500.h"
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2009-01-04 05:23:10 +07:00
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2014-04-17 18:25:33 +07:00
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#define XOP_DCBTLS 166
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2012-02-15 20:28:48 +07:00
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#define XOP_MSGSND 206
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#define XOP_MSGCLR 238
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2015-09-25 22:02:23 +07:00
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#define XOP_MFTMR 366
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2009-01-04 05:23:10 +07:00
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#define XOP_TLBIVAX 786
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#define XOP_TLBSX 914
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#define XOP_TLBRE 946
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#define XOP_TLBWE 978
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2011-12-20 22:34:39 +07:00
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#define XOP_TLBILX 18
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2013-07-04 13:57:45 +07:00
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#define XOP_EHPRIV 270
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2009-01-04 05:23:10 +07:00
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2012-02-15 20:28:48 +07:00
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#ifdef CONFIG_KVM_E500MC
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static int dbell2prio(ulong param)
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{
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int msg = param & PPC_DBELL_TYPE_MASK;
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int prio = -1;
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switch (msg) {
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case PPC_DBELL_TYPE(PPC_DBELL):
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prio = BOOKE_IRQPRIO_DBELL;
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break;
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case PPC_DBELL_TYPE(PPC_DBELL_CRIT):
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prio = BOOKE_IRQPRIO_DBELL_CRIT;
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break;
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default:
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break;
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}
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return prio;
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}
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static int kvmppc_e500_emul_msgclr(struct kvm_vcpu *vcpu, int rb)
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{
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2018-05-07 13:20:07 +07:00
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ulong param = vcpu->arch.regs.gpr[rb];
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2012-02-15 20:28:48 +07:00
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int prio = dbell2prio(param);
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if (prio < 0)
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return EMULATE_FAIL;
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clear_bit(prio, &vcpu->arch.pending_exceptions);
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return EMULATE_DONE;
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}
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static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu *vcpu, int rb)
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{
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2018-05-07 13:20:07 +07:00
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ulong param = vcpu->arch.regs.gpr[rb];
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2012-02-15 20:28:48 +07:00
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int prio = dbell2prio(rb);
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int pir = param & PPC_DBELL_PIR_MASK;
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int i;
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struct kvm_vcpu *cvcpu;
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if (prio < 0)
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return EMULATE_FAIL;
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kvm_for_each_vcpu(i, cvcpu, vcpu->kvm) {
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int cpir = cvcpu->arch.shared->pir;
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if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) {
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set_bit(prio, &cvcpu->arch.pending_exceptions);
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kvm_vcpu_kick(cvcpu);
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}
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}
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return EMULATE_DONE;
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}
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#endif
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2013-07-04 13:57:45 +07:00
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static int kvmppc_e500_emul_ehpriv(struct kvm_run *run, struct kvm_vcpu *vcpu,
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unsigned int inst, int *advance)
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{
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int emulated = EMULATE_DONE;
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switch (get_oc(inst)) {
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case EHPRIV_OC_DEBUG:
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run->exit_reason = KVM_EXIT_DEBUG;
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2018-05-07 13:20:08 +07:00
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run->debug.arch.address = vcpu->arch.regs.nip;
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2013-07-04 13:57:45 +07:00
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run->debug.arch.status = 0;
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kvmppc_account_exit(vcpu, DEBUG_EXITS);
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emulated = EMULATE_EXIT_USER;
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*advance = 0;
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break;
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default:
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emulated = EMULATE_FAIL;
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}
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return emulated;
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}
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2014-04-17 18:25:33 +07:00
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static int kvmppc_e500_emul_dcbtls(struct kvm_vcpu *vcpu)
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{
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struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
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/* Always fail to lock the cache */
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vcpu_e500->l1csr0 |= L1CSR0_CUL;
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return EMULATE_DONE;
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}
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2015-09-25 22:02:23 +07:00
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static int kvmppc_e500_emul_mftmr(struct kvm_vcpu *vcpu, unsigned int inst,
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int rt)
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{
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/* Expose one thread per vcpu */
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if (get_tmrn(inst) == TMRN_TMCFG0) {
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kvmppc_set_gpr(vcpu, rt,
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1 | (1 << TMRN_TMCFG0_NATHRD_SHIFT));
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return EMULATE_DONE;
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}
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return EMULATE_FAIL;
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}
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2013-10-07 23:47:53 +07:00
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int kvmppc_core_emulate_op_e500(struct kvm_run *run, struct kvm_vcpu *vcpu,
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unsigned int inst, int *advance)
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2009-01-04 05:23:10 +07:00
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{
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int emulated = EMULATE_DONE;
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2012-05-04 19:01:33 +07:00
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int ra = get_ra(inst);
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int rb = get_rb(inst);
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int rt = get_rt(inst);
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2012-10-11 13:13:22 +07:00
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gva_t ea;
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2009-01-04 05:23:10 +07:00
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switch (get_op(inst)) {
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case 31:
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switch (get_xop(inst)) {
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2014-04-17 18:25:33 +07:00
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case XOP_DCBTLS:
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emulated = kvmppc_e500_emul_dcbtls(vcpu);
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break;
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2012-02-15 20:28:48 +07:00
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#ifdef CONFIG_KVM_E500MC
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case XOP_MSGSND:
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2012-05-04 19:01:33 +07:00
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emulated = kvmppc_e500_emul_msgsnd(vcpu, rb);
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2012-02-15 20:28:48 +07:00
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break;
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case XOP_MSGCLR:
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2012-05-04 19:01:33 +07:00
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emulated = kvmppc_e500_emul_msgclr(vcpu, rb);
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2012-02-15 20:28:48 +07:00
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break;
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#endif
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2009-01-04 05:23:10 +07:00
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case XOP_TLBRE:
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emulated = kvmppc_e500_emul_tlbre(vcpu);
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break;
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case XOP_TLBWE:
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emulated = kvmppc_e500_emul_tlbwe(vcpu);
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break;
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case XOP_TLBSX:
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2012-10-11 13:13:22 +07:00
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ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
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emulated = kvmppc_e500_emul_tlbsx(vcpu, ea);
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2009-01-04 05:23:10 +07:00
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break;
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2012-10-11 13:13:22 +07:00
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case XOP_TLBILX: {
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int type = rt & 0x3;
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ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
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emulated = kvmppc_e500_emul_tlbilx(vcpu, type, ea);
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2011-12-20 22:34:39 +07:00
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break;
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2012-10-11 13:13:22 +07:00
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}
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2011-12-20 22:34:39 +07:00
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2009-01-04 05:23:10 +07:00
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case XOP_TLBIVAX:
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2012-10-11 13:13:22 +07:00
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ea = kvmppc_get_ea_indexed(vcpu, ra, rb);
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emulated = kvmppc_e500_emul_tlbivax(vcpu, ea);
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2009-01-04 05:23:10 +07:00
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break;
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2015-09-25 22:02:23 +07:00
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case XOP_MFTMR:
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emulated = kvmppc_e500_emul_mftmr(vcpu, inst, rt);
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break;
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2013-07-04 13:57:45 +07:00
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case XOP_EHPRIV:
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emulated = kvmppc_e500_emul_ehpriv(run, vcpu, inst,
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advance);
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break;
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2009-01-04 05:23:10 +07:00
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default:
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emulated = EMULATE_FAIL;
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}
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break;
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default:
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emulated = EMULATE_FAIL;
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}
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if (emulated == EMULATE_FAIL)
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emulated = kvmppc_booke_emulate_op(run, vcpu, inst, advance);
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return emulated;
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}
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2013-10-07 23:47:53 +07:00
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int kvmppc_core_emulate_mtspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
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2009-01-04 05:23:10 +07:00
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{
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struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
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int emulated = EMULATE_DONE;
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switch (sprn) {
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2011-12-20 22:34:47 +07:00
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#ifndef CONFIG_KVM_BOOKE_HV
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2009-01-04 05:23:10 +07:00
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case SPRN_PID:
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2011-04-28 05:24:21 +07:00
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kvmppc_set_pid(vcpu, spr_val);
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2009-01-04 05:23:10 +07:00
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break;
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case SPRN_PID1:
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2011-06-15 06:35:14 +07:00
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if (spr_val != 0)
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return EMULATE_FAIL;
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2012-05-04 19:55:12 +07:00
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vcpu_e500->pid[1] = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_PID2:
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2011-06-15 06:35:14 +07:00
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if (spr_val != 0)
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return EMULATE_FAIL;
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2012-05-04 19:55:12 +07:00
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vcpu_e500->pid[2] = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS0:
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2012-05-04 19:55:12 +07:00
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vcpu->arch.shared->mas0 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS1:
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2012-05-04 19:55:12 +07:00
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vcpu->arch.shared->mas1 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS2:
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2012-05-04 19:55:12 +07:00
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vcpu->arch.shared->mas2 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS3:
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KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 07:23:30 +07:00
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vcpu->arch.shared->mas7_3 &= ~(u64)0xffffffff;
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vcpu->arch.shared->mas7_3 |= spr_val;
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2011-08-19 03:25:21 +07:00
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS4:
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2012-05-04 19:55:12 +07:00
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vcpu->arch.shared->mas4 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS6:
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2012-05-04 19:55:12 +07:00
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vcpu->arch.shared->mas6 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_MAS7:
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KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 07:23:30 +07:00
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vcpu->arch.shared->mas7_3 &= (u64)0xffffffff;
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vcpu->arch.shared->mas7_3 |= (u64)spr_val << 32;
|
2011-08-19 03:25:21 +07:00
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break;
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2011-12-20 22:34:47 +07:00
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#endif
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2010-01-22 17:50:29 +07:00
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case SPRN_L1CSR0:
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vcpu_e500->l1csr0 = spr_val;
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vcpu_e500->l1csr0 &= ~(L1CSR0_DCFI | L1CSR0_CLFC);
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_L1CSR1:
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2012-05-04 19:55:12 +07:00
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vcpu_e500->l1csr1 = spr_val;
|
2014-04-17 17:53:13 +07:00
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vcpu_e500->l1csr1 &= ~(L1CSR1_ICFI | L1CSR1_ICLFR);
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2012-05-04 19:55:12 +07:00
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_HID0:
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2012-05-04 19:55:12 +07:00
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vcpu_e500->hid0 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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case SPRN_HID1:
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2012-05-04 19:55:12 +07:00
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vcpu_e500->hid1 = spr_val;
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break;
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2009-01-04 05:23:10 +07:00
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2009-02-17 15:52:08 +07:00
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case SPRN_MMUCSR0:
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emulated = kvmppc_e500_emul_mt_mmucsr0(vcpu_e500,
|
2010-01-08 08:58:01 +07:00
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spr_val);
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2009-02-17 15:52:08 +07:00
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break;
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2014-07-04 15:17:28 +07:00
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case SPRN_PWRMGTCR0:
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/*
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* Guest relies on host power management configurations
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* Treat the request as a general store
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*/
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|
|
vcpu->arch.pwrmgtcr0 = spr_val;
|
|
|
|
break;
|
|
|
|
|
2018-12-12 21:03:03 +07:00
|
|
|
case SPRN_BUCSR:
|
|
|
|
/*
|
|
|
|
* If we are here, it means that we have already flushed the
|
|
|
|
* branch predictor, so just return to guest.
|
|
|
|
*/
|
|
|
|
break;
|
|
|
|
|
2009-01-04 05:23:13 +07:00
|
|
|
/* extra exceptions */
|
2014-08-20 20:36:23 +07:00
|
|
|
#ifdef CONFIG_SPE_POSSIBLE
|
2009-01-04 05:23:13 +07:00
|
|
|
case SPRN_IVOR32:
|
2010-01-08 08:58:01 +07:00
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL] = spr_val;
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
|
|
|
case SPRN_IVOR33:
|
2010-01-08 08:58:01 +07:00
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_DATA] = spr_val;
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
|
|
|
case SPRN_IVOR34:
|
2010-01-08 08:58:01 +07:00
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND] = spr_val;
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
2014-08-20 20:36:23 +07:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
case SPRN_IVOR32:
|
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_UNAVAIL] = spr_val;
|
|
|
|
break;
|
|
|
|
case SPRN_IVOR33:
|
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_ASSIST] = spr_val;
|
|
|
|
break;
|
|
|
|
#endif
|
2009-01-04 05:23:13 +07:00
|
|
|
case SPRN_IVOR35:
|
2010-01-08 08:58:01 +07:00
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR] = spr_val;
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
2011-12-20 22:34:47 +07:00
|
|
|
#ifdef CONFIG_KVM_BOOKE_HV
|
|
|
|
case SPRN_IVOR36:
|
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL] = spr_val;
|
|
|
|
break;
|
|
|
|
case SPRN_IVOR37:
|
|
|
|
vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL_CRIT] = spr_val;
|
|
|
|
break;
|
|
|
|
#endif
|
2009-01-04 05:23:10 +07:00
|
|
|
default:
|
2012-05-04 19:55:12 +07:00
|
|
|
emulated = kvmppc_booke_emulate_mtspr(vcpu, sprn, spr_val);
|
2009-01-04 05:23:10 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return emulated;
|
|
|
|
}
|
|
|
|
|
2013-10-07 23:47:53 +07:00
|
|
|
int kvmppc_core_emulate_mfspr_e500(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
|
2009-01-04 05:23:10 +07:00
|
|
|
{
|
|
|
|
struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
|
|
|
|
int emulated = EMULATE_DONE;
|
|
|
|
|
|
|
|
switch (sprn) {
|
2011-12-20 22:34:47 +07:00
|
|
|
#ifndef CONFIG_KVM_BOOKE_HV
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_PID:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->pid[0];
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_PID1:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->pid[1];
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_PID2:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->pid[2];
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS0:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.shared->mas0;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS1:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.shared->mas1;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS2:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.shared->mas2;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS3:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = (u32)vcpu->arch.shared->mas7_3;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 07:23:30 +07:00
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS4:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.shared->mas4;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS6:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.shared->mas6;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_MAS7:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.shared->mas7_3 >> 32;
|
KVM: PPC: Paravirtualize SPRG4-7, ESR, PIR, MASn
This allows additional registers to be accessed by the guest
in PR-mode KVM without trapping.
SPRG4-7 are readable from userspace. On booke, KVM will sync
these registers when it enters the guest, so that accesses from
guest userspace will work. The guest kernel, OTOH, must consistently
use either the real registers or the shared area between exits. This
also applies to the already-paravirted SPRG3.
On non-booke, it's not clear to what extent SPRG4-7 are supported
(they're not architected for book3s, but exist on at least some classic
chips). They are copied in the get/set regs ioctls, but I do not see any
non-booke emulation. I also do not see any syncing with real registers
(in PR-mode) including the user-readable SPRG3. This patch should not
make that situation any worse.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-09 07:23:30 +07:00
|
|
|
break;
|
2011-12-20 22:34:47 +07:00
|
|
|
#endif
|
2012-05-21 06:21:23 +07:00
|
|
|
case SPRN_DECAR:
|
|
|
|
*spr_val = vcpu->arch.decar;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_TLB0CFG:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.tlbcfg[0];
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_TLB1CFG:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.tlbcfg[1];
|
|
|
|
break;
|
2013-04-11 07:03:10 +07:00
|
|
|
case SPRN_TLB0PS:
|
|
|
|
if (!has_feature(vcpu, VCPU_FTR_MMU_V2))
|
|
|
|
return EMULATE_FAIL;
|
|
|
|
*spr_val = vcpu->arch.tlbps[0];
|
|
|
|
break;
|
|
|
|
case SPRN_TLB1PS:
|
|
|
|
if (!has_feature(vcpu, VCPU_FTR_MMU_V2))
|
|
|
|
return EMULATE_FAIL;
|
|
|
|
*spr_val = vcpu->arch.tlbps[1];
|
|
|
|
break;
|
2010-01-22 17:50:29 +07:00
|
|
|
case SPRN_L1CSR0:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->l1csr0;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_L1CSR1:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->l1csr1;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_HID0:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->hid0;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
case SPRN_HID1:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->hid1;
|
|
|
|
break;
|
2011-03-30 04:49:10 +07:00
|
|
|
case SPRN_SVR:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu_e500->svr;
|
|
|
|
break;
|
2009-01-04 05:23:10 +07:00
|
|
|
|
2009-02-17 15:52:08 +07:00
|
|
|
case SPRN_MMUCSR0:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = 0;
|
|
|
|
break;
|
2009-02-17 15:52:08 +07:00
|
|
|
|
2009-06-05 13:54:31 +07:00
|
|
|
case SPRN_MMUCFG:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.mmucfg;
|
|
|
|
break;
|
2013-04-11 07:03:11 +07:00
|
|
|
case SPRN_EPTCFG:
|
|
|
|
if (!has_feature(vcpu, VCPU_FTR_MMU_V2))
|
|
|
|
return EMULATE_FAIL;
|
|
|
|
/*
|
|
|
|
* Legacy Linux guests access EPTCFG register even if the E.PT
|
|
|
|
* category is disabled in the VM. Give them a chance to live.
|
|
|
|
*/
|
|
|
|
*spr_val = vcpu->arch.eptcfg;
|
|
|
|
break;
|
2009-06-05 13:54:31 +07:00
|
|
|
|
2014-07-04 15:17:28 +07:00
|
|
|
case SPRN_PWRMGTCR0:
|
|
|
|
*spr_val = vcpu->arch.pwrmgtcr0;
|
|
|
|
break;
|
|
|
|
|
2009-01-04 05:23:13 +07:00
|
|
|
/* extra exceptions */
|
2014-08-20 20:36:23 +07:00
|
|
|
#ifdef CONFIG_SPE_POSSIBLE
|
2009-01-04 05:23:13 +07:00
|
|
|
case SPRN_IVOR32:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL];
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
|
|
|
case SPRN_IVOR33:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_DATA];
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
|
|
|
case SPRN_IVOR34:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND];
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
2014-08-20 20:36:23 +07:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
case SPRN_IVOR32:
|
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_UNAVAIL];
|
|
|
|
break;
|
|
|
|
case SPRN_IVOR33:
|
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALTIVEC_ASSIST];
|
|
|
|
break;
|
|
|
|
#endif
|
2009-01-04 05:23:13 +07:00
|
|
|
case SPRN_IVOR35:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR];
|
2009-01-04 05:23:13 +07:00
|
|
|
break;
|
2011-12-20 22:34:47 +07:00
|
|
|
#ifdef CONFIG_KVM_BOOKE_HV
|
|
|
|
case SPRN_IVOR36:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL];
|
2011-12-20 22:34:47 +07:00
|
|
|
break;
|
|
|
|
case SPRN_IVOR37:
|
2012-05-04 19:55:12 +07:00
|
|
|
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL_CRIT];
|
2011-12-20 22:34:47 +07:00
|
|
|
break;
|
|
|
|
#endif
|
2009-01-04 05:23:10 +07:00
|
|
|
default:
|
2012-05-04 19:55:12 +07:00
|
|
|
emulated = kvmppc_booke_emulate_mfspr(vcpu, sprn, spr_val);
|
2009-01-04 05:23:10 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return emulated;
|
|
|
|
}
|
|
|
|
|