mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 04:35:20 +07:00
411 lines
9.4 KiB
C
411 lines
9.4 KiB
C
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#include <asm/div64.h>
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/* FAPLL Control Register PLL_CTRL */
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#define FAPLL_MAIN_LOCK BIT(7)
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#define FAPLL_MAIN_PLLEN BIT(3)
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#define FAPLL_MAIN_BP BIT(2)
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#define FAPLL_MAIN_LOC_CTL BIT(0)
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/* FAPLL powerdown register PWD */
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#define FAPLL_PWD_OFFSET 4
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#define MAX_FAPLL_OUTPUTS 7
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#define FAPLL_MAX_RETRIES 1000
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#define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
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#define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
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/* The bypass bit is inverted on the ddr_pll.. */
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#define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
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/*
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* The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
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* and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
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*/
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#define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
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#define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
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/* Synthesizer divider register */
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#define SYNTH_LDMDIV1 BIT(8)
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/* Synthesizer frequency register */
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#define SYNTH_LDFREQ BIT(31)
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struct fapll_data {
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struct clk_hw hw;
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void __iomem *base;
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const char *name;
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struct clk *clk_ref;
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struct clk *clk_bypass;
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struct clk_onecell_data outputs;
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bool bypass_bit_inverted;
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};
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struct fapll_synth {
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struct clk_hw hw;
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struct fapll_data *fd;
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int index;
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void __iomem *freq;
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void __iomem *div;
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const char *name;
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struct clk *clk_pll;
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};
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static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
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{
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u32 v = readl_relaxed(fd->base);
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if (fd->bypass_bit_inverted)
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return !(v & FAPLL_MAIN_BP);
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else
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return !!(v & FAPLL_MAIN_BP);
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}
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static int ti_fapll_enable(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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v |= (1 << FAPLL_MAIN_PLLEN);
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writel_relaxed(v, fd->base);
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return 0;
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}
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static void ti_fapll_disable(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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v &= ~(1 << FAPLL_MAIN_PLLEN);
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writel_relaxed(v, fd->base);
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}
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static int ti_fapll_is_enabled(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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return v & (1 << FAPLL_MAIN_PLLEN);
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}
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static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 fapll_n, fapll_p, v;
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long long rate;
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if (ti_fapll_clock_is_bypass(fd))
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return parent_rate;
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rate = parent_rate;
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/* PLL pre-divider is P and multiplier is N */
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v = readl_relaxed(fd->base);
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fapll_p = (v >> 8) & 0xff;
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if (fapll_p)
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do_div(rate, fapll_p);
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fapll_n = v >> 16;
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if (fapll_n)
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rate *= fapll_n;
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return rate;
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}
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static u8 ti_fapll_get_parent(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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if (ti_fapll_clock_is_bypass(fd))
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return 1;
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return 0;
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}
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static struct clk_ops ti_fapll_ops = {
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.enable = ti_fapll_enable,
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.disable = ti_fapll_disable,
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.is_enabled = ti_fapll_is_enabled,
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.recalc_rate = ti_fapll_recalc_rate,
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.get_parent = ti_fapll_get_parent,
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};
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static int ti_fapll_synth_enable(struct clk_hw *hw)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
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v &= ~(1 << synth->index);
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writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
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return 0;
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}
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static void ti_fapll_synth_disable(struct clk_hw *hw)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
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v |= 1 << synth->index;
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writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
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}
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static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
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return !(v & (1 << synth->index));
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}
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/*
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* See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
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*/
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static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 synth_div_m;
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long long rate;
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/* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
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if (!synth->div)
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return 32768;
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/*
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* PLL in bypass sets the synths in bypass mode too. The PLL rate
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* can be also be set to 27MHz, so we can't use parent_rate to
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* check for bypass mode.
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*/
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if (ti_fapll_clock_is_bypass(synth->fd))
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return parent_rate;
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rate = parent_rate;
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/*
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* Synth frequency integer and fractional divider.
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* Note that the phase output K is 8, so the result needs
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* to be multiplied by 8.
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*/
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if (synth->freq) {
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u32 v, synth_int_div, synth_frac_div, synth_div_freq;
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v = readl_relaxed(synth->freq);
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synth_int_div = (v >> 24) & 0xf;
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synth_frac_div = v & 0xffffff;
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synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
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rate *= 10000000;
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do_div(rate, synth_div_freq);
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rate *= 8;
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}
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/* Synth ost-divider M */
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synth_div_m = readl_relaxed(synth->div) & 0xff;
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do_div(rate, synth_div_m);
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return rate;
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}
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static struct clk_ops ti_fapll_synt_ops = {
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.enable = ti_fapll_synth_enable,
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.disable = ti_fapll_synth_disable,
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.is_enabled = ti_fapll_synth_is_enabled,
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.recalc_rate = ti_fapll_synth_recalc_rate,
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};
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static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
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void __iomem *freq,
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void __iomem *div,
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int index,
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const char *name,
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const char *parent,
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struct clk *pll_clk)
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{
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struct clk_init_data *init;
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struct fapll_synth *synth;
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init = kzalloc(sizeof(*init), GFP_KERNEL);
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if (!init)
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return ERR_PTR(-ENOMEM);
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init->ops = &ti_fapll_synt_ops;
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init->name = name;
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init->parent_names = &parent;
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init->num_parents = 1;
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synth = kzalloc(sizeof(*synth), GFP_KERNEL);
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if (!synth)
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goto free;
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synth->fd = fd;
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synth->index = index;
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synth->freq = freq;
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synth->div = div;
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synth->name = name;
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synth->hw.init = init;
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synth->clk_pll = pll_clk;
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return clk_register(NULL, &synth->hw);
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free:
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kfree(synth);
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kfree(init);
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return ERR_PTR(-ENOMEM);
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}
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static void __init ti_fapll_setup(struct device_node *node)
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{
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struct fapll_data *fd;
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struct clk_init_data *init = NULL;
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const char *parent_name[2];
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struct clk *pll_clk;
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int i;
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd)
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return;
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fd->outputs.clks = kzalloc(sizeof(struct clk *) *
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MAX_FAPLL_OUTPUTS + 1,
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GFP_KERNEL);
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if (!fd->outputs.clks)
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goto free;
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init = kzalloc(sizeof(*init), GFP_KERNEL);
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if (!init)
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goto free;
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init->ops = &ti_fapll_ops;
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init->name = node->name;
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init->num_parents = of_clk_get_parent_count(node);
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if (init->num_parents != 2) {
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pr_err("%s must have two parents\n", node->name);
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goto free;
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}
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parent_name[0] = of_clk_get_parent_name(node, 0);
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parent_name[1] = of_clk_get_parent_name(node, 1);
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init->parent_names = parent_name;
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fd->clk_ref = of_clk_get(node, 0);
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if (IS_ERR(fd->clk_ref)) {
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pr_err("%s could not get clk_ref\n", node->name);
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goto free;
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}
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fd->clk_bypass = of_clk_get(node, 1);
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if (IS_ERR(fd->clk_bypass)) {
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pr_err("%s could not get clk_bypass\n", node->name);
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goto free;
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}
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fd->base = of_iomap(node, 0);
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if (!fd->base) {
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pr_err("%s could not get IO base\n", node->name);
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goto free;
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}
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if (fapll_is_ddr_pll(fd->base))
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fd->bypass_bit_inverted = true;
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fd->name = node->name;
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fd->hw.init = init;
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/* Register the parent PLL */
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pll_clk = clk_register(NULL, &fd->hw);
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if (IS_ERR(pll_clk))
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goto unmap;
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fd->outputs.clks[0] = pll_clk;
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fd->outputs.clk_num++;
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/*
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* Set up the child synthesizers starting at index 1 as the
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* PLL output is at index 0. We need to check the clock-indices
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* for numbering in case there are holes in the synth mapping,
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* and then probe the synth register to see if it has a FREQ
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* register available.
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*/
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for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
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const char *output_name;
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void __iomem *freq, *div;
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struct clk *synth_clk;
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int output_instance;
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u32 v;
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if (of_property_read_string_index(node, "clock-output-names",
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i, &output_name))
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continue;
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if (of_property_read_u32_index(node, "clock-indices", i,
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&output_instance))
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output_instance = i;
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freq = fd->base + (output_instance * 8);
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div = freq + 4;
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/* Check for hardwired audio_pll_clk1 */
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if (is_audio_pll_clk1(freq)) {
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freq = 0;
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div = 0;
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} else {
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/* Does the synthesizer have a FREQ register? */
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v = readl_relaxed(freq);
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if (!v)
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freq = 0;
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}
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synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
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output_name, node->name,
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pll_clk);
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if (IS_ERR(synth_clk))
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continue;
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fd->outputs.clks[output_instance] = synth_clk;
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fd->outputs.clk_num++;
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clk_register_clkdev(synth_clk, output_name, NULL);
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}
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/* Register the child synthesizers as the FAPLL outputs */
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of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
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/* Add clock alias for the outputs */
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kfree(init);
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return;
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unmap:
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iounmap(fd->base);
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free:
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if (fd->clk_bypass)
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clk_put(fd->clk_bypass);
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if (fd->clk_ref)
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clk_put(fd->clk_ref);
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kfree(fd->outputs.clks);
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kfree(fd);
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kfree(init);
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}
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CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);
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