2019-03-12 03:55:59 +07:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019, Intel Corporation.
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*
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* Heterogeneous Memory Attributes Table (HMAT) representation
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*
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* This program parses and reports the platform's HMAT tables, and registers
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* the applicable attributes with the node's interfaces.
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*/
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ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
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#define pr_fmt(fmt) "acpi/hmat: " fmt
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#define dev_fmt(fmt) "acpi/hmat: " fmt
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2019-03-12 03:55:59 +07:00
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/list.h>
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ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
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#include <linux/mm.h>
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#include <linux/platform_device.h>
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2019-03-12 03:56:03 +07:00
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#include <linux/list_sort.h>
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ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
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#include <linux/memregion.h>
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2019-08-05 21:27:05 +07:00
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#include <linux/memory.h>
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#include <linux/mutex.h>
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2019-03-12 03:55:59 +07:00
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#include <linux/node.h>
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#include <linux/sysfs.h>
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2019-08-05 21:27:05 +07:00
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static u8 hmat_revision;
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2019-03-12 03:55:59 +07:00
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2019-08-05 21:27:05 +07:00
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static LIST_HEAD(targets);
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static LIST_HEAD(initiators);
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static LIST_HEAD(localities);
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static DEFINE_MUTEX(target_lock);
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2019-03-12 03:56:03 +07:00
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/*
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* The defined enum order is used to prioritize attributes to break ties when
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* selecting the best performing node.
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*/
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enum locality_types {
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WRITE_LATENCY,
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READ_LATENCY,
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WRITE_BANDWIDTH,
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READ_BANDWIDTH,
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};
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static struct memory_locality *localities_types[4];
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2019-08-05 21:27:04 +07:00
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struct target_cache {
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struct list_head node;
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struct node_cache_attrs cache_attrs;
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};
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2019-03-12 03:56:03 +07:00
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struct memory_target {
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struct list_head node;
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unsigned int memory_pxm;
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unsigned int processor_pxm;
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ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
struct resource memregions;
|
2019-03-12 03:56:03 +07:00
|
|
|
struct node_hmem_attrs hmem_attrs;
|
2019-08-05 21:27:04 +07:00
|
|
|
struct list_head caches;
|
2019-08-05 21:27:05 +07:00
|
|
|
struct node_cache_attrs cache_attrs;
|
|
|
|
bool registered;
|
2019-03-12 03:56:03 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
struct memory_initiator {
|
|
|
|
struct list_head node;
|
|
|
|
unsigned int processor_pxm;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct memory_locality {
|
|
|
|
struct list_head node;
|
|
|
|
struct acpi_hmat_locality *hmat_loc;
|
|
|
|
};
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static struct memory_initiator *find_mem_initiator(unsigned int cpu_pxm)
|
2019-03-12 03:56:03 +07:00
|
|
|
{
|
|
|
|
struct memory_initiator *initiator;
|
|
|
|
|
|
|
|
list_for_each_entry(initiator, &initiators, node)
|
|
|
|
if (initiator->processor_pxm == cpu_pxm)
|
|
|
|
return initiator;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static struct memory_target *find_mem_target(unsigned int mem_pxm)
|
2019-03-12 03:56:03 +07:00
|
|
|
{
|
|
|
|
struct memory_target *target;
|
|
|
|
|
|
|
|
list_for_each_entry(target, &targets, node)
|
|
|
|
if (target->memory_pxm == mem_pxm)
|
|
|
|
return target;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init void alloc_memory_initiator(unsigned int cpu_pxm)
|
|
|
|
{
|
|
|
|
struct memory_initiator *initiator;
|
|
|
|
|
|
|
|
if (pxm_to_node(cpu_pxm) == NUMA_NO_NODE)
|
|
|
|
return;
|
|
|
|
|
|
|
|
initiator = find_mem_initiator(cpu_pxm);
|
|
|
|
if (initiator)
|
|
|
|
return;
|
|
|
|
|
|
|
|
initiator = kzalloc(sizeof(*initiator), GFP_KERNEL);
|
|
|
|
if (!initiator)
|
|
|
|
return;
|
|
|
|
|
|
|
|
initiator->processor_pxm = cpu_pxm;
|
|
|
|
list_add_tail(&initiator->node, &initiators);
|
|
|
|
}
|
|
|
|
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
static __init void alloc_memory_target(unsigned int mem_pxm,
|
|
|
|
resource_size_t start, resource_size_t len)
|
2019-03-12 03:56:03 +07:00
|
|
|
{
|
|
|
|
struct memory_target *target;
|
|
|
|
|
|
|
|
target = find_mem_target(mem_pxm);
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
if (!target) {
|
|
|
|
target = kzalloc(sizeof(*target), GFP_KERNEL);
|
|
|
|
if (!target)
|
|
|
|
return;
|
|
|
|
target->memory_pxm = mem_pxm;
|
|
|
|
target->processor_pxm = PXM_INVAL;
|
|
|
|
target->memregions = (struct resource) {
|
|
|
|
.name = "ACPI mem",
|
|
|
|
.start = 0,
|
|
|
|
.end = -1,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
};
|
|
|
|
list_add_tail(&target->node, &targets);
|
|
|
|
INIT_LIST_HEAD(&target->caches);
|
|
|
|
}
|
2019-03-12 03:56:03 +07:00
|
|
|
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
/*
|
|
|
|
* There are potentially multiple ranges per PXM, so record each
|
|
|
|
* in the per-target memregions resource tree.
|
|
|
|
*/
|
|
|
|
if (!__request_region(&target->memregions, start, len, "memory target",
|
|
|
|
IORESOURCE_MEM))
|
|
|
|
pr_warn("failed to reserve %#llx - %#llx in pxm: %d\n",
|
|
|
|
start, start + len, mem_pxm);
|
2019-03-12 03:56:03 +07:00
|
|
|
}
|
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
static __init const char *hmat_data_type(u8 type)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case ACPI_HMAT_ACCESS_LATENCY:
|
|
|
|
return "Access Latency";
|
|
|
|
case ACPI_HMAT_READ_LATENCY:
|
|
|
|
return "Read Latency";
|
|
|
|
case ACPI_HMAT_WRITE_LATENCY:
|
|
|
|
return "Write Latency";
|
|
|
|
case ACPI_HMAT_ACCESS_BANDWIDTH:
|
|
|
|
return "Access Bandwidth";
|
|
|
|
case ACPI_HMAT_READ_BANDWIDTH:
|
|
|
|
return "Read Bandwidth";
|
|
|
|
case ACPI_HMAT_WRITE_BANDWIDTH:
|
|
|
|
return "Write Bandwidth";
|
|
|
|
default:
|
|
|
|
return "Reserved";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init const char *hmat_data_type_suffix(u8 type)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case ACPI_HMAT_ACCESS_LATENCY:
|
|
|
|
case ACPI_HMAT_READ_LATENCY:
|
|
|
|
case ACPI_HMAT_WRITE_LATENCY:
|
|
|
|
return " nsec";
|
|
|
|
case ACPI_HMAT_ACCESS_BANDWIDTH:
|
|
|
|
case ACPI_HMAT_READ_BANDWIDTH:
|
|
|
|
case ACPI_HMAT_WRITE_BANDWIDTH:
|
|
|
|
return " MB/s";
|
|
|
|
default:
|
|
|
|
return "";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static u32 hmat_normalize(u16 entry, u64 base, u8 type)
|
2019-03-12 03:55:59 +07:00
|
|
|
{
|
|
|
|
u32 value;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for invalid and overflow values
|
|
|
|
*/
|
|
|
|
if (entry == 0xffff || !entry)
|
|
|
|
return 0;
|
|
|
|
else if (base > (UINT_MAX / (entry)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Divide by the base unit for version 1, convert latency from
|
|
|
|
* picosenonds to nanoseconds if revision 2.
|
|
|
|
*/
|
|
|
|
value = entry * base;
|
|
|
|
if (hmat_revision == 1) {
|
|
|
|
if (value < 10)
|
|
|
|
return 0;
|
|
|
|
value = DIV_ROUND_UP(value, 10);
|
|
|
|
} else if (hmat_revision == 2) {
|
|
|
|
switch (type) {
|
|
|
|
case ACPI_HMAT_ACCESS_LATENCY:
|
|
|
|
case ACPI_HMAT_READ_LATENCY:
|
|
|
|
case ACPI_HMAT_WRITE_LATENCY:
|
|
|
|
value = DIV_ROUND_UP(value, 1000);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static void hmat_update_target_access(struct memory_target *target,
|
2019-03-12 03:56:03 +07:00
|
|
|
u8 type, u32 value)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case ACPI_HMAT_ACCESS_LATENCY:
|
|
|
|
target->hmem_attrs.read_latency = value;
|
|
|
|
target->hmem_attrs.write_latency = value;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_READ_LATENCY:
|
|
|
|
target->hmem_attrs.read_latency = value;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_WRITE_LATENCY:
|
|
|
|
target->hmem_attrs.write_latency = value;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_ACCESS_BANDWIDTH:
|
|
|
|
target->hmem_attrs.read_bandwidth = value;
|
|
|
|
target->hmem_attrs.write_bandwidth = value;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_READ_BANDWIDTH:
|
|
|
|
target->hmem_attrs.read_bandwidth = value;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_WRITE_BANDWIDTH:
|
|
|
|
target->hmem_attrs.write_bandwidth = value;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init void hmat_add_locality(struct acpi_hmat_locality *hmat_loc)
|
|
|
|
{
|
|
|
|
struct memory_locality *loc;
|
|
|
|
|
|
|
|
loc = kzalloc(sizeof(*loc), GFP_KERNEL);
|
|
|
|
if (!loc) {
|
|
|
|
pr_notice_once("Failed to allocate HMAT locality\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
loc->hmat_loc = hmat_loc;
|
|
|
|
list_add_tail(&loc->node, &localities);
|
|
|
|
|
|
|
|
switch (hmat_loc->data_type) {
|
|
|
|
case ACPI_HMAT_ACCESS_LATENCY:
|
|
|
|
localities_types[READ_LATENCY] = loc;
|
|
|
|
localities_types[WRITE_LATENCY] = loc;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_READ_LATENCY:
|
|
|
|
localities_types[READ_LATENCY] = loc;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_WRITE_LATENCY:
|
|
|
|
localities_types[WRITE_LATENCY] = loc;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_ACCESS_BANDWIDTH:
|
|
|
|
localities_types[READ_BANDWIDTH] = loc;
|
|
|
|
localities_types[WRITE_BANDWIDTH] = loc;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_READ_BANDWIDTH:
|
|
|
|
localities_types[READ_BANDWIDTH] = loc;
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_WRITE_BANDWIDTH:
|
|
|
|
localities_types[WRITE_BANDWIDTH] = loc;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
static __init int hmat_parse_locality(union acpi_subtable_headers *header,
|
|
|
|
const unsigned long end)
|
|
|
|
{
|
|
|
|
struct acpi_hmat_locality *hmat_loc = (void *)header;
|
2019-03-12 03:56:03 +07:00
|
|
|
struct memory_target *target;
|
2019-03-12 03:55:59 +07:00
|
|
|
unsigned int init, targ, total_size, ipds, tpds;
|
|
|
|
u32 *inits, *targs, value;
|
|
|
|
u16 *entries;
|
2019-03-12 03:56:03 +07:00
|
|
|
u8 type, mem_hier;
|
2019-03-12 03:55:59 +07:00
|
|
|
|
|
|
|
if (hmat_loc->header.length < sizeof(*hmat_loc)) {
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_notice("HMAT: Unexpected locality header length: %u\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
hmat_loc->header.length);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
type = hmat_loc->data_type;
|
2019-03-12 03:56:03 +07:00
|
|
|
mem_hier = hmat_loc->flags & ACPI_HMAT_MEMORY_HIERARCHY;
|
2019-03-12 03:55:59 +07:00
|
|
|
ipds = hmat_loc->number_of_initiator_Pds;
|
|
|
|
tpds = hmat_loc->number_of_target_Pds;
|
|
|
|
total_size = sizeof(*hmat_loc) + sizeof(*entries) * ipds * tpds +
|
|
|
|
sizeof(*inits) * ipds + sizeof(*targs) * tpds;
|
|
|
|
if (hmat_loc->header.length < total_size) {
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_notice("HMAT: Unexpected locality header length:%u, minimum required:%u\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
hmat_loc->header.length, total_size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_info("HMAT: Locality: Flags:%02x Type:%s Initiator Domains:%u Target Domains:%u Base:%lld\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
hmat_loc->flags, hmat_data_type(type), ipds, tpds,
|
|
|
|
hmat_loc->entry_base_unit);
|
|
|
|
|
|
|
|
inits = (u32 *)(hmat_loc + 1);
|
|
|
|
targs = inits + ipds;
|
|
|
|
entries = (u16 *)(targs + tpds);
|
|
|
|
for (init = 0; init < ipds; init++) {
|
2019-03-12 03:56:03 +07:00
|
|
|
alloc_memory_initiator(inits[init]);
|
2019-03-12 03:55:59 +07:00
|
|
|
for (targ = 0; targ < tpds; targ++) {
|
|
|
|
value = hmat_normalize(entries[init * tpds + targ],
|
|
|
|
hmat_loc->entry_base_unit,
|
|
|
|
type);
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_info(" Initiator-Target[%u-%u]:%u%s\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
inits[init], targs[targ], value,
|
|
|
|
hmat_data_type_suffix(type));
|
2019-03-12 03:56:03 +07:00
|
|
|
|
|
|
|
if (mem_hier == ACPI_HMAT_MEMORY) {
|
|
|
|
target = find_mem_target(targs[targ]);
|
|
|
|
if (target && target->processor_pxm == inits[init])
|
|
|
|
hmat_update_target_access(target, type, value);
|
|
|
|
}
|
2019-03-12 03:55:59 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-03-12 03:56:03 +07:00
|
|
|
if (mem_hier == ACPI_HMAT_MEMORY)
|
|
|
|
hmat_add_locality(hmat_loc);
|
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static __init int hmat_parse_cache(union acpi_subtable_headers *header,
|
|
|
|
const unsigned long end)
|
|
|
|
{
|
|
|
|
struct acpi_hmat_cache *cache = (void *)header;
|
2019-08-05 21:27:04 +07:00
|
|
|
struct memory_target *target;
|
|
|
|
struct target_cache *tcache;
|
2019-03-12 03:55:59 +07:00
|
|
|
u32 attrs;
|
|
|
|
|
|
|
|
if (cache->header.length < sizeof(*cache)) {
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_notice("HMAT: Unexpected cache header length: %u\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
cache->header.length);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
attrs = cache->cache_attributes;
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_info("HMAT: Cache: Domain:%u Size:%llu Attrs:%08x SMBIOS Handles:%d\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
cache->memory_PD, cache->cache_size, attrs,
|
|
|
|
cache->number_of_SMBIOShandles);
|
|
|
|
|
2019-08-05 21:27:04 +07:00
|
|
|
target = find_mem_target(cache->memory_PD);
|
|
|
|
if (!target)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
tcache = kzalloc(sizeof(*tcache), GFP_KERNEL);
|
|
|
|
if (!tcache) {
|
|
|
|
pr_notice_once("Failed to allocate HMAT cache info\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
tcache->cache_attrs.size = cache->cache_size;
|
|
|
|
tcache->cache_attrs.level = (attrs & ACPI_HMAT_CACHE_LEVEL) >> 4;
|
|
|
|
tcache->cache_attrs.line_size = (attrs & ACPI_HMAT_CACHE_LINE_SIZE) >> 16;
|
2019-03-12 03:56:05 +07:00
|
|
|
|
|
|
|
switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) {
|
|
|
|
case ACPI_HMAT_CA_DIRECT_MAPPED:
|
2019-08-05 21:27:04 +07:00
|
|
|
tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP;
|
2019-03-12 03:56:05 +07:00
|
|
|
break;
|
|
|
|
case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING:
|
2019-08-05 21:27:04 +07:00
|
|
|
tcache->cache_attrs.indexing = NODE_CACHE_INDEXED;
|
2019-03-12 03:56:05 +07:00
|
|
|
break;
|
|
|
|
case ACPI_HMAT_CA_NONE:
|
|
|
|
default:
|
2019-08-05 21:27:04 +07:00
|
|
|
tcache->cache_attrs.indexing = NODE_CACHE_OTHER;
|
2019-03-12 03:56:05 +07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch ((attrs & ACPI_HMAT_WRITE_POLICY) >> 12) {
|
|
|
|
case ACPI_HMAT_CP_WB:
|
2019-08-05 21:27:04 +07:00
|
|
|
tcache->cache_attrs.write_policy = NODE_CACHE_WRITE_BACK;
|
2019-03-12 03:56:05 +07:00
|
|
|
break;
|
|
|
|
case ACPI_HMAT_CP_WT:
|
2019-08-05 21:27:04 +07:00
|
|
|
tcache->cache_attrs.write_policy = NODE_CACHE_WRITE_THROUGH;
|
2019-03-12 03:56:05 +07:00
|
|
|
break;
|
|
|
|
case ACPI_HMAT_CP_NONE:
|
|
|
|
default:
|
2019-08-05 21:27:04 +07:00
|
|
|
tcache->cache_attrs.write_policy = NODE_CACHE_WRITE_OTHER;
|
2019-03-12 03:56:05 +07:00
|
|
|
break;
|
|
|
|
}
|
2019-08-05 21:27:04 +07:00
|
|
|
list_add_tail(&tcache->node, &target->caches);
|
2019-03-12 03:56:05 +07:00
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *header,
|
|
|
|
const unsigned long end)
|
|
|
|
{
|
|
|
|
struct acpi_hmat_proximity_domain *p = (void *)header;
|
2019-04-07 08:12:22 +07:00
|
|
|
struct memory_target *target = NULL;
|
2019-03-12 03:55:59 +07:00
|
|
|
|
|
|
|
if (p->header.length != sizeof(*p)) {
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_notice("HMAT: Unexpected address range header length: %u\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
p->header.length);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hmat_revision == 1)
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_info("HMAT: Memory (%#llx length %#llx) Flags:%04x Processor Domain:%u Memory Domain:%u\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
p->reserved3, p->reserved4, p->flags, p->processor_PD,
|
|
|
|
p->memory_PD);
|
|
|
|
else
|
2019-10-30 13:34:03 +07:00
|
|
|
pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
|
2019-03-12 03:55:59 +07:00
|
|
|
p->flags, p->processor_PD, p->memory_PD);
|
|
|
|
|
2019-08-06 11:24:39 +07:00
|
|
|
if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
|
2019-03-12 03:56:03 +07:00
|
|
|
target = find_mem_target(p->memory_PD);
|
|
|
|
if (!target) {
|
|
|
|
pr_debug("HMAT: Memory Domain missing from SRAT\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (target && p->flags & ACPI_HMAT_PROCESSOR_PD_VALID) {
|
|
|
|
int p_node = pxm_to_node(p->processor_PD);
|
|
|
|
|
|
|
|
if (p_node == NUMA_NO_NODE) {
|
|
|
|
pr_debug("HMAT: Invalid Processor Domain\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2019-10-28 16:11:18 +07:00
|
|
|
target->processor_pxm = p->processor_PD;
|
2019-03-12 03:56:03 +07:00
|
|
|
}
|
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init hmat_parse_subtable(union acpi_subtable_headers *header,
|
|
|
|
const unsigned long end)
|
|
|
|
{
|
|
|
|
struct acpi_hmat_structure *hdr = (void *)header;
|
|
|
|
|
|
|
|
if (!hdr)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (hdr->type) {
|
2019-04-18 01:13:10 +07:00
|
|
|
case ACPI_HMAT_TYPE_PROXIMITY:
|
2019-03-12 03:55:59 +07:00
|
|
|
return hmat_parse_proximity_domain(header, end);
|
|
|
|
case ACPI_HMAT_TYPE_LOCALITY:
|
|
|
|
return hmat_parse_locality(header, end);
|
|
|
|
case ACPI_HMAT_TYPE_CACHE:
|
|
|
|
return hmat_parse_cache(header, end);
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-03-12 03:56:03 +07:00
|
|
|
static __init int srat_parse_mem_affinity(union acpi_subtable_headers *header,
|
|
|
|
const unsigned long end)
|
|
|
|
{
|
|
|
|
struct acpi_srat_mem_affinity *ma = (void *)header;
|
|
|
|
|
|
|
|
if (!ma)
|
|
|
|
return -EINVAL;
|
|
|
|
if (!(ma->flags & ACPI_SRAT_MEM_ENABLED))
|
|
|
|
return 0;
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
alloc_memory_target(ma->proximity_domain, ma->base_address, ma->length);
|
2019-03-12 03:56:03 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static u32 hmat_initiator_perf(struct memory_target *target,
|
2019-03-12 03:56:03 +07:00
|
|
|
struct memory_initiator *initiator,
|
|
|
|
struct acpi_hmat_locality *hmat_loc)
|
|
|
|
{
|
|
|
|
unsigned int ipds, tpds, i, idx = 0, tdx = 0;
|
|
|
|
u32 *inits, *targs;
|
|
|
|
u16 *entries;
|
|
|
|
|
|
|
|
ipds = hmat_loc->number_of_initiator_Pds;
|
|
|
|
tpds = hmat_loc->number_of_target_Pds;
|
|
|
|
inits = (u32 *)(hmat_loc + 1);
|
|
|
|
targs = inits + ipds;
|
|
|
|
entries = (u16 *)(targs + tpds);
|
|
|
|
|
|
|
|
for (i = 0; i < ipds; i++) {
|
|
|
|
if (inits[i] == initiator->processor_pxm) {
|
|
|
|
idx = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == ipds)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (i = 0; i < tpds; i++) {
|
|
|
|
if (targs[i] == target->memory_pxm) {
|
|
|
|
tdx = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i == tpds)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return hmat_normalize(entries[idx * tpds + tdx],
|
|
|
|
hmat_loc->entry_base_unit,
|
|
|
|
hmat_loc->data_type);
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static bool hmat_update_best(u8 type, u32 value, u32 *best)
|
2019-03-12 03:56:03 +07:00
|
|
|
{
|
|
|
|
bool updated = false;
|
|
|
|
|
|
|
|
if (!value)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case ACPI_HMAT_ACCESS_LATENCY:
|
|
|
|
case ACPI_HMAT_READ_LATENCY:
|
|
|
|
case ACPI_HMAT_WRITE_LATENCY:
|
|
|
|
if (!*best || *best > value) {
|
|
|
|
*best = value;
|
|
|
|
updated = true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ACPI_HMAT_ACCESS_BANDWIDTH:
|
|
|
|
case ACPI_HMAT_READ_BANDWIDTH:
|
|
|
|
case ACPI_HMAT_WRITE_BANDWIDTH:
|
|
|
|
if (!*best || *best < value) {
|
|
|
|
*best = value;
|
|
|
|
updated = true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return updated;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int initiator_cmp(void *priv, struct list_head *a, struct list_head *b)
|
|
|
|
{
|
|
|
|
struct memory_initiator *ia;
|
|
|
|
struct memory_initiator *ib;
|
|
|
|
unsigned long *p_nodes = priv;
|
|
|
|
|
|
|
|
ia = list_entry(a, struct memory_initiator, node);
|
|
|
|
ib = list_entry(b, struct memory_initiator, node);
|
|
|
|
|
|
|
|
set_bit(ia->processor_pxm, p_nodes);
|
|
|
|
set_bit(ib->processor_pxm, p_nodes);
|
|
|
|
|
|
|
|
return ia->processor_pxm - ib->processor_pxm;
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static void hmat_register_target_initiators(struct memory_target *target)
|
2019-03-12 03:56:03 +07:00
|
|
|
{
|
|
|
|
static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
|
|
|
|
struct memory_initiator *initiator;
|
|
|
|
unsigned int mem_nid, cpu_nid;
|
|
|
|
struct memory_locality *loc = NULL;
|
|
|
|
u32 best = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
mem_nid = pxm_to_node(target->memory_pxm);
|
|
|
|
/*
|
|
|
|
* If the Address Range Structure provides a local processor pxm, link
|
|
|
|
* only that one. Otherwise, find the best performance attributes and
|
|
|
|
* register all initiators that match.
|
|
|
|
*/
|
|
|
|
if (target->processor_pxm != PXM_INVAL) {
|
|
|
|
cpu_nid = pxm_to_node(target->processor_pxm);
|
|
|
|
register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (list_empty(&localities))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need the initiator list sorted so we can use bitmap_clear for
|
|
|
|
* previously set initiators when we find a better memory accessor.
|
|
|
|
* We'll also use the sorting to prime the candidate nodes with known
|
|
|
|
* initiators.
|
|
|
|
*/
|
|
|
|
bitmap_zero(p_nodes, MAX_NUMNODES);
|
|
|
|
list_sort(p_nodes, &initiators, initiator_cmp);
|
|
|
|
for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
|
|
|
|
loc = localities_types[i];
|
|
|
|
if (!loc)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
best = 0;
|
|
|
|
list_for_each_entry(initiator, &initiators, node) {
|
|
|
|
u32 value;
|
|
|
|
|
|
|
|
if (!test_bit(initiator->processor_pxm, p_nodes))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
value = hmat_initiator_perf(target, initiator, loc->hmat_loc);
|
|
|
|
if (hmat_update_best(loc->hmat_loc->data_type, value, &best))
|
|
|
|
bitmap_clear(p_nodes, 0, initiator->processor_pxm);
|
|
|
|
if (value != best)
|
|
|
|
clear_bit(initiator->processor_pxm, p_nodes);
|
|
|
|
}
|
|
|
|
if (best)
|
|
|
|
hmat_update_target_access(target, loc->hmat_loc->data_type, best);
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
|
|
|
|
cpu_nid = pxm_to_node(i);
|
|
|
|
register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static void hmat_register_target_cache(struct memory_target *target)
|
2019-08-05 21:27:04 +07:00
|
|
|
{
|
|
|
|
unsigned mem_nid = pxm_to_node(target->memory_pxm);
|
|
|
|
struct target_cache *tcache;
|
|
|
|
|
|
|
|
list_for_each_entry(tcache, &target->caches, node)
|
|
|
|
node_add_cache(mem_nid, &tcache->cache_attrs);
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static void hmat_register_target_perf(struct memory_target *target)
|
2019-03-12 03:56:04 +07:00
|
|
|
{
|
|
|
|
unsigned mem_nid = pxm_to_node(target->memory_pxm);
|
|
|
|
node_set_perf_attrs(mem_nid, &target->hmem_attrs, 0);
|
|
|
|
}
|
|
|
|
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
static void hmat_register_target_device(struct memory_target *target,
|
|
|
|
struct resource *r)
|
|
|
|
{
|
|
|
|
/* define a clean / non-busy resource for the platform device */
|
|
|
|
struct resource res = {
|
|
|
|
.start = r->start,
|
|
|
|
.end = r->end,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
};
|
|
|
|
struct platform_device *pdev;
|
|
|
|
struct memregion_info info;
|
|
|
|
int rc, id;
|
|
|
|
|
|
|
|
rc = region_intersects(res.start, resource_size(&res), IORESOURCE_MEM,
|
|
|
|
IORES_DESC_SOFT_RESERVED);
|
|
|
|
if (rc != REGION_INTERSECTS)
|
|
|
|
return;
|
|
|
|
|
|
|
|
id = memregion_alloc(GFP_KERNEL);
|
|
|
|
if (id < 0) {
|
|
|
|
pr_err("memregion allocation failure for %pr\n", &res);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
pdev = platform_device_alloc("hmem", id);
|
|
|
|
if (!pdev) {
|
|
|
|
pr_err("hmem device allocation failure for %pr\n", &res);
|
|
|
|
goto out_pdev;
|
|
|
|
}
|
|
|
|
|
|
|
|
pdev->dev.numa_node = acpi_map_pxm_to_online_node(target->memory_pxm);
|
|
|
|
info = (struct memregion_info) {
|
|
|
|
.target_node = acpi_map_pxm_to_node(target->memory_pxm),
|
|
|
|
};
|
|
|
|
rc = platform_device_add_data(pdev, &info, sizeof(info));
|
|
|
|
if (rc < 0) {
|
|
|
|
pr_err("hmem memregion_info allocation failure for %pr\n", &res);
|
|
|
|
goto out_pdev;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = platform_device_add_resources(pdev, &res, 1);
|
|
|
|
if (rc < 0) {
|
|
|
|
pr_err("hmem resource allocation failure for %pr\n", &res);
|
|
|
|
goto out_resource;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = platform_device_add(pdev);
|
|
|
|
if (rc < 0) {
|
|
|
|
dev_err(&pdev->dev, "device add failed for %pr\n", &res);
|
|
|
|
goto out_resource;
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
out_resource:
|
|
|
|
put_device(&pdev->dev);
|
|
|
|
out_pdev:
|
|
|
|
memregion_free(id);
|
|
|
|
}
|
|
|
|
|
2019-11-12 04:34:26 +07:00
|
|
|
static void hmat_register_target_devices(struct memory_target *target)
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do not bother creating devices if no driver is available to
|
|
|
|
* consume them.
|
|
|
|
*/
|
|
|
|
if (!IS_ENABLED(CONFIG_DEV_DAX_HMEM))
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (res = target->memregions.child; res; res = res->sibling)
|
|
|
|
hmat_register_target_device(target, res);
|
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static void hmat_register_target(struct memory_target *target)
|
2019-08-05 21:27:04 +07:00
|
|
|
{
|
2019-08-05 21:27:06 +07:00
|
|
|
int nid = pxm_to_node(target->memory_pxm);
|
|
|
|
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
/*
|
|
|
|
* Devices may belong to either an offline or online
|
|
|
|
* node, so unconditionally add them.
|
|
|
|
*/
|
|
|
|
hmat_register_target_devices(target);
|
|
|
|
|
2019-08-05 21:27:06 +07:00
|
|
|
/*
|
|
|
|
* Skip offline nodes. This can happen when memory
|
|
|
|
* marked EFI_MEMORY_SP, "specific purpose", is applied
|
|
|
|
* to all the memory in a promixity domain leading to
|
|
|
|
* the node being marked offline / unplugged, or if
|
|
|
|
* memory-only "hotplug" node is offline.
|
|
|
|
*/
|
|
|
|
if (nid == NUMA_NO_NODE || !node_online(nid))
|
2019-08-05 21:27:04 +07:00
|
|
|
return;
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
mutex_lock(&target_lock);
|
|
|
|
if (!target->registered) {
|
|
|
|
hmat_register_target_initiators(target);
|
|
|
|
hmat_register_target_cache(target);
|
|
|
|
hmat_register_target_perf(target);
|
|
|
|
target->registered = true;
|
|
|
|
}
|
|
|
|
mutex_unlock(&target_lock);
|
2019-08-05 21:27:04 +07:00
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static void hmat_register_targets(void)
|
2019-03-12 03:56:03 +07:00
|
|
|
{
|
|
|
|
struct memory_target *target;
|
|
|
|
|
2019-08-05 21:27:04 +07:00
|
|
|
list_for_each_entry(target, &targets, node)
|
|
|
|
hmat_register_target(target);
|
2019-03-12 03:56:03 +07:00
|
|
|
}
|
|
|
|
|
2019-08-05 21:27:05 +07:00
|
|
|
static int hmat_callback(struct notifier_block *self,
|
|
|
|
unsigned long action, void *arg)
|
|
|
|
{
|
|
|
|
struct memory_target *target;
|
|
|
|
struct memory_notify *mnb = arg;
|
|
|
|
int pxm, nid = mnb->status_change_nid;
|
|
|
|
|
|
|
|
if (nid == NUMA_NO_NODE || action != MEM_ONLINE)
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
|
|
|
pxm = node_to_pxm(nid);
|
|
|
|
target = find_mem_target(pxm);
|
|
|
|
if (!target)
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
|
|
|
hmat_register_target(target);
|
|
|
|
return NOTIFY_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct notifier_block hmat_callback_nb = {
|
|
|
|
.notifier_call = hmat_callback,
|
|
|
|
.priority = 2,
|
|
|
|
};
|
|
|
|
|
2019-03-12 03:56:03 +07:00
|
|
|
static __init void hmat_free_structures(void)
|
|
|
|
{
|
|
|
|
struct memory_target *target, *tnext;
|
|
|
|
struct memory_locality *loc, *lnext;
|
|
|
|
struct memory_initiator *initiator, *inext;
|
2019-08-05 21:27:04 +07:00
|
|
|
struct target_cache *tcache, *cnext;
|
2019-03-12 03:56:03 +07:00
|
|
|
|
|
|
|
list_for_each_entry_safe(target, tnext, &targets, node) {
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
struct resource *res, *res_next;
|
|
|
|
|
2019-08-05 21:27:04 +07:00
|
|
|
list_for_each_entry_safe(tcache, cnext, &target->caches, node) {
|
|
|
|
list_del(&tcache->node);
|
|
|
|
kfree(tcache);
|
|
|
|
}
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
|
2019-03-12 03:56:03 +07:00
|
|
|
list_del(&target->node);
|
ACPI: NUMA: HMAT: Register "soft reserved" memory as an "hmem" device
Memory that has been tagged EFI_MEMORY_SP, and has performance
properties described by the ACPI HMAT is expected to have an application
specific consumer.
Those consumers may want 100% of the memory capacity to be reserved from
any usage by the kernel. By default, with this enabling, a platform
device is created to represent this differentiated resource.
The device-dax "hmem" driver claims these devices by default and
provides an mmap interface for the target application. If the
administrator prefers, the hmem resource range can be made available to
the core-mm via the device-dax hotplug facility, kmem, to online the
memory with its own numa node.
This was tested with an emulated HMAT produced by qemu (with the pending
HMAT enabling patches), and "efi_fake_mem=8G@9G:0x40000" on the kernel
command line to mark the memory ranges associated with node2 and node3
as EFI_MEMORY_SP.
qemu numa configuration options:
-numa node,mem=4G,cpus=0-19,nodeid=0
-numa node,mem=4G,cpus=20-39,nodeid=1
-numa node,mem=4G,nodeid=2
-numa node,mem=4G,nodeid=3
-numa dist,src=0,dst=0,val=10
-numa dist,src=0,dst=1,val=21
-numa dist,src=0,dst=2,val=21
-numa dist,src=0,dst=3,val=21
-numa dist,src=1,dst=0,val=21
-numa dist,src=1,dst=1,val=10
-numa dist,src=1,dst=2,val=21
-numa dist,src=1,dst=3,val=21
-numa dist,src=2,dst=0,val=21
-numa dist,src=2,dst=1,val=21
-numa dist,src=2,dst=2,val=10
-numa dist,src=2,dst=3,val=21
-numa dist,src=3,dst=0,val=21
-numa dist,src=3,dst=1,val=21
-numa dist,src=3,dst=2,val=21
-numa dist,src=3,dst=3,val=10
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=0,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,base-lat=10,latency=10
-numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=10
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,base-lat=10,latency=5
-numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=5
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,base-lat=10,latency=15
-numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=15
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-latency,base-lat=10,latency=20
-numa hmat-lb,initiator=1,target=3,hierarchy=memory,data-type=access-bandwidth,base-bw=20,bandwidth=20
Result:
[
{
"path":"\/platform\/hmem.1",
"id":1,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax1.0",
"size":"4.00 GiB (4.29 GB)"
}
]
},
{
"path":"\/platform\/hmem.0",
"id":0,
"size":"4.00 GiB (4.29 GB)",
"align":2097152,
"devices":[
{
"chardev":"dax0.0",
"size":"4.00 GiB (4.29 GB)"
}
]
}
]
[..]
240000000-43fffffff : Soft Reserved
240000000-33fffffff : hmem.0
240000000-33fffffff : dax0.0
340000000-43fffffff : hmem.1
340000000-43fffffff : dax1.0
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2019-11-07 08:43:55 +07:00
|
|
|
res = target->memregions.child;
|
|
|
|
while (res) {
|
|
|
|
res_next = res->sibling;
|
|
|
|
__release_region(&target->memregions, res->start,
|
|
|
|
resource_size(res));
|
|
|
|
res = res_next;
|
|
|
|
}
|
2019-03-12 03:56:03 +07:00
|
|
|
kfree(target);
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry_safe(initiator, inext, &initiators, node) {
|
|
|
|
list_del(&initiator->node);
|
|
|
|
kfree(initiator);
|
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry_safe(loc, lnext, &localities, node) {
|
|
|
|
list_del(&loc->node);
|
|
|
|
kfree(loc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
static __init int hmat_init(void)
|
|
|
|
{
|
|
|
|
struct acpi_table_header *tbl;
|
|
|
|
enum acpi_hmat_type i;
|
|
|
|
acpi_status status;
|
|
|
|
|
|
|
|
if (srat_disabled())
|
|
|
|
return 0;
|
|
|
|
|
2019-03-12 03:56:03 +07:00
|
|
|
status = acpi_get_table(ACPI_SIG_SRAT, 0, &tbl);
|
|
|
|
if (ACPI_FAILURE(status))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (acpi_table_parse_entries(ACPI_SIG_SRAT,
|
|
|
|
sizeof(struct acpi_table_srat),
|
|
|
|
ACPI_SRAT_TYPE_MEMORY_AFFINITY,
|
|
|
|
srat_parse_mem_affinity, 0) < 0)
|
|
|
|
goto out_put;
|
|
|
|
acpi_put_table(tbl);
|
|
|
|
|
2019-03-12 03:55:59 +07:00
|
|
|
status = acpi_get_table(ACPI_SIG_HMAT, 0, &tbl);
|
|
|
|
if (ACPI_FAILURE(status))
|
2019-04-10 09:14:50 +07:00
|
|
|
goto out_put;
|
2019-03-12 03:55:59 +07:00
|
|
|
|
|
|
|
hmat_revision = tbl->revision;
|
|
|
|
switch (hmat_revision) {
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_notice("Ignoring HMAT: Unknown revision:%d\n", hmat_revision);
|
|
|
|
goto out_put;
|
|
|
|
}
|
|
|
|
|
2019-04-18 01:13:10 +07:00
|
|
|
for (i = ACPI_HMAT_TYPE_PROXIMITY; i < ACPI_HMAT_TYPE_RESERVED; i++) {
|
2019-03-12 03:55:59 +07:00
|
|
|
if (acpi_table_parse_entries(ACPI_SIG_HMAT,
|
|
|
|
sizeof(struct acpi_table_hmat), i,
|
|
|
|
hmat_parse_subtable, 0) < 0) {
|
|
|
|
pr_notice("Ignoring HMAT: Invalid table");
|
|
|
|
goto out_put;
|
|
|
|
}
|
|
|
|
}
|
2019-03-12 03:56:03 +07:00
|
|
|
hmat_register_targets();
|
2019-08-05 21:27:05 +07:00
|
|
|
|
|
|
|
/* Keep the table and structures if the notifier may use them */
|
|
|
|
if (!register_hotmemory_notifier(&hmat_callback_nb))
|
|
|
|
return 0;
|
2019-03-12 03:55:59 +07:00
|
|
|
out_put:
|
2019-03-12 03:56:03 +07:00
|
|
|
hmat_free_structures();
|
2019-03-12 03:55:59 +07:00
|
|
|
acpi_put_table(tbl);
|
|
|
|
return 0;
|
|
|
|
}
|
2019-11-07 08:43:49 +07:00
|
|
|
device_initcall(hmat_init);
|