linux_dsm_epyc7002/arch/arm64/boot/dts/mediatek/mt8173.dtsi

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Eddie Huang <eddie.huang@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/mt8173-resets.h>
#include "mt8173-pinfunc.h"

/ {
	compatible = "mediatek,mt8173";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x100>;
			enable-method = "psci";
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x101>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend   = <0x84000001>;
		cpu_off	      = <0x84000002>;
		cpu_on	      = <0x84000003>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "clk32k";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		topckgen: clock-controller@10000000 {
			compatible = "mediatek,mt8173-topckgen";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: power-controller@10001000 {
			compatible = "mediatek,mt8173-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: power-controller@10003000 {
			compatible = "mediatek,mt8173-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		syscfg_pctl_a: syscfg_pctl_a@10005000 {
			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
			reg = <0 0x10005000 0 0x1000>;
		};

		pio: pinctrl@0x10005000 {
			compatible = "mediatek,mt8173-pinctrl";
			reg = <0 0x1000b000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl_a>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		};

		syscfg_pctl_a: syscfg_pctl_a@10005000 {
			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
			reg = <0 0x10005000 0 0x1000>;
		};

		pwrap: pwrap@1000d000 {
			compatible = "mediatek,mt8173-pwrap";
			reg = <0 0x1000d000 0 0x1000>;
			reg-names = "pwrap";
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
			reset-names = "pwrap";
			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
			clock-names = "spi", "wrap";
		};

		sysirq: intpol-controller@10200620 {
			compatible = "mediatek,mt8173-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200620 0 0x20>;
		};

		apmixedsys: clock-controller@10209000 {
			compatible = "mediatek,mt8173-apmixedsys";
			reg = <0 0x10209000 0 0x1000>;
			#clock-cells = <1>;
		};

		gic: interrupt-controller@10220000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x10221000 0 0x1000>,
			      <0 0x10222000 0 0x2000>,
			      <0 0x10224000 0 0x2000>,
			      <0 0x10226000 0 0x2000>;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
			clock-names = "baud", "bus";
			status = "disabled";
		};
	};
};