2016-01-21 02:40:13 +07:00
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/*******************************************************************************
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*
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* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*******************************************************************************/
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#ifndef I40IW_USER_H
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#define I40IW_USER_H
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enum i40iw_device_capabilities_const {
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I40IW_WQE_SIZE = 4,
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I40IW_CQP_WQE_SIZE = 8,
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I40IW_CQE_SIZE = 4,
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I40IW_EXTENDED_CQE_SIZE = 8,
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I40IW_AEQE_SIZE = 2,
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I40IW_CEQE_SIZE = 1,
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I40IW_CQP_CTX_SIZE = 8,
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I40IW_SHADOW_AREA_SIZE = 8,
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I40IW_CEQ_MAX_COUNT = 256,
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I40IW_QUERY_FPM_BUF_SIZE = 128,
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I40IW_COMMIT_FPM_BUF_SIZE = 128,
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I40IW_MIN_IW_QP_ID = 1,
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I40IW_MAX_IW_QP_ID = 262143,
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I40IW_MIN_CEQID = 0,
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I40IW_MAX_CEQID = 256,
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I40IW_MIN_CQID = 0,
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I40IW_MAX_CQID = 131071,
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I40IW_MIN_AEQ_ENTRIES = 1,
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I40IW_MAX_AEQ_ENTRIES = 524287,
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I40IW_MIN_CEQ_ENTRIES = 1,
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I40IW_MAX_CEQ_ENTRIES = 131071,
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I40IW_MIN_CQ_SIZE = 1,
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I40IW_MAX_CQ_SIZE = 1048575,
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I40IW_MAX_AEQ_ALLOCATE_COUNT = 255,
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I40IW_DB_ID_ZERO = 0,
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I40IW_MAX_WQ_FRAGMENT_COUNT = 6,
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I40IW_MAX_SGE_RD = 1,
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I40IW_MAX_OUTBOUND_MESSAGE_SIZE = 2147483647,
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I40IW_MAX_INBOUND_MESSAGE_SIZE = 2147483647,
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I40IW_MAX_PUSH_PAGE_COUNT = 4096,
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I40IW_MAX_PE_ENABLED_VF_COUNT = 32,
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I40IW_MAX_VF_FPM_ID = 47,
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I40IW_MAX_VF_PER_PF = 127,
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I40IW_MAX_SQ_PAYLOAD_SIZE = 2145386496,
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I40IW_MAX_INLINE_DATA_SIZE = 112,
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I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE = 112,
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I40IW_MAX_IRD_SIZE = 32,
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I40IW_QPCTX_ENCD_MAXIRD = 3,
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I40IW_MAX_WQ_ENTRIES = 2048,
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I40IW_MAX_ORD_SIZE = 32,
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I40IW_Q2_BUFFER_SIZE = (248 + 100),
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I40IW_QP_CTX_SIZE = 248
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};
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#define i40iw_handle void *
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#define i40iw_adapter_handle i40iw_handle
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#define i40iw_qp_handle i40iw_handle
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#define i40iw_cq_handle i40iw_handle
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#define i40iw_srq_handle i40iw_handle
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#define i40iw_pd_id i40iw_handle
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#define i40iw_stag_handle i40iw_handle
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#define i40iw_stag_index u32
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#define i40iw_stag u32
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#define i40iw_stag_key u8
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#define i40iw_tagged_offset u64
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#define i40iw_access_privileges u32
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#define i40iw_physical_fragment u64
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#define i40iw_address_list u64 *
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#define I40IW_CREATE_STAG(index, key) (((index) << 8) + (key))
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#define I40IW_STAG_KEY_FROM_STAG(stag) ((stag) && 0x000000FF)
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#define I40IW_STAG_INDEX_FROM_STAG(stag) (((stag) && 0xFFFFFF00) >> 8)
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2016-04-18 22:32:54 +07:00
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#define I40IW_MAX_MR_SIZE 0x10000000000L
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2016-01-21 02:40:13 +07:00
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struct i40iw_qp_uk;
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struct i40iw_cq_uk;
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struct i40iw_srq_uk;
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struct i40iw_qp_uk_init_info;
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struct i40iw_cq_uk_init_info;
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struct i40iw_srq_uk_init_info;
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struct i40iw_sge {
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i40iw_tagged_offset tag_off;
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u32 len;
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i40iw_stag stag;
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};
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#define i40iw_sgl struct i40iw_sge *
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struct i40iw_ring {
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u32 head;
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u32 tail;
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u32 size;
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};
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struct i40iw_cqe {
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u64 buf[I40IW_CQE_SIZE];
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};
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struct i40iw_extended_cqe {
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u64 buf[I40IW_EXTENDED_CQE_SIZE];
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};
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struct i40iw_wqe {
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u64 buf[I40IW_WQE_SIZE];
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};
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struct i40iw_qp_uk_ops;
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enum i40iw_addressing_type {
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I40IW_ADDR_TYPE_ZERO_BASED = 0,
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I40IW_ADDR_TYPE_VA_BASED = 1,
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};
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#define I40IW_ACCESS_FLAGS_LOCALREAD 0x01
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#define I40IW_ACCESS_FLAGS_LOCALWRITE 0x02
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#define I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04
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#define I40IW_ACCESS_FLAGS_REMOTEREAD 0x05
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#define I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08
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#define I40IW_ACCESS_FLAGS_REMOTEWRITE 0x0a
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#define I40IW_ACCESS_FLAGS_BIND_WINDOW 0x10
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#define I40IW_ACCESS_FLAGS_ALL 0x1F
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#define I40IW_OP_TYPE_RDMA_WRITE 0
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#define I40IW_OP_TYPE_RDMA_READ 1
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#define I40IW_OP_TYPE_SEND 3
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#define I40IW_OP_TYPE_SEND_INV 4
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#define I40IW_OP_TYPE_SEND_SOL 5
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#define I40IW_OP_TYPE_SEND_SOL_INV 6
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#define I40IW_OP_TYPE_REC 7
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#define I40IW_OP_TYPE_BIND_MW 8
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#define I40IW_OP_TYPE_FAST_REG_NSMR 9
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#define I40IW_OP_TYPE_INV_STAG 10
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#define I40IW_OP_TYPE_RDMA_READ_INV_STAG 11
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#define I40IW_OP_TYPE_NOP 12
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enum i40iw_completion_status {
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I40IW_COMPL_STATUS_SUCCESS = 0,
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I40IW_COMPL_STATUS_FLUSHED,
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I40IW_COMPL_STATUS_INVALID_WQE,
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I40IW_COMPL_STATUS_QP_CATASTROPHIC,
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I40IW_COMPL_STATUS_REMOTE_TERMINATION,
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I40IW_COMPL_STATUS_INVALID_STAG,
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I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION,
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I40IW_COMPL_STATUS_ACCESS_VIOLATION,
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I40IW_COMPL_STATUS_INVALID_PD_ID,
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I40IW_COMPL_STATUS_WRAP_ERROR,
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I40IW_COMPL_STATUS_STAG_INVALID_PDID,
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I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD,
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I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED,
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I40IW_COMPL_STATUS_STAG_NOT_INVALID,
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I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE,
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I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY,
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I40IW_COMPL_STATUS_INVALID_FBO,
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I40IW_COMPL_STATUS_INVALID_LENGTH,
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I40IW_COMPL_STATUS_INVALID_ACCESS,
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I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG,
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I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS,
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I40IW_COMPL_STATUS_INVALID_REGION,
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I40IW_COMPL_STATUS_INVALID_WINDOW,
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I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH
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};
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enum i40iw_completion_notify {
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IW_CQ_COMPL_EVENT = 0,
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IW_CQ_COMPL_SOLICITED = 1
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};
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struct i40iw_post_send {
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i40iw_sgl sg_list;
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u8 num_sges;
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};
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struct i40iw_post_inline_send {
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void *data;
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u32 len;
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};
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struct i40iw_post_send_w_inv {
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i40iw_sgl sg_list;
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u32 num_sges;
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i40iw_stag remote_stag_to_inv;
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};
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struct i40iw_post_inline_send_w_inv {
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void *data;
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u32 len;
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i40iw_stag remote_stag_to_inv;
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};
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struct i40iw_rdma_write {
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i40iw_sgl lo_sg_list;
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u8 num_lo_sges;
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struct i40iw_sge rem_addr;
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};
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struct i40iw_inline_rdma_write {
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void *data;
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u32 len;
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struct i40iw_sge rem_addr;
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};
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struct i40iw_rdma_read {
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struct i40iw_sge lo_addr;
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struct i40iw_sge rem_addr;
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};
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struct i40iw_bind_window {
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i40iw_stag mr_stag;
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u64 bind_length;
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void *va;
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enum i40iw_addressing_type addressing_type;
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bool enable_reads;
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bool enable_writes;
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i40iw_stag mw_stag;
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};
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struct i40iw_inv_local_stag {
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i40iw_stag target_stag;
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};
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struct i40iw_post_sq_info {
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u64 wr_id;
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u8 op_type;
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bool signaled;
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bool read_fence;
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bool local_fence;
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bool inline_data;
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bool defer_flag;
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union {
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struct i40iw_post_send send;
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struct i40iw_post_send send_w_sol;
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struct i40iw_post_send_w_inv send_w_inv;
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struct i40iw_post_send_w_inv send_w_sol_inv;
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struct i40iw_rdma_write rdma_write;
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struct i40iw_rdma_read rdma_read;
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struct i40iw_rdma_read rdma_read_inv;
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struct i40iw_bind_window bind_window;
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struct i40iw_inv_local_stag inv_local_stag;
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struct i40iw_inline_rdma_write inline_rdma_write;
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struct i40iw_post_inline_send inline_send;
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struct i40iw_post_inline_send inline_send_w_sol;
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struct i40iw_post_inline_send_w_inv inline_send_w_inv;
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struct i40iw_post_inline_send_w_inv inline_send_w_sol_inv;
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} op;
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};
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struct i40iw_post_rq_info {
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u64 wr_id;
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i40iw_sgl sg_list;
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u32 num_sges;
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};
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struct i40iw_cq_poll_info {
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u64 wr_id;
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i40iw_qp_handle qp_handle;
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u32 bytes_xfered;
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u32 tcp_seq_num;
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u32 qp_id;
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i40iw_stag inv_stag;
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enum i40iw_completion_status comp_status;
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u16 major_err;
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u16 minor_err;
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u8 op_type;
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bool stag_invalid_set;
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bool push_dropped;
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bool error;
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bool is_srq;
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bool solicited_event;
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};
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struct i40iw_qp_uk_ops {
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void (*iw_qp_post_wr)(struct i40iw_qp_uk *);
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void (*iw_qp_ring_push_db)(struct i40iw_qp_uk *, u32);
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enum i40iw_status_code (*iw_rdma_write)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, bool);
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enum i40iw_status_code (*iw_rdma_read)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, bool, bool);
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enum i40iw_status_code (*iw_send)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, u32, bool);
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enum i40iw_status_code (*iw_inline_rdma_write)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, bool);
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enum i40iw_status_code (*iw_inline_send)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, u32, bool);
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enum i40iw_status_code (*iw_stag_local_invalidate)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, bool);
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enum i40iw_status_code (*iw_mw_bind)(struct i40iw_qp_uk *,
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struct i40iw_post_sq_info *, bool);
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enum i40iw_status_code (*iw_post_receive)(struct i40iw_qp_uk *,
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struct i40iw_post_rq_info *);
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enum i40iw_status_code (*iw_post_nop)(struct i40iw_qp_uk *, u64, bool, bool);
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};
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struct i40iw_cq_ops {
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void (*iw_cq_request_notification)(struct i40iw_cq_uk *,
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enum i40iw_completion_notify);
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enum i40iw_status_code (*iw_cq_poll_completion)(struct i40iw_cq_uk *,
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struct i40iw_cq_poll_info *, bool);
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enum i40iw_status_code (*iw_cq_post_entries)(struct i40iw_cq_uk *, u8 count);
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void (*iw_cq_clean)(void *, struct i40iw_cq_uk *);
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};
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struct i40iw_dev_uk;
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struct i40iw_device_uk_ops {
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enum i40iw_status_code (*iwarp_cq_uk_init)(struct i40iw_cq_uk *,
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struct i40iw_cq_uk_init_info *);
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enum i40iw_status_code (*iwarp_qp_uk_init)(struct i40iw_qp_uk *,
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struct i40iw_qp_uk_init_info *);
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};
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struct i40iw_dev_uk {
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struct i40iw_device_uk_ops ops_uk;
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};
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struct i40iw_sq_uk_wr_trk_info {
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u64 wrid;
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u64 wr_len;
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};
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struct i40iw_qp_quanta {
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u64 elem[I40IW_WQE_SIZE];
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};
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struct i40iw_qp_uk {
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struct i40iw_qp_quanta *sq_base;
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struct i40iw_qp_quanta *rq_base;
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u32 __iomem *wqe_alloc_reg;
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struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
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u64 *rq_wrid_array;
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u64 *shadow_area;
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u32 *push_db;
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u64 *push_wqe;
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struct i40iw_ring sq_ring;
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struct i40iw_ring rq_ring;
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struct i40iw_ring initial_ring;
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u32 qp_id;
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u32 sq_size;
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u32 rq_size;
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struct i40iw_qp_uk_ops ops;
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bool use_srq;
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u8 swqe_polarity;
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u8 swqe_polarity_deferred;
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u8 rwqe_polarity;
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u8 rq_wqe_size;
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u8 rq_wqe_size_multiplier;
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u8 max_sq_frag_cnt;
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u8 max_rq_frag_cnt;
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bool deferred_flag;
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};
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struct i40iw_cq_uk {
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struct i40iw_cqe *cq_base;
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u32 __iomem *cqe_alloc_reg;
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u64 *shadow_area;
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u32 cq_id;
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u32 cq_size;
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struct i40iw_ring cq_ring;
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u8 polarity;
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bool avoid_mem_cflct;
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struct i40iw_cq_ops ops;
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};
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struct i40iw_qp_uk_init_info {
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struct i40iw_qp_quanta *sq;
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struct i40iw_qp_quanta *rq;
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u32 __iomem *wqe_alloc_reg;
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u64 *shadow_area;
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struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
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u64 *rq_wrid_array;
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u32 *push_db;
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u64 *push_wqe;
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u32 qp_id;
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u32 sq_size;
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u32 rq_size;
|
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u8 max_sq_frag_cnt;
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u8 max_rq_frag_cnt;
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};
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struct i40iw_cq_uk_init_info {
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|
u32 __iomem *cqe_alloc_reg;
|
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struct i40iw_cqe *cq_base;
|
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|
u64 *shadow_area;
|
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|
|
u32 cq_size;
|
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|
|
u32 cq_id;
|
|
|
|
bool avoid_mem_cflct;
|
|
|
|
};
|
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|
|
void i40iw_device_init_uk(struct i40iw_dev_uk *dev);
|
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|
void i40iw_qp_post_wr(struct i40iw_qp_uk *qp);
|
|
|
|
u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx,
|
|
|
|
u8 wqe_size);
|
|
|
|
u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx);
|
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|
|
u64 *i40iw_qp_get_next_srq_wqe(struct i40iw_srq_uk *srq, u32 *wqe_idx);
|
|
|
|
|
|
|
|
enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
|
|
|
|
struct i40iw_cq_uk_init_info *info);
|
|
|
|
enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
|
|
|
|
struct i40iw_qp_uk_init_info *info);
|
|
|
|
|
|
|
|
void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq);
|
|
|
|
enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp, u64 wr_id,
|
|
|
|
bool signaled, bool post_sq);
|
|
|
|
enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u8 frag_cnt, u8 *wqe_size);
|
|
|
|
enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u8 frag_cnt, u8 *wqe_size);
|
|
|
|
enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
|
|
|
|
u8 *wqe_size);
|
|
|
|
enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u8 sge, u8 *shift);
|
|
|
|
#endif
|