License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2006-03-13 16:27:34 +07:00
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/* visemul.c: Emulation of VIS instructions.
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*
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* Copyright (C) 2006 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/thread_info.h>
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2009-12-11 16:07:53 +07:00
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#include <linux/perf_event.h>
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2006-03-13 16:27:34 +07:00
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#include <asm/ptrace.h>
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#include <asm/pstate.h>
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#include <asm/fpumacro.h>
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2016-12-25 02:46:01 +07:00
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#include <linux/uaccess.h>
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2012-03-29 00:30:03 +07:00
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#include <asm/cacheflush.h>
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2006-03-13 16:27:34 +07:00
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/* OPF field of various VIS instructions. */
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/* 000111011 - four 16-bit packs */
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#define FPACK16_OPF 0x03b
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/* 000111010 - two 32-bit packs */
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#define FPACK32_OPF 0x03a
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/* 000111101 - four 16-bit packs */
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#define FPACKFIX_OPF 0x03d
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/* 001001101 - four 16-bit expands */
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#define FEXPAND_OPF 0x04d
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/* 001001011 - two 32-bit merges */
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#define FPMERGE_OPF 0x04b
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2017-02-28 05:28:55 +07:00
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/* 000110001 - 8-by-16-bit partitioned product */
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2006-03-13 16:27:34 +07:00
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#define FMUL8x16_OPF 0x031
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/* 000110011 - 8-by-16-bit upper alpha partitioned product */
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#define FMUL8x16AU_OPF 0x033
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/* 000110101 - 8-by-16-bit lower alpha partitioned product */
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#define FMUL8x16AL_OPF 0x035
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/* 000110110 - upper 8-by-16-bit partitioned product */
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#define FMUL8SUx16_OPF 0x036
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/* 000110111 - lower 8-by-16-bit partitioned product */
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#define FMUL8ULx16_OPF 0x037
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/* 000111000 - upper 8-by-16-bit partitioned product */
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#define FMULD8SUx16_OPF 0x038
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/* 000111001 - lower unsigned 8-by-16-bit partitioned product */
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#define FMULD8ULx16_OPF 0x039
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/* 000101000 - four 16-bit compare; set rd if src1 > src2 */
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#define FCMPGT16_OPF 0x028
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/* 000101100 - two 32-bit compare; set rd if src1 > src2 */
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#define FCMPGT32_OPF 0x02c
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/* 000100000 - four 16-bit compare; set rd if src1 <= src2 */
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#define FCMPLE16_OPF 0x020
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/* 000100100 - two 32-bit compare; set rd if src1 <= src2 */
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#define FCMPLE32_OPF 0x024
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/* 000100010 - four 16-bit compare; set rd if src1 != src2 */
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#define FCMPNE16_OPF 0x022
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/* 000100110 - two 32-bit compare; set rd if src1 != src2 */
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#define FCMPNE32_OPF 0x026
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/* 000101010 - four 16-bit compare; set rd if src1 == src2 */
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#define FCMPEQ16_OPF 0x02a
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/* 000101110 - two 32-bit compare; set rd if src1 == src2 */
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#define FCMPEQ32_OPF 0x02e
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/* 000000000 - Eight 8-bit edge boundary processing */
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#define EDGE8_OPF 0x000
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/* 000000001 - Eight 8-bit edge boundary processing, no CC */
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#define EDGE8N_OPF 0x001
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/* 000000010 - Eight 8-bit edge boundary processing, little-endian */
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#define EDGE8L_OPF 0x002
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/* 000000011 - Eight 8-bit edge boundary processing, little-endian, no CC */
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#define EDGE8LN_OPF 0x003
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/* 000000100 - Four 16-bit edge boundary processing */
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#define EDGE16_OPF 0x004
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/* 000000101 - Four 16-bit edge boundary processing, no CC */
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#define EDGE16N_OPF 0x005
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/* 000000110 - Four 16-bit edge boundary processing, little-endian */
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#define EDGE16L_OPF 0x006
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/* 000000111 - Four 16-bit edge boundary processing, little-endian, no CC */
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#define EDGE16LN_OPF 0x007
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/* 000001000 - Two 32-bit edge boundary processing */
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#define EDGE32_OPF 0x008
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/* 000001001 - Two 32-bit edge boundary processing, no CC */
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#define EDGE32N_OPF 0x009
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/* 000001010 - Two 32-bit edge boundary processing, little-endian */
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#define EDGE32L_OPF 0x00a
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/* 000001011 - Two 32-bit edge boundary processing, little-endian, no CC */
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#define EDGE32LN_OPF 0x00b
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/* 000111110 - distance between 8 8-bit components */
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#define PDIST_OPF 0x03e
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/* 000010000 - convert 8-bit 3-D address to blocked byte address */
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#define ARRAY8_OPF 0x010
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/* 000010010 - convert 16-bit 3-D address to blocked byte address */
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#define ARRAY16_OPF 0x012
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/* 000010100 - convert 32-bit 3-D address to blocked byte address */
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#define ARRAY32_OPF 0x014
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/* 000011001 - Set the GSR.MASK field in preparation for a BSHUFFLE */
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#define BMASK_OPF 0x019
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/* 001001100 - Permute bytes as specified by GSR.MASK */
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#define BSHUFFLE_OPF 0x04c
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#define VIS_OPF_SHIFT 5
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#define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT)
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2008-12-04 10:36:05 +07:00
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#define RS1(INSN) (((INSN) >> 14) & 0x1f)
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2006-03-13 16:27:34 +07:00
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#define RS2(INSN) (((INSN) >> 0) & 0x1f)
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#define RD(INSN) (((INSN) >> 25) & 0x1f)
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static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
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unsigned int rd, int from_kernel)
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{
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if (rs2 >= 16 || rs1 >= 16 || rd >= 16) {
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if (from_kernel != 0)
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__asm__ __volatile__("flushw");
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else
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flushw_user();
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}
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}
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static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
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{
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sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
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unsigned long value, fp;
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2006-03-13 16:27:34 +07:00
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if (reg < 16)
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return (!reg ? 0 : regs->u_regs[reg]);
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sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
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fp = regs->u_regs[UREG_FP];
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2006-03-13 16:27:34 +07:00
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if (regs->tstate & TSTATE_PRIV) {
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struct reg_window *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
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win = (struct reg_window *)(fp + STACK_BIAS);
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2006-03-13 16:27:34 +07:00
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value = win->locals[reg - 16];
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
} else if (!test_thread_64bit_stack(fp)) {
|
2006-03-13 16:27:34 +07:00
|
|
|
struct reg_window32 __user *win32;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
|
2006-03-13 16:27:34 +07:00
|
|
|
get_user(value, &win32->locals[reg - 16]);
|
|
|
|
|
} else {
|
|
|
|
|
struct reg_window __user *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
win = (struct reg_window __user *)(fp + STACK_BIAS);
|
2006-03-13 16:27:34 +07:00
|
|
|
get_user(value, &win->locals[reg - 16]);
|
|
|
|
|
}
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg,
|
|
|
|
|
struct pt_regs *regs)
|
|
|
|
|
{
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
unsigned long fp = regs->u_regs[UREG_FP];
|
|
|
|
|
|
2006-03-13 16:27:34 +07:00
|
|
|
BUG_ON(reg < 16);
|
|
|
|
|
BUG_ON(regs->tstate & TSTATE_PRIV);
|
|
|
|
|
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
if (!test_thread_64bit_stack(fp)) {
|
2006-03-13 16:27:34 +07:00
|
|
|
struct reg_window32 __user *win32;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
|
2006-03-13 16:27:34 +07:00
|
|
|
return (unsigned long __user *)&win32->locals[reg - 16];
|
|
|
|
|
} else {
|
|
|
|
|
struct reg_window __user *win;
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
win = (struct reg_window __user *)(fp + STACK_BIAS);
|
2006-03-13 16:27:34 +07:00
|
|
|
return &win->locals[reg - 16];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long *__fetch_reg_addr_kern(unsigned int reg,
|
|
|
|
|
struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
BUG_ON(reg >= 16);
|
|
|
|
|
BUG_ON(regs->tstate & TSTATE_PRIV);
|
|
|
|
|
|
|
|
|
|
return ®s->u_regs[reg];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void store_reg(struct pt_regs *regs, unsigned long val, unsigned long rd)
|
|
|
|
|
{
|
|
|
|
|
if (rd < 16) {
|
|
|
|
|
unsigned long *rd_kern = __fetch_reg_addr_kern(rd, regs);
|
|
|
|
|
|
|
|
|
|
*rd_kern = val;
|
|
|
|
|
} else {
|
|
|
|
|
unsigned long __user *rd_user = __fetch_reg_addr_user(rd, regs);
|
|
|
|
|
|
sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-27 05:18:37 +07:00
|
|
|
if (!test_thread_64bit_stack(regs->u_regs[UREG_FP]))
|
2006-03-13 16:27:34 +07:00
|
|
|
__put_user((u32)val, (u32 __user *)rd_user);
|
|
|
|
|
else
|
|
|
|
|
__put_user(val, rd_user);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long fpd_regval(struct fpustate *f,
|
|
|
|
|
unsigned int insn_regnum)
|
|
|
|
|
{
|
|
|
|
|
insn_regnum = (((insn_regnum & 1) << 5) |
|
|
|
|
|
(insn_regnum & 0x1e));
|
|
|
|
|
|
|
|
|
|
return *(unsigned long *) &f->regs[insn_regnum];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned long *fpd_regaddr(struct fpustate *f,
|
|
|
|
|
unsigned int insn_regnum)
|
|
|
|
|
{
|
|
|
|
|
insn_regnum = (((insn_regnum & 1) << 5) |
|
|
|
|
|
(insn_regnum & 0x1e));
|
|
|
|
|
|
|
|
|
|
return (unsigned long *) &f->regs[insn_regnum];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned int fps_regval(struct fpustate *f,
|
|
|
|
|
unsigned int insn_regnum)
|
|
|
|
|
{
|
|
|
|
|
return f->regs[insn_regnum];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline unsigned int *fps_regaddr(struct fpustate *f,
|
|
|
|
|
unsigned int insn_regnum)
|
|
|
|
|
{
|
|
|
|
|
return &f->regs[insn_regnum];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct edge_tab {
|
|
|
|
|
u16 left, right;
|
|
|
|
|
};
|
2008-09-12 13:46:40 +07:00
|
|
|
static struct edge_tab edge8_tab[8] = {
|
2006-03-13 16:27:34 +07:00
|
|
|
{ 0xff, 0x80 },
|
|
|
|
|
{ 0x7f, 0xc0 },
|
|
|
|
|
{ 0x3f, 0xe0 },
|
|
|
|
|
{ 0x1f, 0xf0 },
|
|
|
|
|
{ 0x0f, 0xf8 },
|
|
|
|
|
{ 0x07, 0xfc },
|
|
|
|
|
{ 0x03, 0xfe },
|
|
|
|
|
{ 0x01, 0xff },
|
|
|
|
|
};
|
2008-09-12 13:46:40 +07:00
|
|
|
static struct edge_tab edge8_tab_l[8] = {
|
2006-03-13 16:27:34 +07:00
|
|
|
{ 0xff, 0x01 },
|
|
|
|
|
{ 0xfe, 0x03 },
|
|
|
|
|
{ 0xfc, 0x07 },
|
|
|
|
|
{ 0xf8, 0x0f },
|
|
|
|
|
{ 0xf0, 0x1f },
|
|
|
|
|
{ 0xe0, 0x3f },
|
|
|
|
|
{ 0xc0, 0x7f },
|
|
|
|
|
{ 0x80, 0xff },
|
|
|
|
|
};
|
2008-09-12 13:46:40 +07:00
|
|
|
static struct edge_tab edge16_tab[4] = {
|
2006-03-13 16:27:34 +07:00
|
|
|
{ 0xf, 0x8 },
|
|
|
|
|
{ 0x7, 0xc },
|
|
|
|
|
{ 0x3, 0xe },
|
|
|
|
|
{ 0x1, 0xf },
|
|
|
|
|
};
|
2008-09-12 13:46:40 +07:00
|
|
|
static struct edge_tab edge16_tab_l[4] = {
|
2006-03-13 16:27:34 +07:00
|
|
|
{ 0xf, 0x1 },
|
|
|
|
|
{ 0xe, 0x3 },
|
|
|
|
|
{ 0xc, 0x7 },
|
|
|
|
|
{ 0x8, 0xf },
|
|
|
|
|
};
|
2008-09-12 13:46:40 +07:00
|
|
|
static struct edge_tab edge32_tab[2] = {
|
2006-03-13 16:27:34 +07:00
|
|
|
{ 0x3, 0x2 },
|
|
|
|
|
{ 0x1, 0x3 },
|
|
|
|
|
};
|
2008-09-12 13:46:40 +07:00
|
|
|
static struct edge_tab edge32_tab_l[2] = {
|
2006-03-13 16:27:34 +07:00
|
|
|
{ 0x3, 0x1 },
|
|
|
|
|
{ 0x2, 0x3 },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void edge(struct pt_regs *regs, unsigned int insn, unsigned int opf)
|
|
|
|
|
{
|
|
|
|
|
unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val;
|
|
|
|
|
u16 left, right;
|
|
|
|
|
|
|
|
|
|
maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
|
|
|
|
|
orig_rs1 = rs1 = fetch_reg(RS1(insn), regs);
|
|
|
|
|
orig_rs2 = rs2 = fetch_reg(RS2(insn), regs);
|
|
|
|
|
|
|
|
|
|
if (test_thread_flag(TIF_32BIT)) {
|
|
|
|
|
rs1 = rs1 & 0xffffffff;
|
|
|
|
|
rs2 = rs2 & 0xffffffff;
|
|
|
|
|
}
|
|
|
|
|
switch (opf) {
|
|
|
|
|
default:
|
|
|
|
|
case EDGE8_OPF:
|
|
|
|
|
case EDGE8N_OPF:
|
|
|
|
|
left = edge8_tab[rs1 & 0x7].left;
|
|
|
|
|
right = edge8_tab[rs2 & 0x7].right;
|
|
|
|
|
break;
|
|
|
|
|
case EDGE8L_OPF:
|
|
|
|
|
case EDGE8LN_OPF:
|
|
|
|
|
left = edge8_tab_l[rs1 & 0x7].left;
|
|
|
|
|
right = edge8_tab_l[rs2 & 0x7].right;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case EDGE16_OPF:
|
|
|
|
|
case EDGE16N_OPF:
|
|
|
|
|
left = edge16_tab[(rs1 >> 1) & 0x3].left;
|
|
|
|
|
right = edge16_tab[(rs2 >> 1) & 0x3].right;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case EDGE16L_OPF:
|
|
|
|
|
case EDGE16LN_OPF:
|
|
|
|
|
left = edge16_tab_l[(rs1 >> 1) & 0x3].left;
|
|
|
|
|
right = edge16_tab_l[(rs2 >> 1) & 0x3].right;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case EDGE32_OPF:
|
|
|
|
|
case EDGE32N_OPF:
|
|
|
|
|
left = edge32_tab[(rs1 >> 2) & 0x1].left;
|
|
|
|
|
right = edge32_tab[(rs2 >> 2) & 0x1].right;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case EDGE32L_OPF:
|
|
|
|
|
case EDGE32LN_OPF:
|
|
|
|
|
left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
|
|
|
|
|
right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
|
|
|
|
|
break;
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
|
|
|
|
|
rd_val = right & left;
|
|
|
|
|
else
|
|
|
|
|
rd_val = left;
|
|
|
|
|
|
|
|
|
|
store_reg(regs, rd_val, RD(insn));
|
|
|
|
|
|
|
|
|
|
switch (opf) {
|
|
|
|
|
case EDGE8_OPF:
|
|
|
|
|
case EDGE8L_OPF:
|
|
|
|
|
case EDGE16_OPF:
|
|
|
|
|
case EDGE16L_OPF:
|
|
|
|
|
case EDGE32_OPF:
|
|
|
|
|
case EDGE32L_OPF: {
|
|
|
|
|
unsigned long ccr, tstate;
|
|
|
|
|
|
|
|
|
|
__asm__ __volatile__("subcc %1, %2, %%g0\n\t"
|
|
|
|
|
"rd %%ccr, %0"
|
|
|
|
|
: "=r" (ccr)
|
|
|
|
|
: "r" (orig_rs1), "r" (orig_rs2)
|
|
|
|
|
: "cc");
|
|
|
|
|
tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
|
|
|
|
|
regs->tstate = tstate | (ccr << 32UL);
|
|
|
|
|
}
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
|
|
|
|
|
{
|
|
|
|
|
unsigned long rs1, rs2, rd_val;
|
|
|
|
|
unsigned int bits, bits_mask;
|
|
|
|
|
|
|
|
|
|
maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
|
|
|
|
|
rs1 = fetch_reg(RS1(insn), regs);
|
|
|
|
|
rs2 = fetch_reg(RS2(insn), regs);
|
|
|
|
|
|
|
|
|
|
bits = (rs2 > 5 ? 5 : rs2);
|
|
|
|
|
bits_mask = (1UL << bits) - 1UL;
|
|
|
|
|
|
|
|
|
|
rd_val = ((((rs1 >> 11) & 0x3) << 0) |
|
|
|
|
|
(((rs1 >> 33) & 0x3) << 2) |
|
|
|
|
|
(((rs1 >> 55) & 0x1) << 4) |
|
|
|
|
|
(((rs1 >> 13) & 0xf) << 5) |
|
|
|
|
|
(((rs1 >> 35) & 0xf) << 9) |
|
|
|
|
|
(((rs1 >> 56) & 0xf) << 13) |
|
|
|
|
|
(((rs1 >> 17) & bits_mask) << 17) |
|
|
|
|
|
(((rs1 >> 39) & bits_mask) << (17 + bits)) |
|
|
|
|
|
(((rs1 >> 60) & 0xf) << (17 + (2*bits))));
|
|
|
|
|
|
|
|
|
|
switch (opf) {
|
|
|
|
|
case ARRAY16_OPF:
|
|
|
|
|
rd_val <<= 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ARRAY32_OPF:
|
|
|
|
|
rd_val <<= 2;
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
store_reg(regs, rd_val, RD(insn));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void bmask(struct pt_regs *regs, unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
unsigned long rs1, rs2, rd_val, gsr;
|
|
|
|
|
|
|
|
|
|
maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
|
|
|
|
|
rs1 = fetch_reg(RS1(insn), regs);
|
|
|
|
|
rs2 = fetch_reg(RS2(insn), regs);
|
|
|
|
|
rd_val = rs1 + rs2;
|
|
|
|
|
|
|
|
|
|
store_reg(regs, rd_val, RD(insn));
|
|
|
|
|
|
|
|
|
|
gsr = current_thread_info()->gsr[0] & 0xffffffff;
|
|
|
|
|
gsr |= rd_val << 32UL;
|
|
|
|
|
current_thread_info()->gsr[0] = gsr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void bshuffle(struct pt_regs *regs, unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
unsigned long rs1, rs2, rd_val;
|
|
|
|
|
unsigned long bmask, i;
|
|
|
|
|
|
|
|
|
|
bmask = current_thread_info()->gsr[0] >> 32UL;
|
|
|
|
|
|
|
|
|
|
rs1 = fpd_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0UL;
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
unsigned long which = (bmask >> (i * 4)) & 0xf;
|
|
|
|
|
unsigned long byte;
|
|
|
|
|
|
|
|
|
|
if (which < 8)
|
|
|
|
|
byte = (rs1 >> (which * 8)) & 0xff;
|
|
|
|
|
else
|
|
|
|
|
byte = (rs2 >> ((which-8)*8)) & 0xff;
|
|
|
|
|
rd_val |= (byte << (i * 8));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void pdist(struct pt_regs *regs, unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
unsigned long rs1, rs2, *rd, rd_val;
|
|
|
|
|
unsigned long i;
|
|
|
|
|
|
|
|
|
|
rs1 = fpd_regval(f, RS1(insn));
|
2008-12-04 10:36:05 +07:00
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
2006-03-13 16:27:34 +07:00
|
|
|
rd = fpd_regaddr(f, RD(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = *rd;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
s16 s1, s2;
|
|
|
|
|
|
|
|
|
|
s1 = (rs1 >> (56 - (i * 8))) & 0xff;
|
|
|
|
|
s2 = (rs2 >> (56 - (i * 8))) & 0xff;
|
|
|
|
|
|
|
|
|
|
/* Absolute value of difference. */
|
|
|
|
|
s1 -= s2;
|
|
|
|
|
if (s1 < 0)
|
|
|
|
|
s1 = ~s1 + 1;
|
|
|
|
|
|
|
|
|
|
rd_val += s1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*rd = rd_val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void pformat(struct pt_regs *regs, unsigned int insn, unsigned int opf)
|
|
|
|
|
{
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
unsigned long rs1, rs2, gsr, scale, rd_val;
|
|
|
|
|
|
|
|
|
|
gsr = current_thread_info()->gsr[0];
|
|
|
|
|
scale = (gsr >> 3) & (opf == FPACK16_OPF ? 0xf : 0x1f);
|
|
|
|
|
switch (opf) {
|
|
|
|
|
case FPACK16_OPF: {
|
|
|
|
|
unsigned long byte;
|
|
|
|
|
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
for (byte = 0; byte < 4; byte++) {
|
|
|
|
|
unsigned int val;
|
|
|
|
|
s16 src = (rs2 >> (byte * 16UL)) & 0xffffUL;
|
|
|
|
|
int scaled = src << scale;
|
|
|
|
|
int from_fixed = scaled >> 7;
|
|
|
|
|
|
|
|
|
|
val = ((from_fixed < 0) ?
|
|
|
|
|
0 :
|
|
|
|
|
(from_fixed > 255) ?
|
|
|
|
|
255 : from_fixed);
|
|
|
|
|
|
|
|
|
|
rd_val |= (val << (8 * byte));
|
|
|
|
|
}
|
|
|
|
|
*fps_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FPACK32_OPF: {
|
|
|
|
|
unsigned long word;
|
|
|
|
|
|
|
|
|
|
rs1 = fpd_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
rd_val = (rs1 << 8) & ~(0x000000ff000000ffUL);
|
|
|
|
|
for (word = 0; word < 2; word++) {
|
|
|
|
|
unsigned long val;
|
|
|
|
|
s32 src = (rs2 >> (word * 32UL));
|
|
|
|
|
s64 scaled = src << scale;
|
|
|
|
|
s64 from_fixed = scaled >> 23;
|
|
|
|
|
|
|
|
|
|
val = ((from_fixed < 0) ?
|
|
|
|
|
0 :
|
|
|
|
|
(from_fixed > 255) ?
|
|
|
|
|
255 : from_fixed);
|
|
|
|
|
|
|
|
|
|
rd_val |= (val << (32 * word));
|
|
|
|
|
}
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FPACKFIX_OPF: {
|
|
|
|
|
unsigned long word;
|
|
|
|
|
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
for (word = 0; word < 2; word++) {
|
|
|
|
|
long val;
|
|
|
|
|
s32 src = (rs2 >> (word * 32UL));
|
|
|
|
|
s64 scaled = src << scale;
|
|
|
|
|
s64 from_fixed = scaled >> 16;
|
|
|
|
|
|
|
|
|
|
val = ((from_fixed < -32768) ?
|
|
|
|
|
-32768 :
|
|
|
|
|
(from_fixed > 32767) ?
|
|
|
|
|
32767 : from_fixed);
|
|
|
|
|
|
|
|
|
|
rd_val |= ((val & 0xffff) << (word * 16));
|
|
|
|
|
}
|
|
|
|
|
*fps_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FEXPAND_OPF: {
|
|
|
|
|
unsigned long byte;
|
|
|
|
|
|
|
|
|
|
rs2 = fps_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
for (byte = 0; byte < 4; byte++) {
|
|
|
|
|
unsigned long val;
|
|
|
|
|
u8 src = (rs2 >> (byte * 8)) & 0xff;
|
|
|
|
|
|
|
|
|
|
val = src << 4;
|
|
|
|
|
|
|
|
|
|
rd_val |= (val << (byte * 16));
|
|
|
|
|
}
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FPMERGE_OPF: {
|
|
|
|
|
rs1 = fps_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fps_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = (((rs2 & 0x000000ff) << 0) |
|
|
|
|
|
((rs1 & 0x000000ff) << 8) |
|
|
|
|
|
((rs2 & 0x0000ff00) << 8) |
|
|
|
|
|
((rs1 & 0x0000ff00) << 16) |
|
|
|
|
|
((rs2 & 0x00ff0000) << 16) |
|
|
|
|
|
((rs1 & 0x00ff0000) << 24) |
|
|
|
|
|
((rs2 & 0xff000000) << 24) |
|
|
|
|
|
((rs1 & 0xff000000) << 32));
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
|
|
|
|
|
{
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
unsigned long rs1, rs2, rd_val;
|
|
|
|
|
|
|
|
|
|
switch (opf) {
|
|
|
|
|
case FMUL8x16_OPF: {
|
|
|
|
|
unsigned long byte;
|
|
|
|
|
|
|
|
|
|
rs1 = fps_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
for (byte = 0; byte < 4; byte++) {
|
|
|
|
|
u16 src1 = (rs1 >> (byte * 8)) & 0x00ff;
|
|
|
|
|
s16 src2 = (rs2 >> (byte * 16)) & 0xffff;
|
|
|
|
|
u32 prod = src1 * src2;
|
|
|
|
|
u16 scaled = ((prod & 0x00ffff00) >> 8);
|
|
|
|
|
|
|
|
|
|
/* Round up. */
|
|
|
|
|
if (prod & 0x80)
|
|
|
|
|
scaled++;
|
|
|
|
|
rd_val |= ((scaled & 0xffffUL) << (byte * 16UL));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FMUL8x16AU_OPF:
|
|
|
|
|
case FMUL8x16AL_OPF: {
|
|
|
|
|
unsigned long byte;
|
|
|
|
|
s16 src2;
|
|
|
|
|
|
|
|
|
|
rs1 = fps_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fps_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
2009-11-08 15:26:56 +07:00
|
|
|
src2 = rs2 >> (opf == FMUL8x16AU_OPF ? 16 : 0);
|
2006-03-13 16:27:34 +07:00
|
|
|
for (byte = 0; byte < 4; byte++) {
|
|
|
|
|
u16 src1 = (rs1 >> (byte * 8)) & 0x00ff;
|
|
|
|
|
u32 prod = src1 * src2;
|
|
|
|
|
u16 scaled = ((prod & 0x00ffff00) >> 8);
|
|
|
|
|
|
|
|
|
|
/* Round up. */
|
|
|
|
|
if (prod & 0x80)
|
|
|
|
|
scaled++;
|
|
|
|
|
rd_val |= ((scaled & 0xffffUL) << (byte * 16UL));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FMUL8SUx16_OPF:
|
|
|
|
|
case FMUL8ULx16_OPF: {
|
|
|
|
|
unsigned long byte, ushift;
|
|
|
|
|
|
|
|
|
|
rs1 = fpd_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
ushift = (opf == FMUL8SUx16_OPF) ? 8 : 0;
|
|
|
|
|
for (byte = 0; byte < 4; byte++) {
|
|
|
|
|
u16 src1;
|
|
|
|
|
s16 src2;
|
|
|
|
|
u32 prod;
|
|
|
|
|
u16 scaled;
|
|
|
|
|
|
|
|
|
|
src1 = ((rs1 >> ((16 * byte) + ushift)) & 0x00ff);
|
|
|
|
|
src2 = ((rs2 >> (16 * byte)) & 0xffff);
|
|
|
|
|
prod = src1 * src2;
|
|
|
|
|
scaled = ((prod & 0x00ffff00) >> 8);
|
|
|
|
|
|
|
|
|
|
/* Round up. */
|
|
|
|
|
if (prod & 0x80)
|
|
|
|
|
scaled++;
|
|
|
|
|
rd_val |= ((scaled & 0xffffUL) << (byte * 16UL));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case FMULD8SUx16_OPF:
|
|
|
|
|
case FMULD8ULx16_OPF: {
|
|
|
|
|
unsigned long byte, ushift;
|
|
|
|
|
|
|
|
|
|
rs1 = fps_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fps_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
ushift = (opf == FMULD8SUx16_OPF) ? 8 : 0;
|
|
|
|
|
for (byte = 0; byte < 2; byte++) {
|
|
|
|
|
u16 src1;
|
|
|
|
|
s16 src2;
|
|
|
|
|
u32 prod;
|
|
|
|
|
u16 scaled;
|
|
|
|
|
|
|
|
|
|
src1 = ((rs1 >> ((16 * byte) + ushift)) & 0x00ff);
|
|
|
|
|
src2 = ((rs2 >> (16 * byte)) & 0xffff);
|
|
|
|
|
prod = src1 * src2;
|
|
|
|
|
scaled = ((prod & 0x00ffff00) >> 8);
|
|
|
|
|
|
|
|
|
|
/* Round up. */
|
|
|
|
|
if (prod & 0x80)
|
|
|
|
|
scaled++;
|
|
|
|
|
rd_val |= ((scaled & 0xffffUL) <<
|
|
|
|
|
((byte * 32UL) + 7UL));
|
|
|
|
|
}
|
|
|
|
|
*fpd_regaddr(f, RD(insn)) = rd_val;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
|
|
|
|
|
{
|
|
|
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
|
unsigned long rs1, rs2, rd_val, i;
|
|
|
|
|
|
|
|
|
|
rs1 = fpd_regval(f, RS1(insn));
|
|
|
|
|
rs2 = fpd_regval(f, RS2(insn));
|
|
|
|
|
|
|
|
|
|
rd_val = 0;
|
|
|
|
|
|
|
|
|
|
switch (opf) {
|
|
|
|
|
case FCMPGT16_OPF:
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
s16 a = (rs1 >> (i * 16)) & 0xffff;
|
|
|
|
|
s16 b = (rs2 >> (i * 16)) & 0xffff;
|
|
|
|
|
|
|
|
|
|
if (a > b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 8 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPGT32_OPF:
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
2011-10-31 15:05:49 +07:00
|
|
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff;
|
|
|
|
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff;
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
if (a > b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 2 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPLE16_OPF:
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
s16 a = (rs1 >> (i * 16)) & 0xffff;
|
|
|
|
|
s16 b = (rs2 >> (i * 16)) & 0xffff;
|
|
|
|
|
|
|
|
|
|
if (a <= b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 8 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPLE32_OPF:
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
2011-10-31 15:05:49 +07:00
|
|
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff;
|
|
|
|
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff;
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
if (a <= b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 2 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPNE16_OPF:
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
s16 a = (rs1 >> (i * 16)) & 0xffff;
|
|
|
|
|
s16 b = (rs2 >> (i * 16)) & 0xffff;
|
|
|
|
|
|
|
|
|
|
if (a != b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 8 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPNE32_OPF:
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
2011-10-31 15:05:49 +07:00
|
|
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff;
|
|
|
|
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff;
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
if (a != b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 2 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPEQ16_OPF:
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
s16 a = (rs1 >> (i * 16)) & 0xffff;
|
|
|
|
|
s16 b = (rs2 >> (i * 16)) & 0xffff;
|
|
|
|
|
|
|
|
|
|
if (a == b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 8 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case FCMPEQ32_OPF:
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
2011-10-31 15:05:49 +07:00
|
|
|
s32 a = (rs1 >> (i * 32)) & 0xffffffff;
|
|
|
|
|
s32 b = (rs2 >> (i * 32)) & 0xffffffff;
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
if (a == b)
|
2011-10-31 15:05:49 +07:00
|
|
|
rd_val |= 2 >> i;
|
2006-03-13 16:27:34 +07:00
|
|
|
}
|
|
|
|
|
break;
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
maybe_flush_windows(0, 0, RD(insn), 0);
|
|
|
|
|
store_reg(regs, rd_val, RD(insn));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Emulate the VIS instructions which are not implemented in
|
|
|
|
|
* hardware on Niagara.
|
|
|
|
|
*/
|
|
|
|
|
int vis_emul(struct pt_regs *regs, unsigned int insn)
|
|
|
|
|
{
|
|
|
|
|
unsigned long pc = regs->tpc;
|
|
|
|
|
unsigned int opf;
|
|
|
|
|
|
|
|
|
|
BUG_ON(regs->tstate & TSTATE_PRIV);
|
|
|
|
|
|
2011-06-27 19:41:57 +07:00
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
|
2009-12-11 16:07:53 +07:00
|
|
|
|
2006-03-13 16:27:34 +07:00
|
|
|
if (test_thread_flag(TIF_32BIT))
|
|
|
|
|
pc = (u32)pc;
|
|
|
|
|
|
|
|
|
|
if (get_user(insn, (u32 __user *) pc))
|
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
2008-12-05 00:12:57 +07:00
|
|
|
save_and_clear_fpu();
|
|
|
|
|
|
2006-03-13 16:27:34 +07:00
|
|
|
opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT;
|
|
|
|
|
switch (opf) {
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/* Pixel Formatting Instructions. */
|
|
|
|
|
case FPACK16_OPF:
|
|
|
|
|
case FPACK32_OPF:
|
|
|
|
|
case FPACKFIX_OPF:
|
|
|
|
|
case FEXPAND_OPF:
|
|
|
|
|
case FPMERGE_OPF:
|
|
|
|
|
pformat(regs, insn, opf);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Partitioned Multiply Instructions */
|
|
|
|
|
case FMUL8x16_OPF:
|
|
|
|
|
case FMUL8x16AU_OPF:
|
|
|
|
|
case FMUL8x16AL_OPF:
|
|
|
|
|
case FMUL8SUx16_OPF:
|
|
|
|
|
case FMUL8ULx16_OPF:
|
|
|
|
|
case FMULD8SUx16_OPF:
|
|
|
|
|
case FMULD8ULx16_OPF:
|
|
|
|
|
pmul(regs, insn, opf);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Pixel Compare Instructions */
|
|
|
|
|
case FCMPGT16_OPF:
|
|
|
|
|
case FCMPGT32_OPF:
|
|
|
|
|
case FCMPLE16_OPF:
|
|
|
|
|
case FCMPLE32_OPF:
|
|
|
|
|
case FCMPNE16_OPF:
|
|
|
|
|
case FCMPNE32_OPF:
|
|
|
|
|
case FCMPEQ16_OPF:
|
|
|
|
|
case FCMPEQ32_OPF:
|
|
|
|
|
pcmp(regs, insn, opf);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Edge Handling Instructions */
|
|
|
|
|
case EDGE8_OPF:
|
|
|
|
|
case EDGE8N_OPF:
|
|
|
|
|
case EDGE8L_OPF:
|
|
|
|
|
case EDGE8LN_OPF:
|
|
|
|
|
case EDGE16_OPF:
|
|
|
|
|
case EDGE16N_OPF:
|
|
|
|
|
case EDGE16L_OPF:
|
|
|
|
|
case EDGE16LN_OPF:
|
|
|
|
|
case EDGE32_OPF:
|
|
|
|
|
case EDGE32N_OPF:
|
|
|
|
|
case EDGE32L_OPF:
|
|
|
|
|
case EDGE32LN_OPF:
|
|
|
|
|
edge(regs, insn, opf);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Pixel Component Distance */
|
|
|
|
|
case PDIST_OPF:
|
|
|
|
|
pdist(regs, insn);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Three-Dimensional Array Addressing Instructions */
|
|
|
|
|
case ARRAY8_OPF:
|
|
|
|
|
case ARRAY16_OPF:
|
|
|
|
|
case ARRAY32_OPF:
|
|
|
|
|
array(regs, insn, opf);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
/* Byte Mask and Shuffle Instructions */
|
|
|
|
|
case BMASK_OPF:
|
|
|
|
|
bmask(regs, insn);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BSHUFFLE_OPF:
|
|
|
|
|
bshuffle(regs, insn);
|
|
|
|
|
break;
|
2011-06-03 21:45:23 +07:00
|
|
|
}
|
2006-03-13 16:27:34 +07:00
|
|
|
|
|
|
|
|
regs->tpc = regs->tnpc;
|
|
|
|
|
regs->tnpc += 4;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|