2011-01-24 13:21:54 +07:00
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/*
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* OMAP2plus display device setup / initialization.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Senthilvadivu Guruswamy
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* Sumit Semwal
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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2011-07-31 21:52:44 +07:00
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#include <linux/string.h>
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2011-01-24 13:21:54 +07:00
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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2011-12-06 23:50:42 +07:00
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#include <linux/delay.h>
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2011-01-24 13:21:54 +07:00
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2011-05-11 18:05:07 +07:00
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#include <video/omapdss.h>
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2011-01-24 13:21:56 +07:00
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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2011-05-23 19:50:47 +07:00
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#include <plat/omap-pm.h>
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2011-12-06 23:50:42 +07:00
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#include "common.h"
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2011-01-24 13:21:54 +07:00
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2012-02-25 01:34:35 +07:00
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#include "iomap.h"
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2012-01-02 15:32:37 +07:00
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#include "mux.h"
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2011-06-15 19:22:47 +07:00
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#include "control.h"
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2011-10-07 07:04:08 +07:00
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#include "display.h"
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#define DISPC_CONTROL 0x0040
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#define DISPC_CONTROL2 0x0238
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#define DISPC_IRQSTATUS 0x0018
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#define DSS_SYSCONFIG 0x10
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#define DSS_SYSSTATUS 0x14
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#define DSS_CONTROL 0x40
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#define DSS_SDI_CONTROL 0x44
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#define DSS_PLL_CONTROL 0x48
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#define LCD_EN_MASK (0x1 << 0)
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#define DIGIT_EN_MASK (0x1 << 1)
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#define FRAMEDONE_IRQ_SHIFT 0
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#define EVSYNC_EVEN_IRQ_SHIFT 2
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#define EVSYNC_ODD_IRQ_SHIFT 3
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#define FRAMEDONE2_IRQ_SHIFT 22
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#define FRAMEDONETV_IRQ_SHIFT 24
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/*
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* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
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* reset before deciding that something has gone wrong
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*/
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#define FRAMEDONE_IRQ_TIMEOUT 100
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2011-06-15 19:22:47 +07:00
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2011-01-24 13:21:54 +07:00
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static struct platform_device omap_display_device = {
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.name = "omapdss",
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.id = -1,
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.dev = {
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.platform_data = NULL,
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},
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};
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2011-04-18 11:02:13 +07:00
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struct omap_dss_hwmod_data {
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const char *oh_name;
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const char *dev_name;
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const int id;
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};
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static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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};
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static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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2011-08-03 18:00:57 +07:00
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{ "dss_dsi1", "omapdss_dsi", 0 },
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2011-04-18 11:02:13 +07:00
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};
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static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
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{ "dss_core", "omapdss_dss", -1 },
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{ "dss_dispc", "omapdss_dispc", -1 },
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{ "dss_rfbi", "omapdss_rfbi", -1 },
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{ "dss_venc", "omapdss_venc", -1 },
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2011-08-03 18:00:57 +07:00
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{ "dss_dsi1", "omapdss_dsi", 0 },
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{ "dss_dsi2", "omapdss_dsi", 1 },
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2011-04-18 11:02:13 +07:00
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{ "dss_hdmi", "omapdss_hdmi", -1 },
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};
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2012-03-20 10:03:15 +07:00
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static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
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2012-01-02 15:32:37 +07:00
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{
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2012-01-02 15:32:38 +07:00
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u32 reg;
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u16 control_i2c_1;
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2012-01-02 15:32:37 +07:00
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omap_mux_init_signal("hdmi_cec",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("hdmi_ddc_scl",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("hdmi_ddc_sda",
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OMAP_PIN_INPUT_PULLUP);
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2012-01-02 15:32:38 +07:00
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/*
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* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
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* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
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* internal pull up resistor.
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*/
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if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
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control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
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reg = omap4_ctrl_pad_readl(control_i2c_1);
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reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
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OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
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omap4_ctrl_pad_writel(reg, control_i2c_1);
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}
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2012-01-02 15:32:37 +07:00
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}
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2012-03-20 10:03:15 +07:00
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static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
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2011-06-15 19:22:47 +07:00
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{
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u32 enable_mask, enable_shift;
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u32 pipd_mask, pipd_shift;
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u32 reg;
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if (dsi_id == 0) {
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enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
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enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
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pipd_mask = OMAP4_DSI1_PIPD_MASK;
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pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
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} else if (dsi_id == 1) {
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enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
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enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
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pipd_mask = OMAP4_DSI2_PIPD_MASK;
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pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
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} else {
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return -ENODEV;
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}
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reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
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reg &= ~enable_mask;
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reg &= ~pipd_mask;
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reg |= (lanes << enable_shift) & enable_mask;
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reg |= (lanes << pipd_shift) & pipd_mask;
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omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
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return 0;
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}
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2012-02-21 00:43:30 +07:00
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int __init omap_hdmi_init(enum omap_hdmi_flags flags)
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2012-01-02 15:32:37 +07:00
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{
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if (cpu_is_omap44xx())
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2012-01-02 15:32:38 +07:00
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omap4_hdmi_mux_pads(flags);
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2012-01-02 15:32:37 +07:00
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return 0;
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}
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2012-03-20 10:03:15 +07:00
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static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
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2011-06-15 19:21:12 +07:00
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{
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2011-06-15 19:22:47 +07:00
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if (cpu_is_omap44xx())
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return omap4_dsi_mux_pads(dsi_id, lane_mask);
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2011-06-15 19:21:12 +07:00
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return 0;
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}
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2012-03-20 10:03:15 +07:00
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static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
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2011-06-15 19:21:12 +07:00
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{
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2011-06-15 19:22:47 +07:00
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if (cpu_is_omap44xx())
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omap4_dsi_mux_pads(dsi_id, 0);
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2011-06-15 19:21:12 +07:00
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}
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2011-01-24 13:21:54 +07:00
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int __init omap_display_init(struct omap_dss_board_info *board_data)
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{
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int r = 0;
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2011-01-24 13:21:56 +07:00
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struct omap_hwmod *oh;
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2011-07-22 03:48:45 +07:00
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struct platform_device *pdev;
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2011-04-18 11:02:13 +07:00
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int i, oh_count;
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2011-01-24 13:21:56 +07:00
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struct omap_display_platform_data pdata;
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2011-04-18 11:02:13 +07:00
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const struct omap_dss_hwmod_data *curr_dss_hwmod;
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2011-01-24 13:21:56 +07:00
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memset(&pdata, 0, sizeof(pdata));
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2011-04-18 11:02:13 +07:00
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if (cpu_is_omap24xx()) {
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curr_dss_hwmod = omap2_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
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} else if (cpu_is_omap34xx()) {
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curr_dss_hwmod = omap3_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
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} else {
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curr_dss_hwmod = omap4_dss_hwmod_data;
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oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
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}
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2011-01-27 18:17:04 +07:00
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2011-06-15 19:21:12 +07:00
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if (board_data->dsi_enable_pads == NULL)
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board_data->dsi_enable_pads = omap_dsi_enable_pads;
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if (board_data->dsi_disable_pads == NULL)
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board_data->dsi_disable_pads = omap_dsi_disable_pads;
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2011-01-24 13:21:56 +07:00
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pdata.board_data = board_data;
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2011-05-23 19:50:47 +07:00
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pdata.board_data->get_context_loss_count =
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omap_pm_get_dev_context_loss_count;
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2011-01-24 13:21:56 +07:00
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for (i = 0; i < oh_count; i++) {
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2011-04-18 11:02:13 +07:00
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oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
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2011-01-24 13:21:56 +07:00
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if (!oh) {
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2011-04-18 11:02:13 +07:00
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pr_err("Could not look up %s\n",
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curr_dss_hwmod[i].oh_name);
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2011-01-24 13:21:56 +07:00
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return -ENODEV;
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}
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2011-03-01 15:42:13 +07:00
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2011-07-22 03:48:45 +07:00
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pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
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2011-04-18 11:02:13 +07:00
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curr_dss_hwmod[i].id, oh, &pdata,
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2011-01-24 13:21:56 +07:00
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sizeof(struct omap_display_platform_data),
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2011-08-10 20:30:09 +07:00
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NULL, 0, 0);
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2011-01-24 13:21:56 +07:00
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2011-07-22 03:48:45 +07:00
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if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
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2011-04-18 11:02:13 +07:00
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curr_dss_hwmod[i].oh_name))
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2011-01-24 13:21:56 +07:00
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return -ENODEV;
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}
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2011-01-24 13:21:54 +07:00
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omap_display_device.dev.platform_data = board_data;
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r = platform_device_register(&omap_display_device);
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if (r < 0)
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printk(KERN_ERR "Unable to register OMAP-Display device\n");
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return r;
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}
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2011-11-08 17:16:13 +07:00
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2011-10-07 07:04:08 +07:00
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static void dispc_disable_outputs(void)
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{
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u32 v, irq_mask = 0;
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bool lcd_en, digit_en, lcd2_en = false;
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int i;
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struct omap_dss_dispc_dev_attr *da;
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struct omap_hwmod *oh;
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oh = omap_hwmod_lookup("dss_dispc");
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if (!oh) {
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WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
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return;
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}
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if (!oh->dev_attr) {
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pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
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return;
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}
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da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
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/* store value of LCDENABLE and DIGITENABLE bits */
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v = omap_hwmod_read(oh, DISPC_CONTROL);
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lcd_en = v & LCD_EN_MASK;
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digit_en = v & DIGIT_EN_MASK;
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/* store value of LCDENABLE for LCD2 */
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if (da->manager_count > 2) {
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v = omap_hwmod_read(oh, DISPC_CONTROL2);
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lcd2_en = v & LCD_EN_MASK;
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}
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if (!(lcd_en | digit_en | lcd2_en))
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return; /* no managers currently enabled */
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/*
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* If any manager was enabled, we need to disable it before
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* DSS clocks are disabled or DISPC module is reset
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*/
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if (lcd_en)
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irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
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if (digit_en) {
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if (da->has_framedonetv_irq) {
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irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
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} else {
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irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
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1 << EVSYNC_ODD_IRQ_SHIFT;
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}
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}
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if (lcd2_en)
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irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
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/*
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* clear any previous FRAMEDONE, FRAMEDONETV,
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* EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
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*/
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omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
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/* disable LCD and TV managers */
|
|
|
|
v = omap_hwmod_read(oh, DISPC_CONTROL);
|
|
|
|
v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
|
|
|
|
omap_hwmod_write(v, oh, DISPC_CONTROL);
|
|
|
|
|
|
|
|
/* disable LCD2 manager */
|
|
|
|
if (da->manager_count > 2) {
|
|
|
|
v = omap_hwmod_read(oh, DISPC_CONTROL2);
|
|
|
|
v &= ~LCD_EN_MASK;
|
|
|
|
omap_hwmod_write(v, oh, DISPC_CONTROL2);
|
|
|
|
}
|
|
|
|
|
|
|
|
i = 0;
|
|
|
|
while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
|
|
|
|
irq_mask) {
|
|
|
|
i++;
|
|
|
|
if (i > FRAMEDONE_IRQ_TIMEOUT) {
|
|
|
|
pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-08 17:16:13 +07:00
|
|
|
#define MAX_MODULE_SOFTRESET_WAIT 10000
|
|
|
|
int omap_dss_reset(struct omap_hwmod *oh)
|
|
|
|
{
|
|
|
|
struct omap_hwmod_opt_clk *oc;
|
|
|
|
int c = 0;
|
|
|
|
int i, r;
|
|
|
|
|
|
|
|
if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
|
|
|
|
pr_err("dss_core: hwmod data doesn't contain reset data\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
|
|
|
if (oc->_clk)
|
|
|
|
clk_enable(oc->_clk);
|
|
|
|
|
2011-10-07 07:04:08 +07:00
|
|
|
dispc_disable_outputs();
|
|
|
|
|
|
|
|
/* clear SDI registers */
|
|
|
|
if (cpu_is_omap3430()) {
|
|
|
|
omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
|
|
|
|
omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* clear DSS_CONTROL register to switch DSS clock sources to
|
|
|
|
* PRCM clock, if any
|
|
|
|
*/
|
|
|
|
omap_hwmod_write(0x0, oh, DSS_CONTROL);
|
|
|
|
|
2011-11-08 17:16:13 +07:00
|
|
|
omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
|
|
|
|
& SYSS_RESETDONE_MASK),
|
|
|
|
MAX_MODULE_SOFTRESET_WAIT, c);
|
|
|
|
|
|
|
|
if (c == MAX_MODULE_SOFTRESET_WAIT)
|
|
|
|
pr_warning("dss_core: waiting for reset to finish failed\n");
|
|
|
|
else
|
|
|
|
pr_debug("dss_core: softreset done\n");
|
|
|
|
|
|
|
|
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
|
|
|
|
if (oc->_clk)
|
|
|
|
clk_disable(oc->_clk);
|
|
|
|
|
|
|
|
r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|