2005-09-07 23:20:26 +07:00
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/*
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* linux/arch/arm/plat-omap/dmtimer.c
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*
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* OMAP Dual-Mode Timers
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*
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2011-09-20 18:30:17 +07:00
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Tarun Kanti DebBarma <tarun.kanti@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* dmtimer adaptation to platform_driver.
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*
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2005-09-07 23:20:26 +07:00
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* Copyright (C) 2005 Nokia Corporation
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2006-06-27 06:16:12 +07:00
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* OMAP2 support by Juha Yrjola
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* API improvements and OMAP2 clock framework support by Timo Teras
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2005-09-07 23:20:26 +07:00
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*
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2009-05-29 04:16:04 +07:00
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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2005-09-07 23:20:26 +07:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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2011-11-02 08:49:46 +07:00
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#include <linux/module.h>
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2008-09-06 18:10:45 +07:00
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#include <linux/io.h>
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2011-09-20 18:30:19 +07:00
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#include <linux/slab.h>
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2011-09-20 18:30:20 +07:00
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#include <linux/err.h>
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2011-09-20 18:30:21 +07:00
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#include <linux/pm_runtime.h>
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2009-05-29 04:16:04 +07:00
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2011-09-20 18:30:20 +07:00
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#include <plat/dmtimer.h>
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2012-06-06 00:34:56 +07:00
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#include <plat/omap-pm.h>
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2007-06-22 11:48:07 +07:00
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2012-02-25 01:34:35 +07:00
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#include <mach/hardware.h>
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2012-06-06 00:34:51 +07:00
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static u32 omap_reserved_systimers;
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2011-09-20 18:30:19 +07:00
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static LIST_HEAD(omap_timer_list);
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2011-09-20 18:30:20 +07:00
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static DEFINE_SPINLOCK(dm_timer_lock);
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2005-09-07 23:20:26 +07:00
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2011-09-20 18:30:20 +07:00
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/**
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* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
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* @timer: timer pointer over which read operation to perform
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* @reg: lowest byte holds the register offset
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*
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* The posted mode bit is encoded in reg. Note that in posted mode write
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* pending bit must be checked. Otherwise a read of a non completed write
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* will produce an error.
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2008-07-03 16:24:30 +07:00
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*/
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
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2006-06-27 06:16:12 +07:00
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{
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2011-09-17 05:44:20 +07:00
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
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return __omap_dm_timer_read(timer, reg, timer->posted);
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2006-06-27 06:16:12 +07:00
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}
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2005-09-07 23:20:26 +07:00
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2011-09-20 18:30:20 +07:00
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/**
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* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
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* @timer: timer pointer over which write operation is to perform
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* @reg: lowest byte holds the register offset
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* @value: data to write into the register
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*
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* The posted mode bit is encoded in reg. Note that in posted mode the write
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* pending bit must be checked. Otherwise a write on a register which has a
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* pending write will be lost.
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2008-07-03 16:24:30 +07:00
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*/
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
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u32 value)
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2005-09-07 23:20:26 +07:00
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{
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2011-09-17 05:44:20 +07:00
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
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__omap_dm_timer_write(timer, reg, value, timer->posted);
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2005-09-07 23:20:26 +07:00
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}
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2011-09-20 18:30:24 +07:00
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static void omap_timer_restore_context(struct omap_dm_timer *timer)
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{
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2012-03-06 07:11:00 +07:00
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if (timer->revision == 1)
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2011-09-20 18:30:24 +07:00
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__raw_writel(timer->context.tistat, timer->sys_stat);
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__raw_writel(timer->context.tisr, timer->irq_stat);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
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timer->context.twer);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
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timer->context.tcrr);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
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timer->context.tldr);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
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timer->context.tmar);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
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timer->context.tsicr);
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__raw_writel(timer->context.tier, timer->irq_ena);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
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timer->context.tclr);
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}
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2006-06-27 06:16:12 +07:00
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static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
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2005-09-07 23:20:26 +07:00
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{
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2006-06-27 06:16:12 +07:00
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int c;
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2011-09-17 05:44:20 +07:00
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if (!timer->sys_stat)
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return;
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2006-06-27 06:16:12 +07:00
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c = 0;
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2011-09-17 05:44:20 +07:00
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while (!(__raw_readl(timer->sys_stat) & 1)) {
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2006-06-27 06:16:12 +07:00
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c++;
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if (c > 100000) {
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printk(KERN_ERR "Timer failed to reset\n");
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return;
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}
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}
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2005-09-07 23:20:26 +07:00
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}
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2006-06-27 06:16:12 +07:00
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static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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2011-09-20 18:30:24 +07:00
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omap_dm_timer_enable(timer);
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2011-09-20 18:30:20 +07:00
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if (timer->pdev->id != 1) {
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2006-06-27 06:16:13 +07:00
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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omap_dm_timer_wait_for_reset(timer);
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}
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2008-07-03 16:24:30 +07:00
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2011-09-20 18:30:20 +07:00
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__omap_dm_timer_reset(timer, 0, 0);
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2011-09-20 18:30:24 +07:00
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omap_dm_timer_disable(timer);
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2008-07-03 16:24:30 +07:00
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timer->posted = 1;
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2006-06-27 06:16:12 +07:00
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}
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2011-09-20 18:30:20 +07:00
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int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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2006-06-27 06:16:12 +07:00
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{
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2011-09-20 18:30:20 +07:00
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int ret;
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timer->fclk = clk_get(&timer->pdev->dev, "fck");
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if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
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timer->fclk = NULL;
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dev_err(&timer->pdev->dev, ": No fclk handle.\n");
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return -EINVAL;
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}
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2012-06-06 00:34:57 +07:00
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if (timer->capability & OMAP_TIMER_NEEDS_RESET)
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2011-09-20 18:30:20 +07:00
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omap_dm_timer_reset(timer);
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ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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timer->posted = 1;
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return ret;
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2006-06-27 06:16:12 +07:00
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}
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2012-06-06 00:34:51 +07:00
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static inline u32 omap_dm_timer_reserved_systimer(int id)
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{
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return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
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}
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int omap_dm_timer_reserve_systimer(int id)
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{
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if (omap_dm_timer_reserved_systimer(id))
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return -ENODEV;
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omap_reserved_systimers |= (1 << (id - 1));
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return 0;
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}
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2006-06-27 06:16:12 +07:00
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struct omap_dm_timer *omap_dm_timer_request(void)
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{
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2011-09-20 18:30:20 +07:00
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struct omap_dm_timer *timer = NULL, *t;
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2006-06-27 06:16:12 +07:00
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unsigned long flags;
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2011-09-20 18:30:20 +07:00
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int ret = 0;
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2006-06-27 06:16:12 +07:00
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spin_lock_irqsave(&dm_timer_lock, flags);
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2011-09-20 18:30:20 +07:00
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list_for_each_entry(t, &omap_timer_list, node) {
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if (t->reserved)
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2006-06-27 06:16:12 +07:00
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continue;
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2011-09-20 18:30:20 +07:00
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timer = t;
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2006-06-27 06:16:23 +07:00
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timer->reserved = 1;
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2006-06-27 06:16:12 +07:00
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break;
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}
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2011-09-20 18:30:20 +07:00
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if (timer) {
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ret = omap_dm_timer_prepare(timer);
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if (ret) {
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timer->reserved = 0;
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timer = NULL;
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}
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}
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2006-06-27 06:16:12 +07:00
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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2011-09-20 18:30:20 +07:00
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if (!timer)
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pr_debug("%s: timer request failed!\n", __func__);
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2006-06-27 06:16:23 +07:00
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2006-06-27 06:16:12 +07:00
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return timer;
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}
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2009-03-24 08:07:46 +07:00
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EXPORT_SYMBOL_GPL(omap_dm_timer_request);
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2006-06-27 06:16:12 +07:00
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struct omap_dm_timer *omap_dm_timer_request_specific(int id)
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2005-09-07 23:20:26 +07:00
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{
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2011-09-20 18:30:20 +07:00
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struct omap_dm_timer *timer = NULL, *t;
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2006-06-27 06:16:12 +07:00
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unsigned long flags;
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2011-09-20 18:30:20 +07:00
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int ret = 0;
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2005-09-07 23:20:26 +07:00
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2006-06-27 06:16:12 +07:00
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spin_lock_irqsave(&dm_timer_lock, flags);
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2011-09-20 18:30:20 +07:00
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list_for_each_entry(t, &omap_timer_list, node) {
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if (t->pdev->id == id && !t->reserved) {
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timer = t;
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timer->reserved = 1;
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break;
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}
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2006-06-27 06:16:12 +07:00
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}
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2005-09-07 23:20:26 +07:00
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2011-09-20 18:30:20 +07:00
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if (timer) {
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ret = omap_dm_timer_prepare(timer);
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if (ret) {
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timer->reserved = 0;
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timer = NULL;
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}
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}
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2006-06-27 06:16:12 +07:00
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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2011-09-20 18:30:20 +07:00
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if (!timer)
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pr_debug("%s: timer%d request failed!\n", __func__, id);
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2006-06-27 06:16:23 +07:00
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2006-06-27 06:16:12 +07:00
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return timer;
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2005-09-07 23:20:26 +07:00
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}
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2009-03-24 08:07:46 +07:00
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EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
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2005-09-07 23:20:26 +07:00
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2011-09-20 18:30:26 +07:00
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int omap_dm_timer_free(struct omap_dm_timer *timer)
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2006-06-27 06:16:12 +07:00
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{
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2011-09-20 18:30:26 +07:00
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if (unlikely(!timer))
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return -EINVAL;
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2011-09-20 18:30:20 +07:00
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clk_put(timer->fclk);
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2006-09-25 16:41:35 +07:00
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2006-06-27 06:16:12 +07:00
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WARN_ON(!timer->reserved);
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timer->reserved = 0;
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2011-09-20 18:30:26 +07:00
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return 0;
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2006-06-27 06:16:12 +07:00
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}
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2009-03-24 08:07:46 +07:00
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EXPORT_SYMBOL_GPL(omap_dm_timer_free);
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2006-06-27 06:16:12 +07:00
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2006-09-25 16:41:42 +07:00
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void omap_dm_timer_enable(struct omap_dm_timer *timer)
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{
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2011-09-20 18:30:21 +07:00
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pm_runtime_get_sync(&timer->pdev->dev);
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2006-09-25 16:41:42 +07:00
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}
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2009-03-24 08:07:46 +07:00
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EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
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2006-09-25 16:41:42 +07:00
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void omap_dm_timer_disable(struct omap_dm_timer *timer)
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{
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2011-09-20 18:30:21 +07:00
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pm_runtime_put(&timer->pdev->dev);
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2006-09-25 16:41:42 +07:00
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}
|
2009-03-24 08:07:46 +07:00
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EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
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2006-09-25 16:41:42 +07:00
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2006-06-27 06:16:12 +07:00
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
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{
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2011-09-20 18:30:26 +07:00
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if (timer)
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return timer->irq;
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return -EINVAL;
|
2006-06-27 06:16:12 +07:00
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}
|
2009-03-24 08:07:46 +07:00
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EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
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2006-06-27 06:16:12 +07:00
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#if defined(CONFIG_ARCH_OMAP1)
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|
2006-04-02 23:46:21 +07:00
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/**
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* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
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* @inputmask: current value of idlect mask
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*/
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
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{
|
2011-09-20 18:30:20 +07:00
|
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int i = 0;
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struct omap_dm_timer *timer = NULL;
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unsigned long flags;
|
2006-04-02 23:46:21 +07:00
|
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|
|
/* If ARMXOR cannot be idled this function call is unnecessary */
|
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|
if (!(inputmask & (1 << 1)))
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|
return inputmask;
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|
|
/* If any active timer is using ARMXOR return modified mask */
|
2011-09-20 18:30:20 +07:00
|
|
|
spin_lock_irqsave(&dm_timer_lock, flags);
|
|
|
|
list_for_each_entry(timer, &omap_timer_list, node) {
|
2006-06-27 06:16:12 +07:00
|
|
|
u32 l;
|
|
|
|
|
2011-09-20 18:30:20 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
2006-06-27 06:16:12 +07:00
|
|
|
if (l & OMAP_TIMER_CTRL_ST) {
|
|
|
|
if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
|
2006-04-02 23:46:21 +07:00
|
|
|
inputmask &= ~(1 << 1);
|
|
|
|
else
|
|
|
|
inputmask &= ~(1 << 2);
|
|
|
|
}
|
2011-09-20 18:30:20 +07:00
|
|
|
i++;
|
2006-06-27 06:16:12 +07:00
|
|
|
}
|
2011-09-20 18:30:20 +07:00
|
|
|
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
2006-04-02 23:46:21 +07:00
|
|
|
|
|
|
|
return inputmask;
|
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
|
2006-04-02 23:46:21 +07:00
|
|
|
|
2010-02-13 03:26:48 +07:00
|
|
|
#else
|
2006-04-02 23:46:21 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:26 +07:00
|
|
|
if (timer)
|
|
|
|
return timer->fclk;
|
|
|
|
return NULL;
|
2006-06-27 06:16:12 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
|
|
|
|
{
|
|
|
|
BUG();
|
2006-12-07 08:14:00 +07:00
|
|
|
|
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
#endif
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_trigger(struct omap_dm_timer *timer)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
|
|
pr_err("%s: timer not available or enabled.\n", __func__);
|
|
|
|
return -EINVAL;
|
2011-09-20 18:30:24 +07:00
|
|
|
}
|
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_start(struct omap_dm_timer *timer)
|
2006-06-27 06:16:12 +07:00
|
|
|
{
|
|
|
|
u32 l;
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
|
|
|
|
2012-06-06 00:34:55 +07:00
|
|
|
if (!(timer->capability & OMAP_TIMER_ALWON)) {
|
2012-06-06 00:34:56 +07:00
|
|
|
if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
|
|
|
|
timer->ctx_loss_count)
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_timer_restore_context(timer);
|
|
|
|
}
|
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
|
|
if (!(l & OMAP_TIMER_CTRL_ST)) {
|
|
|
|
l |= OMAP_TIMER_CTRL_ST;
|
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
|
|
|
}
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tclr = l;
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2006-06-27 06:16:12 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_start);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_stop(struct omap_dm_timer *timer)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-03-30 05:54:48 +07:00
|
|
|
unsigned long rate = 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2012-06-06 00:34:57 +07:00
|
|
|
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
|
2011-09-20 18:30:20 +07:00
|
|
|
rate = clk_get_rate(timer->fclk);
|
2011-03-30 05:54:48 +07:00
|
|
|
|
2011-09-17 05:44:20 +07:00
|
|
|
__omap_dm_timer_stop(timer, timer->posted, rate);
|
2011-09-20 18:30:26 +07:00
|
|
|
|
2012-06-06 00:34:56 +07:00
|
|
|
if (!(timer->capability & OMAP_TIMER_ALWON))
|
2012-03-06 07:11:00 +07:00
|
|
|
timer->ctx_loss_count =
|
2012-06-06 00:34:56 +07:00
|
|
|
omap_pm_get_dev_context_loss_count(&timer->pdev->dev);
|
2012-03-06 07:11:00 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Since the register values are computed and written within
|
|
|
|
* __omap_dm_timer_stop, we need to use read to retrieve the
|
|
|
|
* context.
|
|
|
|
*/
|
|
|
|
timer->context.tclr =
|
|
|
|
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
|
|
timer->context.tisr = __raw_readl(timer->irq_stat);
|
|
|
|
omap_dm_timer_disable(timer);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
2009-04-24 10:11:10 +07:00
|
|
|
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:20 +07:00
|
|
|
int ret;
|
2011-09-20 18:30:26 +07:00
|
|
|
struct dmtimer_platform_data *pdata;
|
|
|
|
|
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pdata = timer->pdev->dev.platform_data;
|
2011-09-20 18:30:20 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
if (source < 0 || source >= 3)
|
OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
2009-04-24 10:11:10 +07:00
|
|
|
return -EINVAL;
|
2006-06-27 06:16:12 +07:00
|
|
|
|
2011-09-20 18:30:20 +07:00
|
|
|
ret = pdata->set_timer_src(timer->pdev, source);
|
|
|
|
|
|
|
|
return ret;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
|
2006-06-27 06:16:12 +07:00
|
|
|
unsigned int load)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
|
|
|
u32 l;
|
2006-06-27 06:16:12 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
2005-09-07 23:20:26 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
2006-06-27 06:16:12 +07:00
|
|
|
if (autoreload)
|
|
|
|
l |= OMAP_TIMER_CTRL_AR;
|
|
|
|
else
|
|
|
|
l &= ~OMAP_TIMER_CTRL_AR;
|
2005-09-07 23:20:26 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
2006-06-27 06:16:12 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
|
2008-07-03 16:24:30 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
|
2011-09-20 18:30:24 +07:00
|
|
|
/* Save the context */
|
|
|
|
timer->context.tclr = l;
|
|
|
|
timer->context.tldr = load;
|
|
|
|
omap_dm_timer_disable(timer);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2008-07-03 16:24:30 +07:00
|
|
|
/* Optimized set_load which removes costly spin wait in timer_start */
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
|
2008-07-03 16:24:30 +07:00
|
|
|
unsigned int load)
|
|
|
|
{
|
|
|
|
u32 l;
|
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
|
|
|
|
2012-06-06 00:34:55 +07:00
|
|
|
if (!(timer->capability & OMAP_TIMER_ALWON)) {
|
2012-06-06 00:34:56 +07:00
|
|
|
if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
|
|
|
|
timer->ctx_loss_count)
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_timer_restore_context(timer);
|
|
|
|
}
|
|
|
|
|
2008-07-03 16:24:30 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
2008-12-11 08:36:34 +07:00
|
|
|
if (autoreload) {
|
2008-07-03 16:24:30 +07:00
|
|
|
l |= OMAP_TIMER_CTRL_AR;
|
2008-12-11 08:36:34 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
|
|
|
|
} else {
|
2008-07-03 16:24:30 +07:00
|
|
|
l &= ~OMAP_TIMER_CTRL_AR;
|
2008-12-11 08:36:34 +07:00
|
|
|
}
|
2008-07-03 16:24:30 +07:00
|
|
|
l |= OMAP_TIMER_CTRL_ST;
|
|
|
|
|
2011-09-17 05:44:20 +07:00
|
|
|
__omap_dm_timer_load_start(timer, l, load, timer->posted);
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tclr = l;
|
|
|
|
timer->context.tldr = load;
|
|
|
|
timer->context.tcrr = load;
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2008-07-03 16:24:30 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
|
2008-07-03 16:24:30 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
|
2006-06-27 06:16:12 +07:00
|
|
|
unsigned int match)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
|
|
|
u32 l;
|
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
2005-09-07 23:20:26 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
2006-06-27 06:16:23 +07:00
|
|
|
if (enable)
|
2006-06-27 06:16:12 +07:00
|
|
|
l |= OMAP_TIMER_CTRL_CE;
|
|
|
|
else
|
|
|
|
l &= ~OMAP_TIMER_CTRL_CE;
|
2005-09-07 23:20:26 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
2006-06-27 06:16:12 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tclr = l;
|
|
|
|
timer->context.tmar = match;
|
|
|
|
omap_dm_timer_disable(timer);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
|
2006-06-27 06:16:12 +07:00
|
|
|
int toggle, int trigger)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
|
|
|
u32 l;
|
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
2005-09-07 23:20:26 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
2006-06-27 06:16:12 +07:00
|
|
|
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
|
|
|
|
OMAP_TIMER_CTRL_PT | (0x03 << 10));
|
|
|
|
if (def_on)
|
|
|
|
l |= OMAP_TIMER_CTRL_SCPWM;
|
|
|
|
if (toggle)
|
|
|
|
l |= OMAP_TIMER_CTRL_PT;
|
|
|
|
l |= trigger << 10;
|
2005-09-07 23:20:26 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tclr = l;
|
|
|
|
omap_dm_timer_disable(timer);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
|
|
|
u32 l;
|
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
2005-09-07 23:20:26 +07:00
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
2006-06-27 06:16:12 +07:00
|
|
|
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
|
|
|
|
if (prescaler >= 0x00 && prescaler <= 0x07) {
|
|
|
|
l |= OMAP_TIMER_CTRL_PRE;
|
|
|
|
l |= prescaler << 2;
|
|
|
|
}
|
2005-09-07 23:20:26 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tclr = l;
|
|
|
|
omap_dm_timer_disable(timer);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
|
2006-06-27 06:16:12 +07:00
|
|
|
unsigned int value)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-20 18:30:24 +07:00
|
|
|
omap_dm_timer_enable(timer);
|
2011-09-17 05:44:20 +07:00
|
|
|
__omap_dm_timer_int_enable(timer, value);
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tier = value;
|
|
|
|
timer->context.twer = value;
|
|
|
|
omap_dm_timer_disable(timer);
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2006-09-25 16:41:35 +07:00
|
|
|
unsigned int l;
|
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
|
|
pr_err("%s: timer not available or enabled.\n", __func__);
|
2011-09-20 18:30:24 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-17 05:44:20 +07:00
|
|
|
l = __raw_readl(timer->irq_stat);
|
2006-09-25 16:41:35 +07:00
|
|
|
|
|
|
|
return l;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2011-09-17 05:44:20 +07:00
|
|
|
__omap_dm_timer_write_status(timer, value);
|
2011-09-20 18:30:24 +07:00
|
|
|
/* Save the context */
|
|
|
|
timer->context.tisr = value;
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
|
|
pr_err("%s: timer not iavailable or enabled.\n", __func__);
|
2011-09-20 18:30:24 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-17 05:44:20 +07:00
|
|
|
return __omap_dm_timer_read_counter(timer, timer->posted);
|
2005-09-07 23:20:26 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:26 +07:00
|
|
|
int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
|
2006-06-27 06:16:23 +07:00
|
|
|
{
|
2011-09-20 18:30:26 +07:00
|
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
|
|
pr_err("%s: timer not available or enabled.\n", __func__);
|
|
|
|
return -EINVAL;
|
2011-09-20 18:30:24 +07:00
|
|
|
}
|
|
|
|
|
2006-09-25 16:41:35 +07:00
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
|
2011-09-20 18:30:24 +07:00
|
|
|
|
|
|
|
/* Save the context */
|
|
|
|
timer->context.tcrr = value;
|
2011-09-20 18:30:26 +07:00
|
|
|
return 0;
|
2006-06-27 06:16:23 +07:00
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
|
2006-06-27 06:16:23 +07:00
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
int omap_dm_timers_active(void)
|
2005-09-07 23:20:26 +07:00
|
|
|
{
|
2011-09-20 18:30:20 +07:00
|
|
|
struct omap_dm_timer *timer;
|
2006-09-25 16:41:42 +07:00
|
|
|
|
2011-09-20 18:30:20 +07:00
|
|
|
list_for_each_entry(timer, &omap_timer_list, node) {
|
2011-09-20 18:30:21 +07:00
|
|
|
if (!timer->reserved)
|
2006-09-25 16:41:42 +07:00
|
|
|
continue;
|
|
|
|
|
2006-06-27 06:16:12 +07:00
|
|
|
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
|
2006-09-25 16:41:35 +07:00
|
|
|
OMAP_TIMER_CTRL_ST) {
|
2006-06-27 06:16:12 +07:00
|
|
|
return 1;
|
2006-09-25 16:41:35 +07:00
|
|
|
}
|
2006-06-27 06:16:12 +07:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2009-03-24 08:07:46 +07:00
|
|
|
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
|
2005-09-07 23:20:26 +07:00
|
|
|
|
2011-09-20 18:30:19 +07:00
|
|
|
/**
|
|
|
|
* omap_dm_timer_probe - probe function called for every registered device
|
|
|
|
* @pdev: pointer to current timer platform device
|
|
|
|
*
|
|
|
|
* Called by driver framework at the end of device registration for all
|
|
|
|
* timer devices.
|
|
|
|
*/
|
|
|
|
static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
unsigned long flags;
|
|
|
|
struct omap_dm_timer *timer;
|
|
|
|
struct resource *mem, *irq, *ioarea;
|
|
|
|
struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
|
|
|
|
|
|
|
|
if (!pdata) {
|
|
|
|
dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (unlikely(!irq)) {
|
|
|
|
dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (unlikely(!mem)) {
|
|
|
|
dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
ioarea = request_mem_region(mem->start, resource_size(mem),
|
|
|
|
pdev->name);
|
|
|
|
if (!ioarea) {
|
|
|
|
dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
|
|
|
|
if (!timer) {
|
|
|
|
dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
|
|
|
|
__func__);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_free_ioregion;
|
|
|
|
}
|
|
|
|
|
|
|
|
timer->io_base = ioremap(mem->start, resource_size(mem));
|
|
|
|
if (!timer->io_base) {
|
|
|
|
dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_free_mem;
|
|
|
|
}
|
|
|
|
|
|
|
|
timer->id = pdev->id;
|
|
|
|
timer->irq = irq->start;
|
2012-06-06 00:34:51 +07:00
|
|
|
timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
|
2011-09-20 18:30:19 +07:00
|
|
|
timer->pdev = pdev;
|
ARM: OMAP: Add DMTIMER capability variable to represent timer features
Although the OMAP timers share a common hardware design, there are some
differences between the timer instances in a given device. For example, a timer
maybe in a power domain that can be powered-of, so can lose its logic state and
need restoring where as another may be in power domain that is always be on.
Another example, is a timer may support different clock sources to drive the
timer. This information is passed to the dmtimer via the following platform data
structure.
struct dmtimer_platform_data {
int (*set_timer_src)(struct platform_device *pdev, int source);
int timer_ip_version;
u32 needs_manual_reset:1;
bool loses_context;
int (*get_context_loss_count)(struct device *dev);
};
The above structure uses multiple variables to represent the timer features.
HWMOD also stores the timer capabilities using a bit-mask that represents the
features supported. By using the same format for representing the timer
features in the platform data as used by HWMOD, we can ...
1. Use the flags defined in the plat/dmtimer.h to represent the features
supported.
2. For devices using HWMOD, we can retrieve the features supported from HWMOD.
3. Eventually, simplify the platform data structure to be ...
struct dmtimer_platform_data {
int (*set_timer_src)(struct platform_device *pdev, int source);
u32 timer_capability;
}
Another benefit from doing this, is that it will simplify the migration of the
dmtimer driver to device-tree. For example, in the current OMAP2+ timer code the
"loses_context" variable is configured at runtime by calling an architecture
specific function. For device tree this creates a problem, because we would need
to call the architecture specific function from within the dmtimer driver.
However, such attributes do not need to be queried at runtime and we can look up
the attributes via HWMOD or device-tree.
This changes a new "capability" variable to the platform data and timer
structure so we can start removing and simplifying the platform data structure.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2012-06-06 00:34:52 +07:00
|
|
|
timer->capability = pdata->timer_capability;
|
2011-09-20 18:30:19 +07:00
|
|
|
|
2011-09-20 18:30:21 +07:00
|
|
|
/* Skip pm_runtime_enable for OMAP1 */
|
2012-06-06 00:34:57 +07:00
|
|
|
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
|
2011-09-20 18:30:21 +07:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
pm_runtime_irq_safe(&pdev->dev);
|
|
|
|
}
|
|
|
|
|
2011-09-22 06:38:51 +07:00
|
|
|
if (!timer->reserved) {
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
__omap_dm_timer_init_regs(timer);
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
}
|
|
|
|
|
2011-09-20 18:30:19 +07:00
|
|
|
/* add the timer element to the list */
|
|
|
|
spin_lock_irqsave(&dm_timer_lock, flags);
|
|
|
|
list_add_tail(&timer->node, &omap_timer_list);
|
|
|
|
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
|
|
|
|
|
|
|
dev_dbg(&pdev->dev, "Device Probed.\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_free_mem:
|
|
|
|
kfree(timer);
|
|
|
|
|
|
|
|
err_free_ioregion:
|
|
|
|
release_mem_region(mem->start, resource_size(mem));
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* omap_dm_timer_remove - cleanup a registered timer device
|
|
|
|
* @pdev: pointer to current timer platform device
|
|
|
|
*
|
|
|
|
* Called by driver framework whenever a timer device is unregistered.
|
|
|
|
* In addition to freeing platform resources it also deletes the timer
|
|
|
|
* entry from the local list.
|
|
|
|
*/
|
|
|
|
static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct omap_dm_timer *timer;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret = -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dm_timer_lock, flags);
|
|
|
|
list_for_each_entry(timer, &omap_timer_list, node)
|
|
|
|
if (timer->pdev->id == pdev->id) {
|
|
|
|
list_del(&timer->node);
|
|
|
|
kfree(timer);
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver omap_dm_timer_driver = {
|
|
|
|
.probe = omap_dm_timer_probe,
|
2011-10-01 23:42:47 +07:00
|
|
|
.remove = __devexit_p(omap_dm_timer_remove),
|
2011-09-20 18:30:19 +07:00
|
|
|
.driver = {
|
|
|
|
.name = "omap_timer",
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init omap_dm_timer_driver_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&omap_dm_timer_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit omap_dm_timer_driver_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&omap_dm_timer_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
early_platform_init("earlytimer", &omap_dm_timer_driver);
|
|
|
|
module_init(omap_dm_timer_driver_init);
|
|
|
|
module_exit(omap_dm_timer_driver_exit);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
|
|
MODULE_AUTHOR("Texas Instruments Inc");
|