2019-05-30 06:57:50 +07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
2009-10-15 13:03:56 +07:00
|
|
|
/*
|
|
|
|
|
* ALSA SoC Texas Instruments TLV320DAC33 codec driver
|
|
|
|
|
*
|
2011-05-03 22:11:36 +07:00
|
|
|
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
|
2009-10-15 13:03:56 +07:00
|
|
|
*
|
|
|
|
|
* Copyright: (C) 2009 Nokia Corporation
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
|
#include <linux/moduleparam.h>
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
|
#include <linux/delay.h>
|
|
|
|
|
#include <linux/pm.h>
|
|
|
|
|
#include <linux/i2c.h>
|
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
|
#include <linux/gpio.h>
|
2009-12-04 18:49:10 +07:00
|
|
|
#include <linux/regulator/consumer.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
|
|
|
#include <linux/slab.h>
|
2009-10-15 13:03:56 +07:00
|
|
|
#include <sound/core.h>
|
|
|
|
|
#include <sound/pcm.h>
|
|
|
|
|
#include <sound/pcm_params.h>
|
|
|
|
|
#include <sound/soc.h>
|
|
|
|
|
#include <sound/initval.h>
|
|
|
|
|
#include <sound/tlv.h>
|
|
|
|
|
|
|
|
|
|
#include <sound/tlv320dac33-plat.h>
|
|
|
|
|
#include "tlv320dac33.h"
|
|
|
|
|
|
2010-12-22 15:45:17 +07:00
|
|
|
/*
|
|
|
|
|
* The internal FIFO is 24576 bytes long
|
|
|
|
|
* It can be configured to hold 16bit or 24bit samples
|
|
|
|
|
* In 16bit configuration the FIFO can hold 6144 stereo samples
|
|
|
|
|
* In 24bit configuration the FIFO can hold 4096 stereo samples
|
|
|
|
|
*/
|
|
|
|
|
#define DAC33_FIFO_SIZE_16BIT 6144
|
|
|
|
|
#define DAC33_FIFO_SIZE_24BIT 4096
|
|
|
|
|
#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
|
2010-04-23 14:09:59 +07:00
|
|
|
|
2010-04-23 14:10:00 +07:00
|
|
|
#define BURST_BASEFREQ_HZ 49152000
|
|
|
|
|
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
#define SAMPLES_TO_US(rate, samples) \
|
2011-09-29 11:09:57 +07:00
|
|
|
(1000000000 / (((rate) * 1000) / (samples)))
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
|
|
|
|
#define US_TO_SAMPLES(rate, us) \
|
2011-09-29 11:09:57 +07:00
|
|
|
((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
2010-07-28 19:26:55 +07:00
|
|
|
#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
|
2011-09-29 11:09:57 +07:00
|
|
|
(((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
|
2010-07-28 19:26:55 +07:00
|
|
|
|
2012-04-04 21:58:16 +07:00
|
|
|
static void dac33_calculate_times(struct snd_pcm_substream *substream,
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component);
|
2012-04-04 21:58:16 +07:00
|
|
|
static int dac33_prepare_chip(struct snd_pcm_substream *substream,
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
enum dac33_state {
|
|
|
|
|
DAC33_IDLE = 0,
|
|
|
|
|
DAC33_PREFILL,
|
|
|
|
|
DAC33_PLAYBACK,
|
|
|
|
|
DAC33_FLUSH,
|
|
|
|
|
};
|
|
|
|
|
|
2009-12-31 15:30:19 +07:00
|
|
|
enum dac33_fifo_modes {
|
|
|
|
|
DAC33_FIFO_BYPASS = 0,
|
|
|
|
|
DAC33_FIFO_MODE1,
|
2009-12-31 15:30:22 +07:00
|
|
|
DAC33_FIFO_MODE7,
|
2009-12-31 15:30:19 +07:00
|
|
|
DAC33_FIFO_LAST_MODE,
|
|
|
|
|
};
|
|
|
|
|
|
2009-12-04 18:49:10 +07:00
|
|
|
#define DAC33_NUM_SUPPLIES 3
|
|
|
|
|
static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
|
|
|
|
|
"AVDD",
|
|
|
|
|
"DVDD",
|
|
|
|
|
"IOVDD",
|
|
|
|
|
};
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
struct tlv320dac33_priv {
|
|
|
|
|
struct mutex mutex;
|
|
|
|
|
struct work_struct work;
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component;
|
2009-12-04 18:49:10 +07:00
|
|
|
struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
|
2010-04-30 18:59:35 +07:00
|
|
|
struct snd_pcm_substream *substream;
|
2009-10-15 13:03:56 +07:00
|
|
|
int power_gpio;
|
|
|
|
|
int chip_power;
|
|
|
|
|
int irq;
|
|
|
|
|
unsigned int refclk;
|
|
|
|
|
|
|
|
|
|
unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
|
2009-12-31 15:30:19 +07:00
|
|
|
enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
|
2010-12-22 15:45:17 +07:00
|
|
|
unsigned int fifo_size; /* Size of the FIFO in samples */
|
2009-10-15 13:03:56 +07:00
|
|
|
unsigned int nsample; /* burst read amount from host */
|
2010-07-28 19:26:54 +07:00
|
|
|
int mode1_latency; /* latency caused by the i2c writes in
|
|
|
|
|
* us */
|
2010-01-20 14:39:36 +07:00
|
|
|
u8 burst_bclkdiv; /* BCLK divider value in burst mode */
|
2017-11-14 08:04:25 +07:00
|
|
|
u8 *reg_cache;
|
2010-04-23 14:10:00 +07:00
|
|
|
unsigned int burst_rate; /* Interface speed in Burst modes */
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-03-11 21:26:22 +07:00
|
|
|
int keep_bclk; /* Keep the BCLK continuously running
|
|
|
|
|
* in FIFO modes */
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
spinlock_t lock;
|
|
|
|
|
unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
|
|
|
|
|
unsigned long long t_stamp2; /* calculate the FIFO caused delay */
|
|
|
|
|
|
|
|
|
|
unsigned int mode1_us_burst; /* Time to burst read n number of
|
|
|
|
|
* samples */
|
|
|
|
|
unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-06-07 14:50:39 +07:00
|
|
|
unsigned int uthr;
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
enum dac33_state state;
|
2017-11-09 07:19:48 +07:00
|
|
|
struct i2c_client *i2c;
|
2009-10-15 13:03:56 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
|
|
|
|
|
0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
|
|
|
|
|
0x00, 0x00, /* 0x38 - 0x39 */
|
|
|
|
|
/* Registers 0x3a - 0x3f are reserved */
|
|
|
|
|
0x00, 0x00, /* 0x3a - 0x3b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
|
|
|
|
|
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
|
|
|
|
|
0x00, 0x80, /* 0x44 - 0x45 */
|
|
|
|
|
/* Registers 0x46 - 0x47 are reserved */
|
|
|
|
|
0x80, 0x80, /* 0x46 - 0x47 */
|
|
|
|
|
|
|
|
|
|
0x80, 0x00, 0x00, /* 0x48 - 0x4a */
|
|
|
|
|
/* Registers 0x4b - 0x7c are reserved */
|
|
|
|
|
0x00, /* 0x4b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
|
|
|
|
|
0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
|
|
|
|
|
0x00, /* 0x7c */
|
|
|
|
|
|
|
|
|
|
0xda, 0x33, 0x03, /* 0x7d - 0x7f */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Register read and write */
|
2018-01-29 11:14:21 +07:00
|
|
|
static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component,
|
2009-10-15 13:03:56 +07:00
|
|
|
unsigned reg)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2017-11-14 08:04:25 +07:00
|
|
|
u8 *cache = dac33->reg_cache;
|
2009-10-15 13:03:56 +07:00
|
|
|
if (reg >= DAC33_CACHEREGNUM)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
return cache[reg];
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static inline void dac33_write_reg_cache(struct snd_soc_component *component,
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 reg, u8 value)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2017-11-14 08:04:25 +07:00
|
|
|
u8 *cache = dac33->reg_cache;
|
2009-10-15 13:03:56 +07:00
|
|
|
if (reg >= DAC33_CACHEREGNUM)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
cache[reg] = value;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_read(struct snd_soc_component *component, unsigned int reg,
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 *value)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2010-10-26 15:45:59 +07:00
|
|
|
int val, ret = 0;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
*value = reg & 0xff;
|
|
|
|
|
|
|
|
|
|
/* If powered off, return the cached value */
|
|
|
|
|
if (dac33->chip_power) {
|
2017-11-09 07:19:48 +07:00
|
|
|
val = i2c_smbus_read_byte_data(dac33->i2c, value[0]);
|
2009-10-15 13:03:56 +07:00
|
|
|
if (val < 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Read failed (%d)\n", val);
|
|
|
|
|
value[0] = dac33_read_reg_cache(component, reg);
|
2010-10-26 15:45:59 +07:00
|
|
|
ret = val;
|
2009-10-15 13:03:56 +07:00
|
|
|
} else {
|
|
|
|
|
value[0] = val;
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write_reg_cache(component, reg, val);
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
} else {
|
2018-01-29 11:14:21 +07:00
|
|
|
value[0] = dac33_read_reg_cache(component, reg);
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2010-10-26 15:45:59 +07:00
|
|
|
return ret;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_write(struct snd_soc_component *component, unsigned int reg,
|
2009-10-15 13:03:56 +07:00
|
|
|
unsigned int value)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 data[2];
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* data is
|
|
|
|
|
* D15..D8 dac33 register offset
|
|
|
|
|
* D7...D0 register data
|
|
|
|
|
*/
|
|
|
|
|
data[0] = reg & 0xff;
|
|
|
|
|
data[1] = value & 0xff;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write_reg_cache(component, data[0], data[1]);
|
2009-10-15 13:03:56 +07:00
|
|
|
if (dac33->chip_power) {
|
2017-11-09 07:19:48 +07:00
|
|
|
ret = i2c_master_send(dac33->i2c, data, 2);
|
2009-10-15 13:03:56 +07:00
|
|
|
if (ret != 2)
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Write failed (%d)\n", ret);
|
2009-10-15 13:03:56 +07:00
|
|
|
else
|
|
|
|
|
ret = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg,
|
2018-01-16 08:59:01 +07:00
|
|
|
unsigned int value)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2018-01-16 08:59:01 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&dac33->mutex);
|
2018-01-29 11:14:21 +07:00
|
|
|
ret = dac33_write(component, reg, value);
|
2018-01-16 08:59:01 +07:00
|
|
|
mutex_unlock(&dac33->mutex);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
#define DAC33_I2C_ADDR_AUTOINC 0x80
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_write16(struct snd_soc_component *component, unsigned int reg,
|
2009-10-15 13:03:56 +07:00
|
|
|
unsigned int value)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 data[3];
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* data is
|
|
|
|
|
* D23..D16 dac33 register offset
|
|
|
|
|
* D15..D8 register data MSB
|
|
|
|
|
* D7...D0 register data LSB
|
|
|
|
|
*/
|
|
|
|
|
data[0] = reg & 0xff;
|
|
|
|
|
data[1] = (value >> 8) & 0xff;
|
|
|
|
|
data[2] = value & 0xff;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write_reg_cache(component, data[0], data[1]);
|
|
|
|
|
dac33_write_reg_cache(component, data[0] + 1, data[2]);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
if (dac33->chip_power) {
|
|
|
|
|
/* We need to set autoincrement mode for 16 bit writes */
|
|
|
|
|
data[0] |= DAC33_I2C_ADDR_AUTOINC;
|
2017-11-09 07:19:48 +07:00
|
|
|
ret = i2c_master_send(dac33->i2c, data, 3);
|
2009-10-15 13:03:56 +07:00
|
|
|
if (ret != 3)
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Write failed (%d)\n", ret);
|
2009-10-15 13:03:56 +07:00
|
|
|
else
|
|
|
|
|
ret = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static void dac33_init_chip(struct snd_soc_component *component)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-04-30 18:59:33 +07:00
|
|
|
if (unlikely(!dac33->chip_power))
|
2009-10-15 13:03:56 +07:00
|
|
|
return;
|
|
|
|
|
|
2010-04-30 18:59:33 +07:00
|
|
|
/* A : DAC sample rate Fsref/1.5 */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
|
2010-04-30 18:59:33 +07:00
|
|
|
/* B : DAC src=normal, not muted */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
|
2010-04-30 18:59:33 +07:00
|
|
|
DAC33_DACSRCL_LEFT);
|
|
|
|
|
/* C : (defaults) */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_DAC_CTRL_C, 0x00);
|
2010-04-30 18:59:33 +07:00
|
|
|
|
|
|
|
|
/* 73 : volume soft stepping control,
|
|
|
|
|
clock source = internal osc (?) */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
|
2010-04-30 18:59:33 +07:00
|
|
|
|
|
|
|
|
/* Restore only selected registers (gains mostly) */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL));
|
|
|
|
|
dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL));
|
|
|
|
|
|
|
|
|
|
dac33_write(component, DAC33_LINEL_TO_LLO_VOL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL));
|
|
|
|
|
dac33_write(component, DAC33_LINER_TO_RLO_VOL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL));
|
|
|
|
|
|
|
|
|
|
dac33_write(component, DAC33_OUT_AMP_CTRL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL));
|
|
|
|
|
|
|
|
|
|
dac33_write(component, DAC33_LDAC_PWR_CTRL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL));
|
|
|
|
|
dac33_write(component, DAC33_RDAC_PWR_CTRL,
|
|
|
|
|
dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL));
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static inline int dac33_read_id(struct snd_soc_component *component)
|
2010-04-30 18:59:34 +07:00
|
|
|
{
|
2010-10-26 15:45:59 +07:00
|
|
|
int i, ret = 0;
|
2010-04-30 18:59:34 +07:00
|
|
|
u8 reg;
|
|
|
|
|
|
2010-10-26 15:45:59 +07:00
|
|
|
for (i = 0; i < 3; i++) {
|
2018-01-29 11:14:21 +07:00
|
|
|
ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, ®);
|
2010-10-26 15:45:59 +07:00
|
|
|
if (ret < 0)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static inline void dac33_soft_power(struct snd_soc_component *component, int power)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
|
|
|
|
u8 reg;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
|
2009-10-15 13:03:56 +07:00
|
|
|
if (power)
|
|
|
|
|
reg |= DAC33_PDNALLB;
|
|
|
|
|
else
|
2010-03-11 21:26:21 +07:00
|
|
|
reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
|
|
|
|
|
DAC33_DACRPDNB | DAC33_DACLPDNB);
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_PWR_CTRL, reg);
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static inline void dac33_disable_digital(struct snd_soc_component *component)
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
{
|
|
|
|
|
u8 reg;
|
|
|
|
|
|
|
|
|
|
/* Stop the DAI clock */
|
2018-01-29 11:14:21 +07:00
|
|
|
reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
reg &= ~DAC33_BCLKON;
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg);
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
|
|
|
|
|
/* Power down the Oscillator, and DACs */
|
2018-01-29 11:14:21 +07:00
|
|
|
reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_PWR_CTRL, reg);
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_hard_power(struct snd_soc_component *component, int power)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
int ret = 0;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
mutex_lock(&dac33->mutex);
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
|
|
|
|
|
/* Safety check */
|
|
|
|
|
if (unlikely(power == dac33->chip_power)) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_dbg(component->dev, "Trying to set the same power state: %s\n",
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
power ? "ON" : "OFF");
|
|
|
|
|
goto exit;
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
if (power) {
|
2009-12-04 18:49:10 +07:00
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
|
|
|
|
|
dac33->supplies);
|
|
|
|
|
if (ret != 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev,
|
2009-12-04 18:49:10 +07:00
|
|
|
"Failed to enable supplies: %d\n", ret);
|
2018-11-16 22:06:34 +07:00
|
|
|
goto exit;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
2009-12-04 18:49:10 +07:00
|
|
|
|
|
|
|
|
if (dac33->power_gpio >= 0)
|
|
|
|
|
gpio_set_value(dac33->power_gpio, 1);
|
|
|
|
|
|
|
|
|
|
dac33->chip_power = 1;
|
2009-10-15 13:03:56 +07:00
|
|
|
} else {
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_soft_power(component, 0);
|
2009-12-04 18:49:10 +07:00
|
|
|
if (dac33->power_gpio >= 0)
|
2009-10-15 13:03:56 +07:00
|
|
|
gpio_set_value(dac33->power_gpio, 0);
|
2009-12-04 18:49:10 +07:00
|
|
|
|
|
|
|
|
ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
|
|
|
|
|
dac33->supplies);
|
|
|
|
|
if (ret != 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev,
|
2009-12-04 18:49:10 +07:00
|
|
|
"Failed to disable supplies: %d\n", ret);
|
|
|
|
|
goto exit;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
2009-12-04 18:49:10 +07:00
|
|
|
|
|
|
|
|
dac33->chip_power = 0;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2009-12-04 18:49:10 +07:00
|
|
|
exit:
|
|
|
|
|
mutex_unlock(&dac33->mutex);
|
|
|
|
|
return ret;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
static int dac33_playback_event(struct snd_soc_dapm_widget *w,
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
struct snd_kcontrol *kcontrol, int event)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
|
|
|
|
|
switch (event) {
|
|
|
|
|
case SND_SOC_DAPM_PRE_PMU:
|
|
|
|
|
if (likely(dac33->substream)) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_calculate_times(dac33->substream, component);
|
|
|
|
|
dac33_prepare_chip(dac33->substream, component);
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
}
|
|
|
|
|
break;
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
case SND_SOC_DAPM_POST_PMD:
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_disable_digital(component);
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
break;
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-31 15:30:19 +07:00
|
|
|
static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
|
2009-10-15 13:03:56 +07:00
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2016-03-01 00:08:03 +07:00
|
|
|
ucontrol->value.enumerated.item[0] = dac33->fifo_mode;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-31 15:30:19 +07:00
|
|
|
static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
|
2009-10-15 13:03:56 +07:00
|
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
int ret = 0;
|
|
|
|
|
|
2016-03-01 00:08:03 +07:00
|
|
|
if (dac33->fifo_mode == ucontrol->value.enumerated.item[0])
|
2009-10-15 13:03:56 +07:00
|
|
|
return 0;
|
|
|
|
|
/* Do not allow changes while stream is running*/
|
2018-01-29 11:14:21 +07:00
|
|
|
if (snd_soc_component_is_active(component))
|
2009-10-15 13:03:56 +07:00
|
|
|
return -EPERM;
|
|
|
|
|
|
2016-03-01 00:08:03 +07:00
|
|
|
if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE)
|
2009-10-15 13:03:56 +07:00
|
|
|
ret = -EINVAL;
|
|
|
|
|
else
|
2016-03-01 00:08:03 +07:00
|
|
|
dac33->fifo_mode = ucontrol->value.enumerated.item[0];
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-31 15:30:19 +07:00
|
|
|
/* Codec operation modes */
|
|
|
|
|
static const char *dac33_fifo_mode_texts[] = {
|
2009-12-31 15:30:22 +07:00
|
|
|
"Bypass", "Mode 1", "Mode 7"
|
2009-12-31 15:30:19 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-18 17:07:32 +07:00
|
|
|
static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts);
|
2009-12-31 15:30:19 +07:00
|
|
|
|
2010-10-13 15:56:28 +07:00
|
|
|
/* L/R Line Output Gain */
|
|
|
|
|
static const char *lr_lineout_gain_texts[] = {
|
|
|
|
|
"Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
|
|
|
|
|
"Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-18 17:07:32 +07:00
|
|
|
static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum,
|
|
|
|
|
DAC33_LDAC_PWR_CTRL, 0,
|
|
|
|
|
lr_lineout_gain_texts);
|
2010-10-13 15:56:28 +07:00
|
|
|
|
2014-02-18 17:07:32 +07:00
|
|
|
static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum,
|
|
|
|
|
DAC33_RDAC_PWR_CTRL, 0,
|
|
|
|
|
lr_lineout_gain_texts);
|
2010-10-13 15:56:28 +07:00
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
/*
|
|
|
|
|
* DACL/R digital volume control:
|
|
|
|
|
* from 0 dB to -63.5 in 0.5 dB steps
|
|
|
|
|
* Need to be inverted later on:
|
|
|
|
|
* 0x00 == 0 dB
|
|
|
|
|
* 0x7f == -63.5 dB
|
|
|
|
|
*/
|
|
|
|
|
static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new dac33_snd_controls[] = {
|
|
|
|
|
SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
|
|
|
|
|
DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
|
|
|
|
|
0, 0x7f, 1, dac_digivol_tlv),
|
|
|
|
|
SOC_DOUBLE_R("DAC Digital Playback Switch",
|
|
|
|
|
DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
|
|
|
|
|
SOC_DOUBLE_R("Line to Line Out Volume",
|
|
|
|
|
DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
|
2010-10-13 15:56:28 +07:00
|
|
|
SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
|
|
|
|
|
SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
|
2009-10-15 13:03:56 +07:00
|
|
|
};
|
|
|
|
|
|
2010-07-28 19:26:55 +07:00
|
|
|
static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
|
|
|
|
|
SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
|
|
|
|
|
dac33_get_fifo_mode, dac33_set_fifo_mode),
|
|
|
|
|
};
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
/* Analog bypass */
|
|
|
|
|
static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
|
|
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
|
|
|
|
|
SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
|
|
|
|
|
|
2011-01-10 20:39:49 +07:00
|
|
|
/* LOP L/R invert selection */
|
|
|
|
|
static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
|
|
|
|
|
|
2014-02-18 17:07:32 +07:00
|
|
|
static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum,
|
|
|
|
|
DAC33_OUT_AMP_CTRL, 3,
|
|
|
|
|
dac33_lr_lom_texts);
|
2011-01-10 20:39:49 +07:00
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
|
|
|
|
|
SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
|
|
|
|
|
|
2014-02-18 17:07:32 +07:00
|
|
|
static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum,
|
|
|
|
|
DAC33_OUT_AMP_CTRL, 2,
|
|
|
|
|
dac33_lr_lom_texts);
|
2011-01-10 20:39:49 +07:00
|
|
|
|
|
|
|
|
static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
|
|
|
|
|
SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("LEFT_LO"),
|
|
|
|
|
SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
|
|
|
|
|
|
|
|
|
|
SND_SOC_DAPM_INPUT("LINEL"),
|
|
|
|
|
SND_SOC_DAPM_INPUT("LINER"),
|
|
|
|
|
|
2010-12-08 21:04:33 +07:00
|
|
|
SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
|
|
|
|
|
SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* Analog bypass */
|
|
|
|
|
SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&dac33_dapm_abypassl_control),
|
|
|
|
|
SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&dac33_dapm_abypassr_control),
|
|
|
|
|
|
2011-01-10 20:39:49 +07:00
|
|
|
SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&dac33_dapm_left_lom_control),
|
|
|
|
|
SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
|
|
|
|
|
&dac33_dapm_right_lom_control),
|
|
|
|
|
/*
|
|
|
|
|
* For DAPM path, when only the anlog bypass path is enabled, and the
|
|
|
|
|
* LOP inverted from the corresponding DAC side.
|
|
|
|
|
* This is needed, so we can attach the DAC power supply in this case.
|
|
|
|
|
*/
|
|
|
|
|
SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
|
|
|
|
|
SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
|
|
|
|
|
|
2010-12-08 21:04:32 +07:00
|
|
|
SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
|
2009-10-15 13:03:56 +07:00
|
|
|
DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
|
2010-12-08 21:04:32 +07:00
|
|
|
SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
|
2009-10-15 13:03:56 +07:00
|
|
|
DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
|
2010-12-08 21:04:33 +07:00
|
|
|
SND_SOC_DAPM_SUPPLY("Left DAC Power",
|
|
|
|
|
DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
|
|
|
|
|
SND_SOC_DAPM_SUPPLY("Right DAC Power",
|
|
|
|
|
DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
|
|
|
|
|
|
2011-03-24 14:11:49 +07:00
|
|
|
SND_SOC_DAPM_SUPPLY("Codec Power",
|
|
|
|
|
DAC33_PWR_CTRL, 4, 0, NULL, 0),
|
|
|
|
|
|
ASoC: tlv320dac33: Power down digital parts, when not needed
If the following scenario has been followed:
1. Enable analog bypass
amixer sset 'Analog Left Bypass' on
amixer sset 'Analog Right Bypass' on
2. Start playback
aplay -fdat -d3 /dev/zero
After the playback stopped (3 sec), and the soc timeout (5 sec),
the digital parts of the codec will remain powered up.
This means that the DAI clocks are continue to run, the
oscillator remain operational, etc.
Use the SND_SOC_DAPM_POST_PMD widget to get notification
about the stopped stream, and power down the digital
part of the codec.
If the analog bypass is enabled, than the codec will remain in
BIAS_ON level, and things will work correctly.
In case, if the bypass is disabled, than the codec will
fall to BIAS_STANDBY than to BIAS_OFF level, as it used
to.
The digital part of DAC33 is initialized at every stream start
(DAPM_PRE:PRE_PMU event), so subsequent streams (within 5 sec)
will have working DAI.
When the codec is coming out from BIAS_OFF, the full power-up
sequence followed by the same DAPM_PRE widget event will power up
the digital part.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-12-10 18:26:31 +07:00
|
|
|
SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
|
|
|
|
|
SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
|
2009-10-15 13:03:56 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct snd_soc_dapm_route audio_map[] = {
|
|
|
|
|
/* Analog bypass */
|
|
|
|
|
{"Analog Left Bypass", "Switch", "LINEL"},
|
|
|
|
|
{"Analog Right Bypass", "Switch", "LINER"},
|
|
|
|
|
|
2010-12-08 21:04:32 +07:00
|
|
|
{"Output Left Amplifier", NULL, "DACL"},
|
|
|
|
|
{"Output Right Amplifier", NULL, "DACR"},
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2011-01-10 20:39:49 +07:00
|
|
|
{"Left Bypass PGA", NULL, "Analog Left Bypass"},
|
|
|
|
|
{"Right Bypass PGA", NULL, "Analog Right Bypass"},
|
|
|
|
|
|
|
|
|
|
{"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
|
|
|
|
|
{"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
|
|
|
|
|
{"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
|
|
|
|
|
{"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
|
|
|
|
|
|
|
|
|
|
{"Output Left Amplifier", NULL, "Left LOM Inverted From"},
|
|
|
|
|
{"Output Right Amplifier", NULL, "Right LOM Inverted From"},
|
|
|
|
|
|
|
|
|
|
{"DACL", NULL, "Left DAC Power"},
|
|
|
|
|
{"DACR", NULL, "Right DAC Power"},
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2011-01-10 20:39:49 +07:00
|
|
|
{"Left Bypass PGA", NULL, "Left DAC Power"},
|
|
|
|
|
{"Right Bypass PGA", NULL, "Right DAC Power"},
|
2010-12-08 21:04:33 +07:00
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
/* output */
|
2010-12-08 21:04:32 +07:00
|
|
|
{"LEFT_LO", NULL, "Output Left Amplifier"},
|
|
|
|
|
{"RIGHT_LO", NULL, "Output Right Amplifier"},
|
2011-03-24 14:11:49 +07:00
|
|
|
|
|
|
|
|
{"LEFT_LO", NULL, "Codec Power"},
|
|
|
|
|
{"RIGHT_LO", NULL, "Codec Power"},
|
2009-10-15 13:03:56 +07:00
|
|
|
};
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_set_bias_level(struct snd_soc_component *component,
|
2009-10-15 13:03:56 +07:00
|
|
|
enum snd_soc_bias_level level)
|
|
|
|
|
{
|
2009-12-04 18:49:10 +07:00
|
|
|
int ret;
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
switch (level) {
|
|
|
|
|
case SND_SOC_BIAS_ON:
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_BIAS_PREPARE:
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_BIAS_STANDBY:
|
2018-01-29 11:14:21 +07:00
|
|
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
|
|
|
|
|
/* Coming from OFF, switch on the component */
|
|
|
|
|
ret = dac33_hard_power(component, 1);
|
2009-12-04 18:49:10 +07:00
|
|
|
if (ret != 0)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_init_chip(component);
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
}
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
case SND_SOC_BIAS_OFF:
|
2018-01-29 11:14:21 +07:00
|
|
|
/* Do not power off, when the component is already off */
|
|
|
|
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
|
2010-05-17 18:21:46 +07:00
|
|
|
return 0;
|
2018-01-29 11:14:21 +07:00
|
|
|
ret = dac33_hard_power(component, 0);
|
2009-12-04 18:49:10 +07:00
|
|
|
if (ret != 0)
|
|
|
|
|
return ret;
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-31 15:30:20 +07:00
|
|
|
static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dac33->component;
|
2010-10-22 19:11:20 +07:00
|
|
|
unsigned int delay;
|
2011-03-18 20:15:11 +07:00
|
|
|
unsigned long flags;
|
2009-12-31 15:30:20 +07:00
|
|
|
|
|
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_NSAMPLE_MSB,
|
2010-07-28 19:26:54 +07:00
|
|
|
DAC33_THRREG(dac33->nsample));
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
|
|
|
|
/* Take the timestamps */
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_lock_irqsave(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->t_stamp2 = ktime_to_us(ktime_get());
|
|
|
|
|
dac33->t_stamp1 = dac33->t_stamp2;
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_unlock_irqrestore(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_PREFILL_MSB,
|
2009-12-31 15:30:20 +07:00
|
|
|
DAC33_THRREG(dac33->alarm_threshold));
|
2010-04-23 14:09:57 +07:00
|
|
|
/* Enable Alarm Threshold IRQ with a delay */
|
2010-10-22 19:11:20 +07:00
|
|
|
delay = SAMPLES_TO_US(dac33->burst_rate,
|
|
|
|
|
dac33->alarm_threshold) + 1000;
|
|
|
|
|
usleep_range(delay, delay + 500);
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
|
2009-12-31 15:30:20 +07:00
|
|
|
break;
|
2009-12-31 15:30:22 +07:00
|
|
|
case DAC33_FIFO_MODE7:
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
/* Take the timestamp */
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_lock_irqsave(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->t_stamp1 = ktime_to_us(ktime_get());
|
|
|
|
|
/* Move back the timestamp with drain time */
|
|
|
|
|
dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_unlock_irqrestore(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_PREFILL_MSB,
|
2010-12-22 15:45:17 +07:00
|
|
|
DAC33_THRREG(DAC33_MODE7_MARGIN));
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
|
|
|
|
/* Enable Upper Threshold IRQ */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
|
2009-12-31 15:30:22 +07:00
|
|
|
break;
|
2009-12-31 15:30:20 +07:00
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
|
2009-12-31 15:30:20 +07:00
|
|
|
dac33->fifo_mode);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dac33->component;
|
2011-03-18 20:15:11 +07:00
|
|
|
unsigned long flags;
|
2009-12-31 15:30:20 +07:00
|
|
|
|
|
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
/* Take the timestamp */
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_lock_irqsave(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->t_stamp2 = ktime_to_us(ktime_get());
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_unlock_irqrestore(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_NSAMPLE_MSB,
|
2009-12-31 15:30:20 +07:00
|
|
|
DAC33_THRREG(dac33->nsample));
|
|
|
|
|
break;
|
2009-12-31 15:30:22 +07:00
|
|
|
case DAC33_FIFO_MODE7:
|
|
|
|
|
/* At the moment we are not using interrupts in mode7 */
|
|
|
|
|
break;
|
2009-12-31 15:30:20 +07:00
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
|
2009-12-31 15:30:20 +07:00
|
|
|
dac33->fifo_mode);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
static void dac33_work(struct work_struct *work)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component;
|
2009-10-15 13:03:56 +07:00
|
|
|
struct tlv320dac33_priv *dac33;
|
|
|
|
|
u8 reg;
|
|
|
|
|
|
|
|
|
|
dac33 = container_of(work, struct tlv320dac33_priv, work);
|
2018-01-29 11:14:21 +07:00
|
|
|
component = dac33->component;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
mutex_lock(&dac33->mutex);
|
|
|
|
|
switch (dac33->state) {
|
|
|
|
|
case DAC33_PREFILL:
|
|
|
|
|
dac33->state = DAC33_PLAYBACK;
|
2009-12-31 15:30:20 +07:00
|
|
|
dac33_prefill_handler(dac33);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
case DAC33_PLAYBACK:
|
2009-12-31 15:30:20 +07:00
|
|
|
dac33_playback_handler(dac33);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
case DAC33_IDLE:
|
|
|
|
|
break;
|
|
|
|
|
case DAC33_FLUSH:
|
|
|
|
|
dac33->state = DAC33_IDLE;
|
|
|
|
|
/* Mask all interrupts from dac33 */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_IRQ_MASK, 0);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* flush fifo */
|
2018-01-29 11:14:21 +07:00
|
|
|
reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
|
2009-10-15 13:03:56 +07:00
|
|
|
reg |= DAC33_FIFOFLUSH;
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_CTRL_A, reg);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
mutex_unlock(&dac33->mutex);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dev;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2011-03-18 20:15:11 +07:00
|
|
|
unsigned long flags;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_lock_irqsave(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->t_stamp1 = ktime_to_us(ktime_get());
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_unlock_irqrestore(&dac33->lock, flags);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
/* Do not schedule the workqueue in Mode7 */
|
|
|
|
|
if (dac33->fifo_mode != DAC33_FIFO_MODE7)
|
2016-09-04 22:57:32 +07:00
|
|
|
schedule_work(&dac33->work);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static void dac33_oscwait(struct snd_soc_component *component)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2010-10-22 19:11:20 +07:00
|
|
|
int timeout = 60;
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 reg;
|
|
|
|
|
|
|
|
|
|
do {
|
2010-10-22 19:11:20 +07:00
|
|
|
usleep_range(1000, 2000);
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_read(component, DAC33_INT_OSC_STATUS, ®);
|
2009-10-15 13:03:56 +07:00
|
|
|
} while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
|
|
|
|
|
if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev,
|
2009-10-15 13:03:56 +07:00
|
|
|
"internal oscillator calibration failed\n");
|
|
|
|
|
}
|
|
|
|
|
|
2010-04-30 18:59:35 +07:00
|
|
|
static int dac33_startup(struct snd_pcm_substream *substream,
|
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2010-04-30 18:59:35 +07:00
|
|
|
|
|
|
|
|
/* Stream started, save the substream pointer */
|
|
|
|
|
dac33->substream = substream;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dac33_shutdown(struct snd_pcm_substream *substream,
|
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2010-04-30 18:59:35 +07:00
|
|
|
|
|
|
|
|
dac33->substream = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2010-12-22 15:45:17 +07:00
|
|
|
#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
|
|
|
|
|
(BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
|
2009-10-15 13:03:56 +07:00
|
|
|
static int dac33_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* Check parameters for validity */
|
|
|
|
|
switch (params_rate(params)) {
|
|
|
|
|
case 44100:
|
|
|
|
|
case 48000:
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "unsupported rate %d\n",
|
2009-10-15 13:03:56 +07:00
|
|
|
params_rate(params));
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-31 18:48:44 +07:00
|
|
|
switch (params_width(params)) {
|
|
|
|
|
case 16:
|
2010-12-22 15:45:17 +07:00
|
|
|
dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
|
|
|
|
|
dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
2014-07-31 18:48:44 +07:00
|
|
|
case 32:
|
2010-12-22 15:45:18 +07:00
|
|
|
dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
|
|
|
|
|
dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
|
|
|
|
|
break;
|
2009-10-15 13:03:56 +07:00
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "unsupported width %d\n",
|
2014-07-31 18:48:44 +07:00
|
|
|
params_width(params));
|
2009-10-15 13:03:56 +07:00
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define CALC_OSCSET(rate, refclk) ( \
|
2010-02-16 18:23:16 +07:00
|
|
|
((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
|
2009-10-15 13:03:56 +07:00
|
|
|
#define CALC_RATIOSET(rate, refclk) ( \
|
|
|
|
|
((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* tlv320dac33 is strict on the sequence of the register writes, if the register
|
|
|
|
|
* writes happens in different order, than dac33 might end up in unknown state.
|
|
|
|
|
* Use the known, working sequence of register writes to initialize the dac33.
|
|
|
|
|
*/
|
2012-04-04 21:58:16 +07:00
|
|
|
static int dac33_prepare_chip(struct snd_pcm_substream *substream,
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
|
2009-12-31 15:30:21 +07:00
|
|
|
u8 aictrl_a, aictrl_b, fifoctrl_a;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
switch (substream->runtime->rate) {
|
|
|
|
|
case 44100:
|
|
|
|
|
case 48000:
|
|
|
|
|
oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
|
|
|
|
|
ratioset = CALC_RATIOSET(substream->runtime->rate,
|
|
|
|
|
dac33->refclk);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "unsupported rate %d\n",
|
2009-10-15 13:03:56 +07:00
|
|
|
substream->runtime->rate);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
|
2009-10-15 13:03:56 +07:00
|
|
|
aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
|
2010-02-16 18:23:15 +07:00
|
|
|
/* Read FIFO control A, and clear FIFO flush bit */
|
2018-01-29 11:14:21 +07:00
|
|
|
fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
|
2010-02-16 18:23:15 +07:00
|
|
|
fifoctrl_a &= ~DAC33_FIFOFLUSH;
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
fifoctrl_a &= ~DAC33_WIDTH;
|
|
|
|
|
switch (substream->runtime->format) {
|
|
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
|
|
|
aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
|
|
|
|
|
fifoctrl_a |= DAC33_WIDTH;
|
|
|
|
|
break;
|
2010-12-22 15:45:18 +07:00
|
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
|
|
|
aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
|
|
|
|
|
break;
|
2009-10-15 13:03:56 +07:00
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "unsupported format %d\n",
|
2009-10-15 13:03:56 +07:00
|
|
|
substream->runtime->format);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mutex_lock(&dac33->mutex);
|
ASoC: tlv320dac33: Support for turning off the codec
Let the codec to hit OFF instead of STANDBY, when there is no activity.
When the codec is off, than the associated regulator can be also turned
off (if the number of users on the regulator is 0).
After initialization, the codec remains in power off, it is only turned
on for reading the ID registers (also testing the regulators).
The codec power is enabled, when the codec is moving from BIAS_OFF
to BIAS_STANDBY.
The codec is turned off, when it hits BIAS_OFF.
There are few scenarios, which has to be taken care::
1. Analog bypass caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, but we does not
need to execute the playback related configuration
2. Playback caused BIAS_OFF -> BIAS_ON
We need to power on the codec, and do the chip init, and also we need
to execute the playback related configuration.
3. Playback start, while Analog bypass is on (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
already on.
4. Analog bypass enable, while playback (BIAS_ON -> BIAS_ON)
Nothing need to be done.
5. Playback start withing soc power down timeout (BIAS_ON -> BIAS_ON)
We need to execute the playback related configuration. The codec is
still on.
Since the power up, and the codec init is optimized, the added overhead
in stream start is minimal.
Withing this patch, the hard_power function is now only doing what it
supposed to: only handle the powers, and GPIO reset line.
The codec initialization and state restore has been moved out.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-30 18:59:36 +07:00
|
|
|
|
|
|
|
|
if (!dac33->chip_power) {
|
|
|
|
|
/*
|
|
|
|
|
* Chip is not powered yet.
|
|
|
|
|
* Do the init in the dac33_set_bias_level later.
|
|
|
|
|
*/
|
|
|
|
|
mutex_unlock(&dac33->mutex);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_soft_power(component, 0);
|
|
|
|
|
dac33_soft_power(component, 1);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
|
|
|
|
|
dac33_write(component, DAC33_INT_OSC_CTRL, reg_tmp);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* Write registers 0x08 and 0x09 (MSB, LSB) */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, oscset);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2011-04-12 13:09:17 +07:00
|
|
|
/* OSC calibration time */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_CALIB_TIME, 96);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* adjustment treshold & step */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
|
2009-10-15 13:03:56 +07:00
|
|
|
DAC33_ADJSTEP(1));
|
|
|
|
|
|
|
|
|
|
/* div=4 / gain=1 / div */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
|
2009-10-15 13:03:56 +07:00
|
|
|
pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_PWR_CTRL, pwr_ctrl);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_oscwait(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2009-12-31 15:30:19 +07:00
|
|
|
if (dac33->fifo_mode) {
|
2009-12-31 15:30:21 +07:00
|
|
|
/* Generic for all FIFO modes */
|
2009-10-15 13:03:56 +07:00
|
|
|
/* 50-51 : ASRC Control registers */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
|
|
|
|
|
dac33_write(component, DAC33_ASRC_CTRL_B, 1); /* ??? */
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* Write registers 0x34 and 0x35 (MSB, LSB) */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* Set interrupts to high active */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
|
2009-10-15 13:03:56 +07:00
|
|
|
} else {
|
2009-12-31 15:30:21 +07:00
|
|
|
/* FIFO bypass mode */
|
2009-10-15 13:03:56 +07:00
|
|
|
/* 50-51 : ASRC Control registers */
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
|
|
|
|
|
dac33_write(component, DAC33_ASRC_CTRL_B, 0); /* ??? */
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2009-12-31 15:30:21 +07:00
|
|
|
/* Interrupt behaviour configuration */
|
|
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_IRQ_MODE_B,
|
2009-12-31 15:30:21 +07:00
|
|
|
DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
|
|
|
|
|
break;
|
2009-12-31 15:30:22 +07:00
|
|
|
case DAC33_FIFO_MODE7:
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_IRQ_MODE_A,
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
|
2009-12-31 15:30:22 +07:00
|
|
|
break;
|
2009-12-31 15:30:21 +07:00
|
|
|
default:
|
|
|
|
|
/* in FIFO bypass mode, the interrupts are not used */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
|
2009-12-31 15:30:21 +07:00
|
|
|
|
|
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
|
|
|
|
/*
|
|
|
|
|
* For mode1:
|
|
|
|
|
* Disable the FIFO bypass (Enable the use of FIFO)
|
|
|
|
|
* Select nSample mode
|
|
|
|
|
* BCLK is only running when data is needed by DAC33
|
|
|
|
|
*/
|
2009-10-15 13:03:56 +07:00
|
|
|
fifoctrl_a &= ~DAC33_FBYPAS;
|
2009-12-31 15:30:21 +07:00
|
|
|
fifoctrl_a &= ~DAC33_FAUTO;
|
2010-03-11 21:26:22 +07:00
|
|
|
if (dac33->keep_bclk)
|
|
|
|
|
aictrl_b |= DAC33_BCLKON;
|
|
|
|
|
else
|
|
|
|
|
aictrl_b &= ~DAC33_BCLKON;
|
2009-12-31 15:30:21 +07:00
|
|
|
break;
|
2009-12-31 15:30:22 +07:00
|
|
|
case DAC33_FIFO_MODE7:
|
|
|
|
|
/*
|
|
|
|
|
* For mode1:
|
|
|
|
|
* Disable the FIFO bypass (Enable the use of FIFO)
|
|
|
|
|
* Select Threshold mode
|
|
|
|
|
* BCLK is only running when data is needed by DAC33
|
|
|
|
|
*/
|
|
|
|
|
fifoctrl_a &= ~DAC33_FBYPAS;
|
|
|
|
|
fifoctrl_a |= DAC33_FAUTO;
|
2010-03-11 21:26:22 +07:00
|
|
|
if (dac33->keep_bclk)
|
|
|
|
|
aictrl_b |= DAC33_BCLKON;
|
|
|
|
|
else
|
|
|
|
|
aictrl_b &= ~DAC33_BCLKON;
|
2009-12-31 15:30:22 +07:00
|
|
|
break;
|
2009-12-31 15:30:21 +07:00
|
|
|
default:
|
|
|
|
|
/*
|
|
|
|
|
* For FIFO bypass mode:
|
|
|
|
|
* Enable the FIFO bypass (Disable the FIFO use)
|
2011-03-31 08:57:33 +07:00
|
|
|
* Set the BCLK as continuous
|
2009-12-31 15:30:21 +07:00
|
|
|
*/
|
2009-10-15 13:03:56 +07:00
|
|
|
fifoctrl_a |= DAC33_FBYPAS;
|
2009-12-31 15:30:21 +07:00
|
|
|
aictrl_b |= DAC33_BCLKON;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_FIFO_CTRL_A, fifoctrl_a);
|
|
|
|
|
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
|
|
|
|
|
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-01-20 14:39:36 +07:00
|
|
|
/*
|
|
|
|
|
* BCLK divide ratio
|
|
|
|
|
* 0: 1.5
|
|
|
|
|
* 1: 1
|
|
|
|
|
* 2: 2
|
|
|
|
|
* ...
|
|
|
|
|
* 254: 254
|
|
|
|
|
* 255: 255
|
|
|
|
|
*/
|
2010-01-20 14:39:35 +07:00
|
|
|
if (dac33->fifo_mode)
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C,
|
2010-01-20 14:39:36 +07:00
|
|
|
dac33->burst_bclkdiv);
|
2010-01-20 14:39:35 +07:00
|
|
|
else
|
2010-12-22 15:45:18 +07:00
|
|
|
if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 32);
|
2010-12-22 15:45:18 +07:00
|
|
|
else
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 16);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-01-20 14:39:35 +07:00
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_ATHR_MSB,
|
2009-10-15 13:03:56 +07:00
|
|
|
DAC33_THRREG(dac33->alarm_threshold));
|
2009-12-31 15:30:21 +07:00
|
|
|
break;
|
2009-12-31 15:30:22 +07:00
|
|
|
case DAC33_FIFO_MODE7:
|
|
|
|
|
/*
|
|
|
|
|
* Configure the threshold levels, and leave 10 sample space
|
|
|
|
|
* at the bottom, and also at the top of the FIFO
|
|
|
|
|
*/
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
|
|
|
|
|
dac33_write16(component, DAC33_LTHR_MSB,
|
2010-12-22 15:45:17 +07:00
|
|
|
DAC33_THRREG(DAC33_MODE7_MARGIN));
|
2009-12-31 15:30:22 +07:00
|
|
|
break;
|
2009-12-31 15:30:21 +07:00
|
|
|
default:
|
|
|
|
|
break;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mutex_unlock(&dac33->mutex);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-04 21:58:16 +07:00
|
|
|
static void dac33_calculate_times(struct snd_pcm_substream *substream,
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2010-07-28 19:26:54 +07:00
|
|
|
unsigned int period_size = substream->runtime->period_size;
|
|
|
|
|
unsigned int rate = substream->runtime->rate;
|
2009-10-15 13:03:56 +07:00
|
|
|
unsigned int nsample_limit;
|
|
|
|
|
|
2010-04-23 14:09:58 +07:00
|
|
|
/* In bypass mode we don't need to calculate */
|
|
|
|
|
if (!dac33->fifo_mode)
|
|
|
|
|
return;
|
|
|
|
|
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
2010-07-28 19:26:54 +07:00
|
|
|
/* Number of samples under i2c latency */
|
|
|
|
|
dac33->alarm_threshold = US_TO_SAMPLES(rate,
|
|
|
|
|
dac33->mode1_latency);
|
2010-12-22 15:45:17 +07:00
|
|
|
nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
|
2010-10-29 13:49:37 +07:00
|
|
|
|
2010-12-22 15:45:16 +07:00
|
|
|
if (period_size <= dac33->alarm_threshold)
|
2010-07-28 19:26:55 +07:00
|
|
|
/*
|
2010-12-22 15:45:16 +07:00
|
|
|
* Configure nSamaple to number of periods,
|
|
|
|
|
* which covers the latency requironment.
|
2010-07-28 19:26:55 +07:00
|
|
|
*/
|
2010-12-22 15:45:16 +07:00
|
|
|
dac33->nsample = period_size *
|
|
|
|
|
((dac33->alarm_threshold / period_size) +
|
|
|
|
|
(dac33->alarm_threshold % period_size ?
|
|
|
|
|
1 : 0));
|
|
|
|
|
else if (period_size > nsample_limit)
|
|
|
|
|
dac33->nsample = nsample_limit;
|
|
|
|
|
else
|
|
|
|
|
dac33->nsample = period_size;
|
2010-07-28 19:26:54 +07:00
|
|
|
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
|
|
|
|
|
dac33->nsample);
|
|
|
|
|
dac33->t_stamp1 = 0;
|
|
|
|
|
dac33->t_stamp2 = 0;
|
|
|
|
|
break;
|
|
|
|
|
case DAC33_FIFO_MODE7:
|
2010-12-22 15:45:16 +07:00
|
|
|
dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
|
|
|
|
|
dac33->burst_rate) + 9;
|
2010-12-22 15:45:17 +07:00
|
|
|
if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
|
|
|
|
|
dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
|
|
|
|
|
if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
|
|
|
|
|
dac33->uthr = (DAC33_MODE7_MARGIN + 10);
|
2010-12-22 15:45:16 +07:00
|
|
|
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->mode7_us_to_lthr =
|
2010-06-07 14:50:39 +07:00
|
|
|
SAMPLES_TO_US(substream->runtime->rate,
|
2010-12-22 15:45:17 +07:00
|
|
|
dac33->uthr - DAC33_MODE7_MARGIN + 1);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->t_stamp1 = 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2009-12-31 15:30:19 +07:00
|
|
|
if (dac33->fifo_mode) {
|
2009-10-15 13:03:56 +07:00
|
|
|
dac33->state = DAC33_PREFILL;
|
2016-09-04 22:57:32 +07:00
|
|
|
schedule_work(&dac33->work);
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
2009-12-31 15:30:19 +07:00
|
|
|
if (dac33->fifo_mode) {
|
2009-10-15 13:03:56 +07:00
|
|
|
dac33->state = DAC33_FLUSH;
|
2016-09-04 22:57:32 +07:00
|
|
|
schedule_work(&dac33->work);
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
ret = -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
static snd_pcm_sframes_t dac33_dai_delay(
|
|
|
|
|
struct snd_pcm_substream *substream,
|
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
unsigned long long t0, t1, t_now;
|
2010-06-07 14:50:39 +07:00
|
|
|
unsigned int time_delta, uthr;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
int samples_out, samples_in, samples;
|
|
|
|
|
snd_pcm_sframes_t delay = 0;
|
2011-03-18 20:15:11 +07:00
|
|
|
unsigned long flags;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
|
|
|
|
switch (dac33->fifo_mode) {
|
|
|
|
|
case DAC33_FIFO_BYPASS:
|
|
|
|
|
break;
|
|
|
|
|
case DAC33_FIFO_MODE1:
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_lock_irqsave(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
t0 = dac33->t_stamp1;
|
|
|
|
|
t1 = dac33->t_stamp2;
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_unlock_irqrestore(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
t_now = ktime_to_us(ktime_get());
|
|
|
|
|
|
|
|
|
|
/* We have not started to fill the FIFO yet, delay is 0 */
|
|
|
|
|
if (!t1)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
if (t0 > t1) {
|
|
|
|
|
/*
|
|
|
|
|
* Phase 1:
|
|
|
|
|
* After Alarm threshold, and before nSample write
|
|
|
|
|
*/
|
|
|
|
|
time_delta = t_now - t0;
|
|
|
|
|
samples_out = time_delta ? US_TO_SAMPLES(
|
|
|
|
|
substream->runtime->rate,
|
|
|
|
|
time_delta) : 0;
|
|
|
|
|
|
|
|
|
|
if (likely(dac33->alarm_threshold > samples_out))
|
|
|
|
|
delay = dac33->alarm_threshold - samples_out;
|
|
|
|
|
else
|
|
|
|
|
delay = 0;
|
|
|
|
|
} else if ((t_now - t1) <= dac33->mode1_us_burst) {
|
|
|
|
|
/*
|
|
|
|
|
* Phase 2:
|
|
|
|
|
* After nSample write (during burst operation)
|
|
|
|
|
*/
|
|
|
|
|
time_delta = t_now - t0;
|
|
|
|
|
samples_out = time_delta ? US_TO_SAMPLES(
|
|
|
|
|
substream->runtime->rate,
|
|
|
|
|
time_delta) : 0;
|
|
|
|
|
|
|
|
|
|
time_delta = t_now - t1;
|
|
|
|
|
samples_in = time_delta ? US_TO_SAMPLES(
|
|
|
|
|
dac33->burst_rate,
|
|
|
|
|
time_delta) : 0;
|
|
|
|
|
|
|
|
|
|
samples = dac33->alarm_threshold;
|
|
|
|
|
samples += (samples_in - samples_out);
|
|
|
|
|
|
|
|
|
|
if (likely(samples > 0))
|
|
|
|
|
delay = samples;
|
|
|
|
|
else
|
|
|
|
|
delay = 0;
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* Phase 3:
|
|
|
|
|
* After burst operation, before next alarm threshold
|
|
|
|
|
*/
|
|
|
|
|
time_delta = t_now - t0;
|
|
|
|
|
samples_out = time_delta ? US_TO_SAMPLES(
|
|
|
|
|
substream->runtime->rate,
|
|
|
|
|
time_delta) : 0;
|
|
|
|
|
|
|
|
|
|
samples_in = dac33->nsample;
|
|
|
|
|
samples = dac33->alarm_threshold;
|
|
|
|
|
samples += (samples_in - samples_out);
|
|
|
|
|
|
|
|
|
|
if (likely(samples > 0))
|
2010-12-22 15:45:17 +07:00
|
|
|
delay = samples > dac33->fifo_size ?
|
|
|
|
|
dac33->fifo_size : samples;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
else
|
|
|
|
|
delay = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case DAC33_FIFO_MODE7:
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_lock_irqsave(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
t0 = dac33->t_stamp1;
|
2010-06-07 14:50:39 +07:00
|
|
|
uthr = dac33->uthr;
|
2011-03-18 20:15:11 +07:00
|
|
|
spin_unlock_irqrestore(&dac33->lock, flags);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
t_now = ktime_to_us(ktime_get());
|
|
|
|
|
|
|
|
|
|
/* We have not started to fill the FIFO yet, delay is 0 */
|
|
|
|
|
if (!t0)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
if (t_now <= t0) {
|
|
|
|
|
/*
|
|
|
|
|
* Either the timestamps are messed or equal. Report
|
|
|
|
|
* maximum delay
|
|
|
|
|
*/
|
2010-06-07 14:50:39 +07:00
|
|
|
delay = uthr;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
time_delta = t_now - t0;
|
|
|
|
|
if (time_delta <= dac33->mode7_us_to_lthr) {
|
|
|
|
|
/*
|
|
|
|
|
* Phase 1:
|
|
|
|
|
* After burst (draining phase)
|
|
|
|
|
*/
|
|
|
|
|
samples_out = US_TO_SAMPLES(
|
|
|
|
|
substream->runtime->rate,
|
|
|
|
|
time_delta);
|
|
|
|
|
|
2010-06-07 14:50:39 +07:00
|
|
|
if (likely(uthr > samples_out))
|
|
|
|
|
delay = uthr - samples_out;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
else
|
|
|
|
|
delay = 0;
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* Phase 2:
|
|
|
|
|
* During burst operation
|
|
|
|
|
*/
|
|
|
|
|
time_delta = time_delta - dac33->mode7_us_to_lthr;
|
|
|
|
|
|
|
|
|
|
samples_out = US_TO_SAMPLES(
|
|
|
|
|
substream->runtime->rate,
|
|
|
|
|
time_delta);
|
|
|
|
|
samples_in = US_TO_SAMPLES(
|
|
|
|
|
dac33->burst_rate,
|
|
|
|
|
time_delta);
|
2010-12-22 15:45:17 +07:00
|
|
|
delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
|
2010-06-07 14:50:39 +07:00
|
|
|
if (unlikely(delay > uthr))
|
|
|
|
|
delay = uthr;
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
dac33->fifo_mode);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
out:
|
|
|
|
|
return delay;
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-15 13:03:56 +07:00
|
|
|
static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
|
|
|
|
|
int clk_id, unsigned int freq, int dir)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 ioc_reg, asrcb_reg;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
|
|
|
|
|
asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B);
|
2009-10-15 13:03:56 +07:00
|
|
|
switch (clk_id) {
|
|
|
|
|
case TLV320DAC33_MCLK:
|
|
|
|
|
ioc_reg |= DAC33_REFSEL;
|
|
|
|
|
asrcb_reg |= DAC33_SRCREFSEL;
|
|
|
|
|
break;
|
|
|
|
|
case TLV320DAC33_SLEEPCLK:
|
|
|
|
|
ioc_reg &= ~DAC33_REFSEL;
|
|
|
|
|
asrcb_reg &= ~DAC33_SRCREFSEL;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Invalid clock ID (%d)\n", clk_id);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
dac33->refclk = freq;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, ioc_reg);
|
|
|
|
|
dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, asrcb_reg);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
|
|
|
|
|
unsigned int fmt)
|
|
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct snd_soc_component *component = codec_dai->component;
|
|
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
u8 aictrl_a, aictrl_b;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
|
|
|
|
|
aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
|
2009-10-15 13:03:56 +07:00
|
|
|
/* set master/slave audio interface */
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
|
/* Codec Master */
|
|
|
|
|
aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
|
/* Codec Slave */
|
2009-12-31 15:30:23 +07:00
|
|
|
if (dac33->fifo_mode) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "FIFO mode requires master mode\n");
|
2009-12-31 15:30:23 +07:00
|
|
|
return -EINVAL;
|
|
|
|
|
} else
|
|
|
|
|
aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
aictrl_a &= ~DAC33_AFMT_MASK;
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
|
aictrl_a |= DAC33_AFMT_I2S;
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
|
|
|
aictrl_a |= DAC33_AFMT_DSP;
|
|
|
|
|
aictrl_b &= ~DAC33_DATA_DELAY_MASK;
|
2010-03-19 16:10:19 +07:00
|
|
|
aictrl_b |= DAC33_DATA_DELAY(0);
|
2009-10-15 13:03:56 +07:00
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_RIGHT_J:
|
|
|
|
|
aictrl_a |= DAC33_AFMT_RIGHT_J;
|
|
|
|
|
break;
|
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
|
aictrl_a |= DAC33_AFMT_LEFT_J;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Unsupported format (%u)\n",
|
2009-10-15 13:03:56 +07:00
|
|
|
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
|
|
|
|
|
dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static int dac33_soc_probe(struct snd_soc_component *component)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
int ret = 0;
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33->component = component;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
/* Read the tlv320dac33 ID registers */
|
2018-01-29 11:14:21 +07:00
|
|
|
ret = dac33_hard_power(component, 1);
|
2010-03-18 03:15:21 +07:00
|
|
|
if (ret != 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Failed to power up component: %d\n", ret);
|
2010-03-18 03:15:21 +07:00
|
|
|
goto err_power;
|
|
|
|
|
}
|
2018-01-29 11:14:21 +07:00
|
|
|
ret = dac33_read_id(component);
|
|
|
|
|
dac33_hard_power(component, 0);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-10-26 15:45:59 +07:00
|
|
|
if (ret < 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Failed to read chip ID: %d\n", ret);
|
2010-10-26 15:45:59 +07:00
|
|
|
ret = -ENODEV;
|
|
|
|
|
goto err_power;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
/* Check if the IRQ number is valid and request it */
|
|
|
|
|
if (dac33->irq >= 0) {
|
|
|
|
|
ret = request_irq(dac33->irq, dac33_interrupt_handler,
|
2011-09-22 15:59:20 +07:00
|
|
|
IRQF_TRIGGER_RISING,
|
2018-01-29 11:14:21 +07:00
|
|
|
component->name, component);
|
2010-03-18 03:15:21 +07:00
|
|
|
if (ret < 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
dev_err(component->dev, "Could not request IRQ%d (%d)\n",
|
2010-03-18 03:15:21 +07:00
|
|
|
dac33->irq, ret);
|
|
|
|
|
dac33->irq = -1;
|
|
|
|
|
}
|
|
|
|
|
if (dac33->irq != -1) {
|
|
|
|
|
INIT_WORK(&dac33->work, dac33_work);
|
|
|
|
|
}
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2010-07-28 19:26:55 +07:00
|
|
|
/* Only add the FIFO controls, if we have valid IRQ number */
|
2010-12-22 15:45:16 +07:00
|
|
|
if (dac33->irq >= 0)
|
2018-01-29 11:14:21 +07:00
|
|
|
snd_soc_add_component_controls(component, dac33_mode_snd_controls,
|
2010-07-28 19:26:55 +07:00
|
|
|
ARRAY_SIZE(dac33_mode_snd_controls));
|
2010-12-22 15:45:16 +07:00
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
err_power:
|
2009-10-15 13:03:56 +07:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static void dac33_soc_remove(struct snd_soc_component *component)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2018-01-29 11:14:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
if (dac33->irq >= 0) {
|
2018-01-29 11:14:21 +07:00
|
|
|
free_irq(dac33->irq, dac33->component);
|
2016-09-04 22:57:32 +07:00
|
|
|
flush_work(&dac33->work);
|
2010-03-18 03:15:21 +07:00
|
|
|
}
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = {
|
|
|
|
|
.read = dac33_read_reg_cache,
|
|
|
|
|
.write = dac33_write_locked,
|
|
|
|
|
.set_bias_level = dac33_set_bias_level,
|
|
|
|
|
.probe = dac33_soc_probe,
|
|
|
|
|
.remove = dac33_soc_remove,
|
|
|
|
|
.controls = dac33_snd_controls,
|
|
|
|
|
.num_controls = ARRAY_SIZE(dac33_snd_controls),
|
|
|
|
|
.dapm_widgets = dac33_dapm_widgets,
|
|
|
|
|
.num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets),
|
|
|
|
|
.dapm_routes = audio_map,
|
|
|
|
|
.num_dapm_routes = ARRAY_SIZE(audio_map),
|
|
|
|
|
.use_pmdown_time = 1,
|
|
|
|
|
.endianness = 1,
|
|
|
|
|
.non_legacy_dai_naming = 1,
|
2009-10-15 13:03:56 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
|
|
|
|
|
SNDRV_PCM_RATE_48000)
|
2010-12-22 15:45:18 +07:00
|
|
|
#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
2009-10-15 13:03:56 +07:00
|
|
|
|
2011-11-23 17:40:40 +07:00
|
|
|
static const struct snd_soc_dai_ops dac33_dai_ops = {
|
2010-04-30 18:59:35 +07:00
|
|
|
.startup = dac33_startup,
|
2009-10-15 13:03:56 +07:00
|
|
|
.shutdown = dac33_shutdown,
|
|
|
|
|
.hw_params = dac33_hw_params,
|
|
|
|
|
.trigger = dac33_pcm_trigger,
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
.delay = dac33_dai_delay,
|
2009-10-15 13:03:56 +07:00
|
|
|
.set_sysclk = dac33_set_dai_sysclk,
|
|
|
|
|
.set_fmt = dac33_set_dai_fmt,
|
|
|
|
|
};
|
|
|
|
|
|
2010-03-18 03:15:21 +07:00
|
|
|
static struct snd_soc_dai_driver dac33_dai = {
|
|
|
|
|
.name = "tlv320dac33-hifi",
|
2009-10-15 13:03:56 +07:00
|
|
|
.playback = {
|
|
|
|
|
.stream_name = "Playback",
|
|
|
|
|
.channels_min = 2,
|
|
|
|
|
.channels_max = 2,
|
|
|
|
|
.rates = DAC33_RATES,
|
2012-01-21 00:52:39 +07:00
|
|
|
.formats = DAC33_FORMATS,
|
2012-01-18 18:18:25 +07:00
|
|
|
.sig_bits = 24,
|
2012-01-21 00:52:39 +07:00
|
|
|
},
|
2009-10-15 13:03:56 +07:00
|
|
|
.ops = &dac33_dai_ops,
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-07 21:26:37 +07:00
|
|
|
static int dac33_i2c_probe(struct i2c_client *client,
|
|
|
|
|
const struct i2c_device_id *id)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
|
|
|
|
struct tlv320dac33_platform_data *pdata;
|
|
|
|
|
struct tlv320dac33_priv *dac33;
|
2009-12-04 18:49:10 +07:00
|
|
|
int ret, i;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
if (client->dev.platform_data == NULL) {
|
|
|
|
|
dev_err(&client->dev, "Platform data not set\n");
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
pdata = client->dev.platform_data;
|
|
|
|
|
|
2011-12-29 11:11:00 +07:00
|
|
|
dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
|
|
|
|
|
GFP_KERNEL);
|
2009-10-15 13:03:56 +07:00
|
|
|
if (dac33 == NULL)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2017-11-14 08:04:25 +07:00
|
|
|
dac33->reg_cache = devm_kmemdup(&client->dev,
|
|
|
|
|
dac33_reg,
|
|
|
|
|
ARRAY_SIZE(dac33_reg) * sizeof(u8),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!dac33->reg_cache)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2017-11-09 07:19:48 +07:00
|
|
|
dac33->i2c = client;
|
2009-10-15 13:03:56 +07:00
|
|
|
mutex_init(&dac33->mutex);
|
ASoC: tlv320dac33: FIFO caused delay reporting
Delay reporting for the three implemented DAC33 FIFO modes.
DAC33 has FIFO depth status register(s), but it can not be used, since
inside of pcm_pointer we can not send I2C commands.
Timestamp based estimation need to be used. The method of calculating
the delay depends on the active FIFO mode.
Bypass mode: FIFO is bypassed, report 0 as delay
Mode1: nSample fill mode. In this mode I need to use two timestamp
ts1: taken when the interrupt has been received
ts2: taken before writing to nSample register.
Interrupts are coming when DAC33 FIFO depth goes under alarm threshold.
Phase1: when we received the alarm threshold, but our workqueue has
not been executed (safeguard phase). Just count the played out
samples since ts1 and subtract it from the alarm threshold
value.
Phase2: During nSample burst (after writing to nSample register), count
the played out samples since ts1, count the samples received
since ts2 (in a burst). Estimate the FIFO depth using these and
alarm threshold value.
Phase3: Draining phase (after the burst read), count the played out
samples since ts1. Estimate the FIFO depth using the nSample
configuration and the alarm threshold value.
Mode7: Threshold based fill mode. In this mode one timestamp is enough.
ts1: taken when the interrupt has been received
Interrupts are coming when DAC33 FIFO depth reaches upper threshold.
Phase1: Draining phase (after the burst), counting the played out
samples since ts1, and subtract it from the upper threshold
value.
Phase2: During burst operation. Using the pre calculated time needed to
play out samples from the buffer during the drain period (from
upper to lower threshold), move the time window to cover the
estimated time from the burst start to the current time.
Calculate the samples played out since lower threshold and also
the samples received during the same time.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
2010-04-23 14:10:01 +07:00
|
|
|
spin_lock_init(&dac33->lock);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
i2c_set_clientdata(client, dac33);
|
|
|
|
|
|
|
|
|
|
dac33->power_gpio = pdata->power_gpio;
|
2010-01-20 14:39:36 +07:00
|
|
|
dac33->burst_bclkdiv = pdata->burst_bclkdiv;
|
2010-03-11 21:26:22 +07:00
|
|
|
dac33->keep_bclk = pdata->keep_bclk;
|
2010-07-28 19:26:54 +07:00
|
|
|
dac33->mode1_latency = pdata->mode1_latency;
|
|
|
|
|
if (!dac33->mode1_latency)
|
|
|
|
|
dac33->mode1_latency = 10000; /* 10ms */
|
2009-10-15 13:03:56 +07:00
|
|
|
dac33->irq = client->irq;
|
|
|
|
|
/* Disable FIFO use by default */
|
2009-12-31 15:30:19 +07:00
|
|
|
dac33->fifo_mode = DAC33_FIFO_BYPASS;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
/* Check if the reset GPIO number is valid and request it */
|
|
|
|
|
if (dac33->power_gpio >= 0) {
|
|
|
|
|
ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
|
|
|
|
|
if (ret < 0) {
|
2010-03-18 03:15:21 +07:00
|
|
|
dev_err(&client->dev,
|
2009-10-15 13:03:56 +07:00
|
|
|
"Failed to request reset GPIO (%d)\n",
|
|
|
|
|
dac33->power_gpio);
|
2010-03-18 03:15:21 +07:00
|
|
|
goto err_gpio;
|
2009-10-15 13:03:56 +07:00
|
|
|
}
|
|
|
|
|
gpio_direction_output(dac33->power_gpio, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2009-12-04 18:49:10 +07:00
|
|
|
for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
|
|
|
|
|
dac33->supplies[i].supply = dac33_supply_names[i];
|
|
|
|
|
|
2014-04-25 08:27:03 +07:00
|
|
|
ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
|
2009-12-04 18:49:10 +07:00
|
|
|
dac33->supplies);
|
|
|
|
|
|
|
|
|
|
if (ret != 0) {
|
2010-03-18 03:15:21 +07:00
|
|
|
dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
|
2009-12-04 18:49:10 +07:00
|
|
|
goto err_get;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-29 11:14:21 +07:00
|
|
|
ret = devm_snd_soc_register_component(&client->dev,
|
|
|
|
|
&soc_component_dev_tlv320dac33, &dac33_dai, 1);
|
2010-03-18 03:15:21 +07:00
|
|
|
if (ret < 0)
|
2014-04-25 08:27:03 +07:00
|
|
|
goto err_get;
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
return ret;
|
2009-12-04 18:49:10 +07:00
|
|
|
err_get:
|
2009-10-15 13:03:56 +07:00
|
|
|
if (dac33->power_gpio >= 0)
|
|
|
|
|
gpio_free(dac33->power_gpio);
|
2010-03-18 03:15:21 +07:00
|
|
|
err_gpio:
|
2009-10-15 13:03:56 +07:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-07 21:26:37 +07:00
|
|
|
static int dac33_i2c_remove(struct i2c_client *client)
|
2009-10-15 13:03:56 +07:00
|
|
|
{
|
2010-03-18 03:15:21 +07:00
|
|
|
struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
|
2010-04-30 18:59:34 +07:00
|
|
|
|
|
|
|
|
if (unlikely(dac33->chip_power))
|
2018-01-29 11:14:21 +07:00
|
|
|
dac33_hard_power(dac33->component, 0);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
if (dac33->power_gpio >= 0)
|
|
|
|
|
gpio_free(dac33->power_gpio);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct i2c_device_id tlv320dac33_i2c_id[] = {
|
|
|
|
|
{
|
|
|
|
|
.name = "tlv320dac33",
|
|
|
|
|
.driver_data = 0,
|
|
|
|
|
},
|
|
|
|
|
{ },
|
|
|
|
|
};
|
2011-03-04 14:18:18 +07:00
|
|
|
MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
static struct i2c_driver tlv320dac33_i2c_driver = {
|
|
|
|
|
.driver = {
|
2010-03-18 03:15:21 +07:00
|
|
|
.name = "tlv320dac33-codec",
|
2009-10-15 13:03:56 +07:00
|
|
|
},
|
|
|
|
|
.probe = dac33_i2c_probe,
|
2012-12-07 21:26:37 +07:00
|
|
|
.remove = dac33_i2c_remove,
|
2009-10-15 13:03:56 +07:00
|
|
|
.id_table = tlv320dac33_i2c_id,
|
|
|
|
|
};
|
|
|
|
|
|
2012-08-06 18:55:44 +07:00
|
|
|
module_i2c_driver(tlv320dac33_i2c_driver);
|
2009-10-15 13:03:56 +07:00
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
|
2011-05-03 22:11:36 +07:00
|
|
|
MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
|
2009-10-15 13:03:56 +07:00
|
|
|
MODULE_LICENSE("GPL");
|