2019-05-29 21:17:58 +07:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2018-10-11 17:16:01 +07:00
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/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
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2015-03-03 06:30:29 +07:00
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* Copyright (C) 2015 Linaro Ltd.
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2010-08-28 00:01:23 +07:00
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*/
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2015-02-05 05:30:46 +07:00
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#ifndef __QCOM_SCM_H
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#define __QCOM_SCM_H
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2010-08-28 00:01:23 +07:00
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2018-12-26 19:06:19 +07:00
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#include <linux/err.h>
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2017-12-05 00:18:46 +07:00
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#include <linux/types.h>
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#include <linux/cpumask.h>
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2016-11-23 00:03:09 +07:00
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#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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2015-04-11 03:15:59 +07:00
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#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
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struct qcom_scm_hdcp_req {
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u32 addr;
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u32 val;
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};
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2017-10-24 22:52:24 +07:00
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struct qcom_scm_vmperm {
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int vmid;
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int perm;
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};
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#define QCOM_SCM_VMID_HLOS 0x3
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#define QCOM_SCM_VMID_MSS_MSA 0xF
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2018-10-11 17:16:01 +07:00
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#define QCOM_SCM_VMID_WLAN 0x18
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#define QCOM_SCM_VMID_WLAN_CE 0x19
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2017-10-24 22:52:24 +07:00
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#define QCOM_SCM_PERM_READ 0x4
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#define QCOM_SCM_PERM_WRITE 0x2
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#define QCOM_SCM_PERM_EXEC 0x1
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#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
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#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
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2016-11-23 00:03:09 +07:00
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#if IS_ENABLED(CONFIG_QCOM_SCM)
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extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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2015-09-30 02:48:55 +07:00
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extern bool qcom_scm_is_available(void);
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2015-04-11 03:15:59 +07:00
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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2016-11-23 00:03:09 +07:00
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u32 *resp);
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2015-09-24 02:56:12 +07:00
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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2016-11-23 00:03:09 +07:00
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size_t size);
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2015-09-24 02:56:12 +07:00
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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2016-11-23 00:03:09 +07:00
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phys_addr_t size);
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2015-09-24 02:56:12 +07:00
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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2017-10-24 22:52:24 +07:00
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extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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2019-05-18 04:09:22 +07:00
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt);
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2015-03-03 06:30:30 +07:00
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extern void qcom_scm_cpu_power_down(u32 flags);
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2015-02-05 05:30:46 +07:00
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extern u32 qcom_scm_get_version(void);
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2017-01-17 12:24:15 +07:00
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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2017-03-14 22:18:03 +07:00
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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2017-03-14 22:18:04 +07:00
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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2017-08-15 05:46:17 +07:00
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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2016-11-23 00:03:09 +07:00
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#else
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2018-11-22 09:32:25 +07:00
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#include <linux/errno.h>
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2016-11-23 00:03:09 +07:00
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static inline
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENODEV;
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}
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static inline
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENODEV;
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}
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static inline bool qcom_scm_is_available(void) { return false; }
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static inline bool qcom_scm_hdcp_available(void) { return false; }
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static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp) { return -ENODEV; }
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static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size) { return -ENODEV; }
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static inline int
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qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
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static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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2018-06-12 20:23:13 +07:00
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static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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2019-05-18 04:09:22 +07:00
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt) { return -ENODEV; }
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2016-11-23 00:03:09 +07:00
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static inline void qcom_scm_cpu_power_down(u32 flags) {}
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static inline u32 qcom_scm_get_version(void) { return 0; }
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2017-01-17 12:24:15 +07:00
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static inline u32
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qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
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2017-03-14 22:18:03 +07:00
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static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
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2017-03-14 22:18:04 +07:00
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static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
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2017-08-15 05:46:17 +07:00
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static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
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static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
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2016-11-23 00:03:09 +07:00
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#endif
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2010-08-28 00:01:23 +07:00
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#endif
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