2015-06-01 18:13:55 +07:00
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include "clkc.h"
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2016-04-29 07:18:52 +07:00
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/*
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* Clock controller register offsets
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*
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* Register offsets from the HardKernel[0] data sheet are listed in comment
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* blocks below. Those offsets must be multiplied by 4 before adding them to
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* the base address to get the right value
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
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#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
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#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
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2015-06-01 18:13:55 +07:00
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#define MESON8B_REG_PLL_FIXED 0x0280
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#define MESON8B_REG_PLL_SYS 0x0300
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#define MESON8B_REG_PLL_VID 0x0320
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static const struct pll_rate_table sys_pll_rate_table[] = {
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PLL_RATE(312000000, 52, 1, 2),
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PLL_RATE(336000000, 56, 1, 2),
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PLL_RATE(360000000, 60, 1, 2),
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PLL_RATE(384000000, 64, 1, 2),
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PLL_RATE(408000000, 68, 1, 2),
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PLL_RATE(432000000, 72, 1, 2),
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PLL_RATE(456000000, 76, 1, 2),
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PLL_RATE(480000000, 80, 1, 2),
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PLL_RATE(504000000, 84, 1, 2),
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PLL_RATE(528000000, 88, 1, 2),
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PLL_RATE(552000000, 92, 1, 2),
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PLL_RATE(576000000, 96, 1, 2),
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PLL_RATE(600000000, 50, 1, 1),
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PLL_RATE(624000000, 52, 1, 1),
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PLL_RATE(648000000, 54, 1, 1),
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PLL_RATE(672000000, 56, 1, 1),
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PLL_RATE(696000000, 58, 1, 1),
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PLL_RATE(720000000, 60, 1, 1),
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PLL_RATE(744000000, 62, 1, 1),
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PLL_RATE(768000000, 64, 1, 1),
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PLL_RATE(792000000, 66, 1, 1),
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PLL_RATE(816000000, 68, 1, 1),
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PLL_RATE(840000000, 70, 1, 1),
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PLL_RATE(864000000, 72, 1, 1),
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PLL_RATE(888000000, 74, 1, 1),
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PLL_RATE(912000000, 76, 1, 1),
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PLL_RATE(936000000, 78, 1, 1),
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PLL_RATE(960000000, 80, 1, 1),
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PLL_RATE(984000000, 82, 1, 1),
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PLL_RATE(1008000000, 84, 1, 1),
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PLL_RATE(1032000000, 86, 1, 1),
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PLL_RATE(1056000000, 88, 1, 1),
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PLL_RATE(1080000000, 90, 1, 1),
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PLL_RATE(1104000000, 92, 1, 1),
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PLL_RATE(1128000000, 94, 1, 1),
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PLL_RATE(1152000000, 96, 1, 1),
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PLL_RATE(1176000000, 98, 1, 1),
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PLL_RATE(1200000000, 50, 1, 0),
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PLL_RATE(1224000000, 51, 1, 0),
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PLL_RATE(1248000000, 52, 1, 0),
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PLL_RATE(1272000000, 53, 1, 0),
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PLL_RATE(1296000000, 54, 1, 0),
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PLL_RATE(1320000000, 55, 1, 0),
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PLL_RATE(1344000000, 56, 1, 0),
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PLL_RATE(1368000000, 57, 1, 0),
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PLL_RATE(1392000000, 58, 1, 0),
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PLL_RATE(1416000000, 59, 1, 0),
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PLL_RATE(1440000000, 60, 1, 0),
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PLL_RATE(1464000000, 61, 1, 0),
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PLL_RATE(1488000000, 62, 1, 0),
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PLL_RATE(1512000000, 63, 1, 0),
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PLL_RATE(1536000000, 64, 1, 0),
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{ /* sentinel */ },
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};
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static const struct clk_div_table cpu_div_table[] = {
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{ .val = 1, .div = 1 },
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{ .val = 2, .div = 2 },
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{ .val = 3, .div = 3 },
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{ .val = 2, .div = 4 },
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{ .val = 3, .div = 6 },
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{ .val = 4, .div = 8 },
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{ .val = 5, .div = 10 },
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{ .val = 6, .div = 12 },
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{ .val = 7, .div = 14 },
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{ .val = 8, .div = 16 },
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{ /* sentinel */ },
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};
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PNAME(p_cpu_clk) = { "sys_pll" };
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PNAME(p_clk81) = { "fclk_div3", "fclk_div4", "fclk_div5" };
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PNAME(p_mali) = { "fclk_div3", "fclk_div4", "fclk_div5",
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"fclk_div7", "zero" };
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static u32 mux_table_clk81[] = { 6, 5, 7 };
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static u32 mux_table_mali[] = { 6, 5, 7, 4, 0 };
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static const struct composite_conf clk81_conf __initconst = {
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.mux_table = mux_table_clk81,
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.mux_flags = CLK_MUX_READ_ONLY,
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.mux_parm = PARM(0x00, 12, 3),
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.div_parm = PARM(0x00, 0, 7),
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.gate_parm = PARM(0x00, 7, 1),
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};
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static const struct composite_conf mali_conf __initconst = {
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.mux_table = mux_table_mali,
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.mux_parm = PARM(0x00, 9, 3),
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.div_parm = PARM(0x00, 0, 7),
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.gate_parm = PARM(0x00, 8, 1),
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};
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2016-04-29 02:00:52 +07:00
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static struct clk_fixed_rate meson8b_xtal = {
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.fixed_rate = 24000000,
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.hw.init = &(struct clk_init_data){
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.name = "xtal",
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.num_parents = 0,
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.ops = &clk_fixed_rate_ops,
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},
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};
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static struct clk_fixed_rate meson8b_zero = {
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.fixed_rate = 0,
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.hw.init = &(struct clk_init_data){
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.name = "zero",
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.num_parents = 0,
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.ops = &clk_fixed_rate_ops,
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},
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};
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2015-06-01 18:13:55 +07:00
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2016-04-29 02:01:42 +07:00
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static struct meson_clk_pll meson8b_fixed_pll = {
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.m = {
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.reg_off = MESON8B_REG_PLL_FIXED,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = MESON8B_REG_PLL_FIXED,
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.shift = 9,
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.width = 5,
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},
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.od = {
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.reg_off = MESON8B_REG_PLL_FIXED,
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.shift = 16,
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.width = 2,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "fixed_pll",
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.ops = &meson_clk_pll_ro_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct meson_clk_pll meson8b_vid_pll = {
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.m = {
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.reg_off = MESON8B_REG_PLL_VID,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = MESON8B_REG_PLL_VID,
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.shift = 9,
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.width = 5,
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},
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.od = {
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.reg_off = MESON8B_REG_PLL_VID,
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.shift = 16,
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.width = 2,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "vid_pll",
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.ops = &meson_clk_pll_ro_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct meson_clk_pll meson8b_sys_pll = {
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.m = {
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.reg_off = MESON8B_REG_PLL_SYS,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = MESON8B_REG_PLL_SYS,
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.shift = 9,
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.width = 5,
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},
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.od = {
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.reg_off = MESON8B_REG_PLL_SYS,
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.shift = 16,
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.width = 2,
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},
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.rate_table = sys_pll_rate_table,
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.rate_count = ARRAY_SIZE(sys_pll_rate_table),
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "sys_pll",
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.ops = &meson_clk_pll_ops,
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.parent_names = (const char *[]){ "xtal" },
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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2016-04-29 02:01:58 +07:00
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static struct clk_fixed_factor meson8b_fclk_div2 = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div2",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div3 = {
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.mult = 1,
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.div = 3,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div3",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div4 = {
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.mult = 1,
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.div = 4,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div4",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div5 = {
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.mult = 1,
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.div = 5,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div5",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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static struct clk_fixed_factor meson8b_fclk_div7 = {
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.mult = 1,
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.div = 7,
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.hw.init = &(struct clk_init_data){
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.name = "fclk_div7",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "fixed_pll" },
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.num_parents = 1,
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},
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};
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2015-06-01 18:13:55 +07:00
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static const struct clk_conf meson8b_clk_confs[] __initconst = {
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CPU(MESON8B_REG_SYS_CPU_CNTL1, CLKID_CPUCLK, "a5_clk", p_cpu_clk,
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cpu_div_table),
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COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81,
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CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf),
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COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali,
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CLK_IGNORE_UNUSED, &mali_conf),
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};
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2016-04-29 02:00:52 +07:00
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/*
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* FIXME we cannot register two providers w/o breaking things. Luckily only
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* clk81 is actually used by any drivers. Convert clk81 to use
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* clk_hw_onecell_data last and flip the switch to call of_clk_add_hw_provider
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* instead of of_clk_add_provider in the clk81 conversion patch to keep from
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* breaking bisect. Then delete this comment ;-)
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*/
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static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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.hws = {
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[CLKID_XTAL] = &meson8b_xtal.hw,
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[CLKID_ZERO] = &meson8b_zero.hw,
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2016-04-29 02:01:42 +07:00
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[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
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[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
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[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
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2016-04-29 02:01:58 +07:00
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[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
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[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
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[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
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[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
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[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
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2016-04-29 02:00:52 +07:00
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},
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.num = CLK_NR_CLKS,
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};
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2016-04-29 02:01:42 +07:00
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static struct meson_clk_pll *const meson8b_clk_plls[] = {
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&meson8b_fixed_pll,
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&meson8b_vid_pll,
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&meson8b_sys_pll,
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};
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2015-06-01 18:13:55 +07:00
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static void __init meson8b_clkc_init(struct device_node *np)
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{
|
|
|
|
void __iomem *clk_base;
|
2016-04-29 02:01:42 +07:00
|
|
|
int ret, clkid, i;
|
2015-06-01 18:13:55 +07:00
|
|
|
|
|
|
|
if (!meson_clk_init(np, CLK_NR_CLKS))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Generic clocks and PLLs */
|
|
|
|
clk_base = of_iomap(np, 1);
|
|
|
|
if (!clk_base) {
|
|
|
|
pr_err("%s: Unable to map clk base\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-04-29 02:01:42 +07:00
|
|
|
/* Populate base address for PLLs */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
|
|
|
|
meson8b_clk_plls[i]->base = clk_base;
|
|
|
|
|
2016-04-29 02:00:52 +07:00
|
|
|
/*
|
|
|
|
* register all clks
|
|
|
|
* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
|
|
|
|
*/
|
|
|
|
for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
|
|
|
|
/* array might be sparse */
|
|
|
|
if (!meson8b_hw_onecell_data.hws[clkid])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* FIXME convert to devm_clk_register */
|
|
|
|
ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[clkid]);
|
|
|
|
if (ret)
|
|
|
|
goto unregister;
|
|
|
|
}
|
|
|
|
|
2015-06-01 18:13:55 +07:00
|
|
|
meson_clk_register_clks(meson8b_clk_confs,
|
|
|
|
ARRAY_SIZE(meson8b_clk_confs),
|
|
|
|
clk_base);
|
2016-04-29 02:00:52 +07:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* FIXME remove after converting to platform_driver/devm_clk_register */
|
|
|
|
unregister:
|
|
|
|
for (clkid = CLK_NR_CLKS - 1; clkid >= 0; clkid--)
|
|
|
|
clk_hw_unregister(meson8b_hw_onecell_data.hws[clkid]);
|
2015-06-01 18:13:55 +07:00
|
|
|
}
|
|
|
|
CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);
|