2013-10-08 14:25:26 +07:00
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/*
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* HDMI PLL
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*
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* Copyright (C) 2013 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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2013-11-14 18:46:32 +07:00
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#define DSS_SUBSYS_NAME "HDMIPLL"
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2013-10-08 14:25:26 +07:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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2014-10-22 19:02:17 +07:00
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#include <linux/clk.h>
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2013-10-08 14:25:26 +07:00
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#include <video/omapdss.h>
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#include "dss.h"
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2013-09-12 19:15:57 +07:00
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#include "hdmi.h"
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2013-10-08 14:25:26 +07:00
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
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{
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#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
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hdmi_read_reg(pll->base, r))
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DUMPPLL(PLLCTRL_PLL_CONTROL);
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DUMPPLL(PLLCTRL_PLL_STATUS);
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DUMPPLL(PLLCTRL_PLL_GO);
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DUMPPLL(PLLCTRL_CFG1);
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DUMPPLL(PLLCTRL_CFG2);
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DUMPPLL(PLLCTRL_CFG3);
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DUMPPLL(PLLCTRL_SSC_CFG1);
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DUMPPLL(PLLCTRL_SSC_CFG2);
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DUMPPLL(PLLCTRL_CFG4);
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}
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2014-10-22 19:02:17 +07:00
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void hdmi_pll_compute(struct hdmi_pll_data *pll,
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unsigned long target_tmds, struct dss_pll_clock_info *pi)
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2013-10-08 14:25:26 +07:00
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{
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2014-09-15 19:40:47 +07:00
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unsigned long fint, clkdco, clkout;
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unsigned long target_bitclk, target_clkdco;
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unsigned long min_dco;
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unsigned n, m, mf, m2, sd;
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2014-10-22 19:02:17 +07:00
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unsigned long clkin;
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const struct dss_pll_hw *hw = pll->pll.hw;
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clkin = clk_get_rate(pll->pll.clkin);
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2014-09-15 19:40:47 +07:00
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DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
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target_bitclk = target_tmds * 10;
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2013-10-08 14:25:26 +07:00
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2014-09-15 19:40:47 +07:00
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/* Fint */
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2014-10-22 19:02:17 +07:00
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n = DIV_ROUND_UP(clkin, hw->fint_max);
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2014-09-15 19:40:47 +07:00
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fint = clkin / n;
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2013-10-08 14:25:26 +07:00
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2014-09-15 19:40:47 +07:00
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/* adjust m2 so that the clkdco will be high enough */
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2014-10-22 19:02:17 +07:00
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min_dco = roundup(hw->clkdco_min, fint);
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2014-09-15 19:40:47 +07:00
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m2 = DIV_ROUND_UP(min_dco, target_bitclk);
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if (m2 == 0)
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m2 = 1;
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2013-10-08 14:25:26 +07:00
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2014-09-15 19:40:47 +07:00
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target_clkdco = target_bitclk * m2;
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m = target_clkdco / fint;
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2013-10-08 14:25:26 +07:00
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2014-09-15 19:40:47 +07:00
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clkdco = fint * m;
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2013-10-08 14:25:26 +07:00
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2014-09-15 19:40:47 +07:00
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/* adjust clkdco with fractional mf */
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if (WARN_ON(target_clkdco - clkdco > fint))
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mf = 0;
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2013-09-23 16:42:34 +07:00
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else
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2014-09-15 19:40:47 +07:00
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mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
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if (mf > 0)
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clkdco += (u32)div_u64((u64)mf * fint, 262144);
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2013-10-08 14:25:26 +07:00
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2014-09-15 19:40:47 +07:00
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clkout = clkdco / m2;
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/* sigma-delta */
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sd = DIV_ROUND_UP(fint * m, 250000000);
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DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
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n, m, mf, m2, sd);
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DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
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2014-10-22 19:02:17 +07:00
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pi->n = n;
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pi->m = m;
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pi->mf = mf;
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pi->mX[0] = m2;
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pi->sd = sd;
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2014-09-15 19:40:47 +07:00
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2014-10-22 19:02:17 +07:00
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pi->fint = fint;
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2014-09-15 19:40:47 +07:00
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pi->clkdco = clkdco;
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2014-10-22 19:02:17 +07:00
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pi->clkout[0] = clkout;
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2013-10-08 14:25:26 +07:00
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}
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2014-10-22 19:02:17 +07:00
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static int hdmi_pll_enable(struct dss_pll *dsspll)
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2013-10-08 14:25:26 +07:00
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{
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2014-10-22 19:02:17 +07:00
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struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
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2014-10-16 19:31:38 +07:00
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struct hdmi_wp_data *wp = pll->wp;
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2013-10-08 14:25:26 +07:00
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u16 r = 0;
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2014-12-31 16:26:18 +07:00
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dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
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2013-10-08 14:25:26 +07:00
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r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
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if (r)
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return r;
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return 0;
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}
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2014-10-22 19:02:17 +07:00
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static void hdmi_pll_disable(struct dss_pll *dsspll)
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2013-10-08 14:25:26 +07:00
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{
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2014-10-22 19:02:17 +07:00
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struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
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2014-10-16 19:31:38 +07:00
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struct hdmi_wp_data *wp = pll->wp;
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2013-10-08 14:25:26 +07:00
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hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
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2014-12-31 16:26:18 +07:00
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dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
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2013-10-08 14:25:26 +07:00
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}
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2014-10-22 19:02:17 +07:00
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static const struct dss_pll_ops dsi_pll_ops = {
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.enable = hdmi_pll_enable,
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.disable = hdmi_pll_disable,
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.set_config = dss_pll_write_config_type_b,
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};
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static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
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.n_max = 255,
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.m_min = 20,
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.m_max = 4095,
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.mX_max = 127,
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.fint_min = 500000,
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.fint_max = 2500000,
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.clkdco_min = 500000000,
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.clkdco_low = 1000000000,
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.clkdco_max = 2000000000,
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.n_msb = 8,
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.n_lsb = 1,
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.m_msb = 20,
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.m_lsb = 9,
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.mX_msb[0] = 24,
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.mX_lsb[0] = 18,
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.has_selfreqdco = true,
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2013-09-23 16:42:34 +07:00
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};
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2014-10-22 19:02:17 +07:00
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static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
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.n_max = 255,
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.m_min = 20,
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.m_max = 2045,
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.mX_max = 127,
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.fint_min = 620000,
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.fint_max = 2500000,
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.clkdco_min = 750000000,
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.clkdco_low = 1500000000,
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.clkdco_max = 2500000000UL,
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.n_msb = 8,
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.n_lsb = 1,
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.m_msb = 20,
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.m_lsb = 9,
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.mX_msb[0] = 24,
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.mX_lsb[0] = 18,
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.has_selfreqdco = true,
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.has_refsel = true,
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2013-09-23 16:42:34 +07:00
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};
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2014-10-22 19:02:17 +07:00
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static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll)
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2013-09-23 16:42:34 +07:00
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{
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2014-10-22 19:02:17 +07:00
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struct dss_pll *pll = &hpll->pll;
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struct clk *clk;
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int r;
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2013-09-23 16:42:34 +07:00
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2014-10-22 19:02:17 +07:00
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clk = devm_clk_get(&pdev->dev, "sys_clk");
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if (IS_ERR(clk)) {
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DSSERR("can't get sys_clk\n");
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return PTR_ERR(clk);
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2013-09-23 16:42:34 +07:00
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}
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2014-10-22 19:02:17 +07:00
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pll->name = "hdmi";
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2015-01-02 15:05:33 +07:00
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pll->id = DSS_PLL_HDMI;
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2014-10-22 19:02:17 +07:00
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pll->base = hpll->base;
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pll->clkin = clk;
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2013-09-23 16:42:34 +07:00
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switch (omapdss_get_version()) {
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case OMAPDSS_VER_OMAP4430_ES1:
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case OMAPDSS_VER_OMAP4430_ES2:
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case OMAPDSS_VER_OMAP4:
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2014-10-22 19:02:17 +07:00
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pll->hw = &dss_omap4_hdmi_pll_hw;
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2013-09-23 16:42:34 +07:00
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break;
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case OMAPDSS_VER_OMAP5:
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2014-12-31 16:26:18 +07:00
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case OMAPDSS_VER_DRA7xx:
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2014-10-22 19:02:17 +07:00
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pll->hw = &dss_omap5_hdmi_pll_hw;
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2013-09-23 16:42:34 +07:00
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break;
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default:
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return -ENODEV;
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}
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2014-10-22 19:02:17 +07:00
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pll->ops = &dsi_pll_ops;
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r = dss_pll_register(pll);
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if (r)
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return r;
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2013-09-23 16:42:34 +07:00
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return 0;
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}
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2014-10-16 19:31:38 +07:00
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
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struct hdmi_wp_data *wp)
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2013-10-08 14:25:26 +07:00
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{
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2013-09-23 16:42:34 +07:00
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int r;
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2013-10-08 14:25:26 +07:00
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struct resource *res;
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2014-10-16 19:31:38 +07:00
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pll->wp = wp;
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2013-12-17 19:41:14 +07:00
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
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2013-10-08 14:25:26 +07:00
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if (!res) {
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2014-04-28 20:11:01 +07:00
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DSSERR("can't get PLL mem resource\n");
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return -EINVAL;
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2013-10-08 14:25:26 +07:00
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}
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2014-04-28 20:11:01 +07:00
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pll->base = devm_ioremap_resource(&pdev->dev, res);
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2014-05-23 18:50:09 +07:00
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if (IS_ERR(pll->base)) {
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2013-10-08 14:25:26 +07:00
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DSSERR("can't ioremap PLLCTRL\n");
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2014-05-23 18:50:09 +07:00
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return PTR_ERR(pll->base);
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2013-10-08 14:25:26 +07:00
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}
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2014-10-22 19:02:17 +07:00
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r = dsi_init_pll_data(pdev, pll);
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if (r) {
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DSSERR("failed to init HDMI PLL\n");
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return r;
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}
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2013-10-08 14:25:26 +07:00
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return 0;
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}
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2014-10-22 19:02:17 +07:00
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void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
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{
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struct dss_pll *pll = &hpll->pll;
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dss_pll_unregister(pll);
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}
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