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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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75 lines
2.1 KiB
Plaintext
75 lines
2.1 KiB
Plaintext
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/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include "arm-realview-eb-mp.dtsi"
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/ {
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model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C";
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arm,hbi = <0x146>;
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/*
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* This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
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* Reference: ARM DUI 0318F
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*
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* To run this machine with QEMU, specify the following:
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* qemu-system-arm -M realview-eb-mpcore -smp cpus=4
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "arm,realview-smp";
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MP11_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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MP11_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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MP11_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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MP11_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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};
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&pmu {
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interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
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};
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