2005-04-17 05:20:36 +07:00
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/*
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* Dump R4x00 TLB for debugging purposes.
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*
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* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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2015-05-19 15:50:32 +07:00
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#include <asm/hazards.h>
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2005-04-17 05:20:36 +07:00
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#include <asm/mipsregs.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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2007-07-11 22:51:00 +07:00
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#include <asm/tlbdebug.h>
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2005-04-17 05:20:36 +07:00
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2015-07-15 22:17:43 +07:00
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void dump_tlb_regs(void)
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{
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const int field = 2 * sizeof(unsigned long);
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pr_info("Index : %0x\n", read_c0_index());
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pr_info("PageMask : %0x\n", read_c0_pagemask());
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2016-05-11 21:50:32 +07:00
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if (cpu_has_guestid)
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pr_info("GuestCtl1: %0x\n", read_c0_guestctl1());
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2015-07-15 22:17:43 +07:00
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pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
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pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
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pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
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pr_info("Wired : %0x\n", read_c0_wired());
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2015-07-15 22:17:46 +07:00
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switch (current_cpu_type()) {
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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case CPU_R16000:
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pr_info("FrameMask: %0x\n", read_c0_framemask());
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break;
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}
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2015-07-15 22:17:45 +07:00
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if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa)
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pr_info("PageGrain: %0x\n", read_c0_pagegrain());
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2015-07-15 22:17:43 +07:00
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if (cpu_has_htw) {
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pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
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pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());
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pr_info("PWCtl : %0x\n", read_c0_pwctl());
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}
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}
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2005-04-17 05:20:36 +07:00
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static inline const char *msk2str(unsigned int mask)
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{
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switch (mask) {
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case PM_4K: return "4kb";
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case PM_16K: return "16kb";
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case PM_64K: return "64kb";
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case PM_256K: return "256kb";
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2009-04-02 19:07:10 +07:00
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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case PM_8K: return "8kb";
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case PM_32K: return "32kb";
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case PM_128K: return "128kb";
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case PM_512K: return "512kb";
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case PM_2M: return "2Mb";
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case PM_8M: return "8Mb";
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case PM_32M: return "32Mb";
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#endif
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2005-04-17 05:20:36 +07:00
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#ifndef CONFIG_CPU_VR41XX
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case PM_1M: return "1Mb";
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case PM_4M: return "4Mb";
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case PM_16M: return "16Mb";
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case PM_64M: return "64Mb";
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case PM_256M: return "256Mb";
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2008-10-23 23:27:57 +07:00
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case PM_1G: return "1Gb";
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2005-04-17 05:20:36 +07:00
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#endif
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}
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2007-06-01 22:21:30 +07:00
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return "";
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2005-04-17 05:20:36 +07:00
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}
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2007-06-01 22:30:25 +07:00
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static void dump_tlb(int first, int last)
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2005-04-17 05:20:36 +07:00
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{
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2007-06-01 22:21:30 +07:00
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unsigned long s_entryhi, entryhi, asid;
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MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:
Index: 253 pgmask=16kb va=77b18000 asid=75
[pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]
The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.
Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:
Index: 226 pgmask=16kb va=77be0000 asid=79
[ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-19 15:50:37 +07:00
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unsigned long long entrylo0, entrylo1, pa;
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2016-05-11 21:50:31 +07:00
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unsigned int s_index, s_pagemask, s_guestctl1 = 0;
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unsigned int pagemask, guestctl1 = 0, c0, c1, i;
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2016-05-06 20:36:23 +07:00
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unsigned long asidmask = cpu_asid_mask(¤t_cpu_data);
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int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4);
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2015-05-19 15:50:33 +07:00
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#ifdef CONFIG_32BIT
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2015-05-19 15:50:38 +07:00
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bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
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int pwidth = xpa ? 11 : 8;
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int vwidth = 8;
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2015-05-19 15:50:33 +07:00
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#else
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2015-05-19 15:50:38 +07:00
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bool xpa = false;
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int pwidth = 11;
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int vwidth = 11;
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2015-05-19 15:50:33 +07:00
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#endif
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2005-04-17 05:20:36 +07:00
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2012-10-17 06:01:20 +07:00
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s_pagemask = read_c0_pagemask();
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2005-04-17 05:20:36 +07:00
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s_entryhi = read_c0_entryhi();
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s_index = read_c0_index();
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2016-05-06 20:36:23 +07:00
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asid = s_entryhi & asidmask;
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2016-05-11 21:50:31 +07:00
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if (cpu_has_guestid)
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s_guestctl1 = read_c0_guestctl1();
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2005-04-17 05:20:36 +07:00
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for (i = first; i <= last; i++) {
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write_c0_index(i);
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2015-05-19 15:50:32 +07:00
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mtc0_tlbr_hazard();
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2005-04-17 05:20:36 +07:00
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tlb_read();
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2015-05-19 15:50:32 +07:00
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tlb_read_hazard();
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2005-04-17 05:20:36 +07:00
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pagemask = read_c0_pagemask();
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2013-01-22 18:59:30 +07:00
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entryhi = read_c0_entryhi();
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2005-04-17 05:20:36 +07:00
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entrylo0 = read_c0_entrylo0();
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entrylo1 = read_c0_entrylo1();
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2016-05-11 21:50:31 +07:00
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if (cpu_has_guestid)
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guestctl1 = read_c0_guestctl1();
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2005-04-17 05:20:36 +07:00
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2015-05-19 15:50:36 +07:00
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/* EHINV bit marks entire entry as invalid */
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if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
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continue;
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2015-05-19 15:50:33 +07:00
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/*
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* Prior to tlbinv, unused entries have a virtual address of
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* CKSEG0.
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*/
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if ((entryhi & ~0x1ffffUL) == CKSEG0)
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continue;
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2015-05-19 15:50:35 +07:00
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/*
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* ASID takes effect in absence of G (global) bit.
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* We check both G bits, even though architecturally they should
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* match one another, because some revisions of the SB1 core may
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* leave only a single G bit set after a machine check exception
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* due to duplicate TLB entry.
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*/
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2015-07-15 22:17:47 +07:00
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if (!((entrylo0 | entrylo1) & ENTRYLO_G) &&
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2016-05-06 20:36:23 +07:00
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(entryhi & asidmask) != asid)
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2015-05-19 15:50:33 +07:00
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continue;
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/*
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* Only print entries in use
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*/
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printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
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2005-04-17 05:20:36 +07:00
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2015-07-15 22:17:47 +07:00
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c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
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c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
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2005-04-17 05:20:36 +07:00
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2016-10-22 02:06:40 +07:00
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pr_cont("va=%0*lx asid=%0*lx",
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vwidth, (entryhi & ~0x1fffUL),
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asidwidth, entryhi & asidmask);
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2016-05-11 21:50:31 +07:00
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if (cpu_has_guestid)
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2016-10-22 02:06:40 +07:00
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pr_cont(" gid=%02lx",
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(guestctl1 & MIPS_GCTL1_RID)
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2016-05-11 21:50:31 +07:00
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>> MIPS_GCTL1_RID_SHIFT);
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MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:
Index: 253 pgmask=16kb va=77b18000 asid=75
[pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]
The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.
Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:
Index: 226 pgmask=16kb va=77be0000 asid=79
[ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-19 15:50:37 +07:00
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/* RI/XI are in awkward places, so mask them off separately */
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pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
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2015-05-19 15:50:38 +07:00
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if (xpa)
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pa |= (unsigned long long)readx_c0_entrylo0() << 30;
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MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:
Index: 253 pgmask=16kb va=77b18000 asid=75
[pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]
The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.
Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:
Index: 226 pgmask=16kb va=77be0000 asid=79
[ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-19 15:50:37 +07:00
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pa = (pa << 6) & PAGE_MASK;
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2016-10-22 02:06:40 +07:00
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pr_cont("\n\t[");
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MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:
Index: 253 pgmask=16kb va=77b18000 asid=75
[pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]
The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.
Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:
Index: 226 pgmask=16kb va=77be0000 asid=79
[ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-19 15:50:37 +07:00
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if (cpu_has_rixi)
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2016-10-22 02:06:40 +07:00
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pr_cont("ri=%d xi=%d ",
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(entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
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(entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
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pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d] [",
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pwidth, pa, c0,
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(entrylo0 & ENTRYLO_D) ? 1 : 0,
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(entrylo0 & ENTRYLO_V) ? 1 : 0,
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(entrylo0 & ENTRYLO_G) ? 1 : 0);
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MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:
Index: 253 pgmask=16kb va=77b18000 asid=75
[pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]
The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.
Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:
Index: 226 pgmask=16kb va=77be0000 asid=79
[ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-19 15:50:37 +07:00
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/* RI/XI are in awkward places, so mask them off separately */
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pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
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2015-05-19 15:50:38 +07:00
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if (xpa)
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pa |= (unsigned long long)readx_c0_entrylo1() << 30;
|
MIPS: dump_tlb: Take RI/XI bits into account
The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:
Index: 253 pgmask=16kb va=77b18000 asid=75
[pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]
The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.
Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:
Index: 226 pgmask=16kb va=77be0000 asid=79
[ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-19 15:50:37 +07:00
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pa = (pa << 6) & PAGE_MASK;
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if (cpu_has_rixi)
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2016-10-22 02:06:40 +07:00
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pr_cont("ri=%d xi=%d ",
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(entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
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(entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
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pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
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pwidth, pa, c1,
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(entrylo1 & ENTRYLO_D) ? 1 : 0,
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(entrylo1 & ENTRYLO_V) ? 1 : 0,
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(entrylo1 & ENTRYLO_G) ? 1 : 0);
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2005-04-17 05:20:36 +07:00
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}
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printk("\n");
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write_c0_entryhi(s_entryhi);
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write_c0_index(s_index);
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2012-10-17 06:01:20 +07:00
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write_c0_pagemask(s_pagemask);
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2016-05-11 21:50:31 +07:00
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if (cpu_has_guestid)
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write_c0_guestctl1(s_guestctl1);
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2005-04-17 05:20:36 +07:00
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}
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void dump_tlb_all(void)
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{
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dump_tlb(0, current_cpu_data.tlbsize - 1);
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}
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