2006-08-30 05:12:40 +07:00
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/*
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* pata_ns87410.c - National Semiconductor 87410 PATA for new ATA layer
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* (C) 2006 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_ns87410"
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2007-03-09 19:24:15 +07:00
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#define DRV_VERSION "0.4.6"
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2006-08-30 05:12:40 +07:00
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/**
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* ns87410_pre_reset - probe begin
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* @ap: ATA port
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 14:50:52 +07:00
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* @deadline: deadline jiffies for the operation
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2006-08-30 05:12:40 +07:00
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*
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2007-03-09 19:24:15 +07:00
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* Check enabled ports
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2006-08-30 05:12:40 +07:00
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*/
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 14:50:52 +07:00
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static int ns87410_pre_reset(struct ata_port *ap, unsigned long deadline)
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2006-08-30 05:12:40 +07:00
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const struct pci_bits ns87410_enable_bits[] = {
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{ 0x43, 1, 0x08, 0x08 },
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{ 0x47, 1, 0x08, 0x08 }
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};
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2006-09-26 23:53:38 +07:00
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if (!pci_test_config_bits(pdev, &ns87410_enable_bits[ap->port_no]))
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return -ENOENT;
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 14:50:52 +07:00
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return ata_std_prereset(ap, deadline);
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2006-08-30 05:12:40 +07:00
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}
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/**
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* ns87410_error_handler - probe reset
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* @ap: ATA port
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*
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* Perform the ATA probe and bus reset sequence plus specific handling
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* for this hardware. The MPIIX has the enable bits in a different place
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* to PIIX4 and friends. As a pure PIO device it has no cable detect
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*/
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static void ns87410_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, ns87410_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* ns87410_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Program timing data. This is kept per channel not per device,
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* and only affects the data port.
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*/
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static void ns87410_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x40 + 4 * ap->port_no;
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u8 idetcr, idefr;
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struct ata_timing at;
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static const u8 activebits[15] = {
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0, 1, 2, 3, 4,
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5, 5, 6, 6, 6,
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6, 7, 7, 7, 7
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};
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static const u8 recoverbits[12] = {
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0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 7, 7
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};
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pci_read_config_byte(pdev, port + 3, &idefr);
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if (ata_pio_need_iordy(adev))
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idefr |= 0x04; /* IORDY enable */
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else
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idefr &= ~0x04;
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if (ata_timing_compute(adev, adev->pio_mode, &at, 30303, 1) < 0) {
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dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", adev->pio_mode);
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return;
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}
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at.active = FIT(at.active, 2, 16) - 2;
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at.setup = FIT(at.setup, 1, 4) - 1;
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at.recover = FIT(at.recover, 1, 12) - 1;
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idetcr = (at.setup << 6) | (recoverbits[at.recover] << 3) | activebits[at.active];
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pci_write_config_byte(pdev, port, idetcr);
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pci_write_config_byte(pdev, port + 3, idefr);
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/* We use ap->private_data as a pointer to the device currently
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loaded for timing */
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ap->private_data = adev;
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}
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/**
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* ns87410_qc_issue_prot - command issue
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* @qc: command pending
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*
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* Called when the libata layer is about to issue a command. We wrap
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* this interface so that we can load the correct ATA timings if
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* neccessary.
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*/
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static unsigned int ns87410_qc_issue_prot(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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/* If modes have been configured and the channel data is not loaded
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then load it. We have to check if pio_mode is set as the core code
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does not set adev->pio_mode to XFER_PIO_0 while probing as would be
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logical */
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if (adev->pio_mode && adev != ap->private_data)
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ns87410_set_piomode(ap, adev);
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return ata_qc_issue_prot(qc);
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}
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static struct scsi_host_template ns87410_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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2006-11-29 09:26:47 +07:00
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.slave_destroy = ata_scsi_slave_destroy,
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2006-08-30 05:12:40 +07:00
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations ns87410_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = ns87410_set_piomode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ns87410_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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2007-03-09 19:24:15 +07:00
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.cable_detect = ata_cable_40wire,
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2006-08-30 05:12:40 +07:00
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.qc_prep = ata_qc_prep,
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.qc_issue = ns87410_qc_issue_prot,
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2006-09-27 16:41:13 +07:00
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2007-02-01 13:06:36 +07:00
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.data_xfer = ata_data_xfer,
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2006-08-30 05:12:40 +07:00
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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2007-01-26 14:27:58 +07:00
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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2006-08-30 05:12:40 +07:00
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.port_start = ata_port_start,
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};
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static int ns87410_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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2007-05-04 17:43:58 +07:00
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static const struct ata_port_info info = {
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2006-08-30 05:12:40 +07:00
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.sht = &ns87410_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x0F,
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.port_ops = &ns87410_port_ops
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};
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2007-05-04 17:43:58 +07:00
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const struct ata_port_info *ppi[] = { &info, NULL };
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return ata_pci_init_one(dev, ppi);
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2006-08-30 05:12:40 +07:00
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}
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static const struct pci_device_id ns87410[] = {
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2006-09-29 07:21:59 +07:00
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{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87410), },
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{ },
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2006-08-30 05:12:40 +07:00
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};
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static struct pci_driver ns87410_pci_driver = {
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2006-09-29 07:21:59 +07:00
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.name = DRV_NAME,
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2006-08-30 05:12:40 +07:00
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.id_table = ns87410,
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.probe = ns87410_init_one,
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2006-11-22 23:57:36 +07:00
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.remove = ata_pci_remove_one,
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2007-03-02 15:31:26 +07:00
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#ifdef CONFIG_PM
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2006-11-22 23:57:36 +07:00
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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2007-03-02 15:31:26 +07:00
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#endif
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2006-08-30 05:12:40 +07:00
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};
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static int __init ns87410_init(void)
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{
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return pci_register_driver(&ns87410_pci_driver);
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}
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static void __exit ns87410_exit(void)
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{
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pci_unregister_driver(&ns87410_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Nat Semi 87410");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, ns87410);
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MODULE_VERSION(DRV_VERSION);
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module_init(ns87410_init);
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module_exit(ns87410_exit);
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