2011-10-04 17:19:01 +07:00
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/* exynos_drm_drv.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Authors:
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* Inki Dae <inki.dae@samsung.com>
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Seung-Woo Kim <sw0312.kim@samsung.com>
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*
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2012-12-18 00:30:17 +07:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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2011-10-04 17:19:01 +07:00
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*/
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#ifndef _EXYNOS_DRM_DRV_H_
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#define _EXYNOS_DRM_DRV_H_
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2014-10-31 21:17:38 +07:00
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#include <drm/drmP.h>
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2011-11-12 14:57:42 +07:00
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#include <linux/module.h>
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2011-10-04 17:19:01 +07:00
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2012-03-21 08:55:26 +07:00
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#define MAX_CRTC 3
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2011-12-08 15:54:07 +07:00
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#define MAX_PLANE 5
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2012-03-21 08:55:26 +07:00
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#define MAX_FB_BUFFER 4
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2011-10-04 17:19:01 +07:00
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2015-10-12 20:07:48 +07:00
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#define DEFAULT_WIN 0
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2014-11-04 03:20:29 +07:00
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#define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base)
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2014-11-04 03:13:27 +07:00
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#define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base)
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2014-10-31 21:32:32 +07:00
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2011-10-04 17:19:01 +07:00
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/* this enumerates display type. */
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enum exynos_drm_output_type {
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EXYNOS_DISPLAY_TYPE_NONE,
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/* RGB or CPU Interface. */
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EXYNOS_DISPLAY_TYPE_LCD,
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/* HDMI Interface. */
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EXYNOS_DISPLAY_TYPE_HDMI,
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2012-03-21 08:55:26 +07:00
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/* Virtual Display Interface. */
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EXYNOS_DISPLAY_TYPE_VIDI,
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2011-10-04 17:19:01 +07:00
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};
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2015-11-30 20:53:22 +07:00
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struct exynos_drm_rect {
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unsigned int x, y;
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unsigned int w, h;
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};
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2011-10-04 17:19:01 +07:00
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/*
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2015-11-30 20:53:22 +07:00
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* Exynos drm plane state structure.
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2011-10-04 17:19:01 +07:00
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*
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2015-11-30 20:53:22 +07:00
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* @base: plane_state object (contains drm_framebuffer pointer)
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* @src: rectangle of the source image data to be displayed (clipped to
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* visible part).
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* @crtc: rectangle of the target image position on hardware screen
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* (clipped to visible part).
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2015-04-07 13:59:39 +07:00
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* @h_ratio: horizontal scaling ratio, 16.16 fixed point
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* @v_ratio: vertical scaling ratio, 16.16 fixed point
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2015-11-30 20:53:22 +07:00
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*
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* this structure consists plane state data that will be applied to hardware
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* specific overlay info.
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*/
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struct exynos_drm_plane_state {
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struct drm_plane_state base;
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struct exynos_drm_rect crtc;
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struct exynos_drm_rect src;
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unsigned int h_ratio;
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unsigned int v_ratio;
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};
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static inline struct exynos_drm_plane_state *
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to_exynos_plane_state(struct drm_plane_state *state)
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{
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return container_of(state, struct exynos_drm_plane_state, base);
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}
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/*
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* Exynos drm common overlay structure.
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*
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* @base: plane object
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2015-12-16 19:21:42 +07:00
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* @index: hardware index of the overlay layer
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2011-10-04 17:19:01 +07:00
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*
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* this structure is common to exynos SoC and its contents would be copied
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* to hardware specific overlay info.
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*/
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2014-11-04 03:13:27 +07:00
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struct exynos_drm_plane {
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struct drm_plane base;
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2015-11-30 20:53:25 +07:00
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const struct exynos_drm_plane_config *config;
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2015-12-16 19:21:42 +07:00
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unsigned int index;
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2011-10-04 17:19:01 +07:00
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};
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2015-11-30 20:53:26 +07:00
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#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0)
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#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1)
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2015-12-16 19:21:43 +07:00
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#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2)
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2017-08-22 21:19:37 +07:00
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#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3)
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2015-11-30 20:53:26 +07:00
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2015-11-30 20:53:25 +07:00
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/*
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* Exynos DRM plane configuration structure.
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*
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2015-12-16 19:21:43 +07:00
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* @zpos: initial z-position of the plane.
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2015-11-30 20:53:25 +07:00
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* @type: type of the plane (primary, cursor or overlay).
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* @pixel_formats: supported pixel formats.
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* @num_pixel_formats: number of elements in 'pixel_formats'.
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* @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*)
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*/
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struct exynos_drm_plane_config {
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unsigned int zpos;
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enum drm_plane_type type;
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const uint32_t *pixel_formats;
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unsigned int num_pixel_formats;
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unsigned int capabilities;
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};
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2011-10-04 17:19:01 +07:00
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/*
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2015-01-18 16:16:23 +07:00
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* Exynos drm crtc ops
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2011-10-04 17:19:01 +07:00
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*
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2015-06-01 22:04:55 +07:00
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* @enable: enable the device
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* @disable: disable the device
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2011-10-04 17:19:01 +07:00
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* @enable_vblank: specific driver callback for enabling vblank interrupt.
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* @disable_vblank: specific driver callback for disabling vblank interrupt.
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2017-08-24 20:33:56 +07:00
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* @mode_valid: specific driver callback for mode validation
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2015-10-26 19:03:39 +07:00
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* @atomic_check: validate state
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2016-01-05 19:52:51 +07:00
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* @atomic_begin: prepare device to receive an update
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* @atomic_flush: mark the end of device update
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2015-08-03 12:38:05 +07:00
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* @update_plane: apply hardware specific overlay data to registers.
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* @disable_plane: disable hardware specific overlay.
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2014-07-17 16:01:19 +07:00
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* @te_handler: trigger to transfer video image at the tearing effect
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* synchronization signal if there is a page flip request.
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2011-10-04 17:19:01 +07:00
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*/
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2015-01-18 16:16:23 +07:00
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struct exynos_drm_crtc;
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struct exynos_drm_crtc_ops {
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2015-06-01 22:04:55 +07:00
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void (*enable)(struct exynos_drm_crtc *crtc);
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void (*disable)(struct exynos_drm_crtc *crtc);
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2015-01-18 16:16:23 +07:00
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int (*enable_vblank)(struct exynos_drm_crtc *crtc);
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void (*disable_vblank)(struct exynos_drm_crtc *crtc);
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2017-03-15 21:41:02 +07:00
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u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc);
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2017-08-24 20:33:56 +07:00
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enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
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const struct drm_display_mode *mode);
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2015-10-26 19:03:39 +07:00
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int (*atomic_check)(struct exynos_drm_crtc *crtc,
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struct drm_crtc_state *state);
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2016-01-05 19:52:51 +07:00
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void (*atomic_begin)(struct exynos_drm_crtc *crtc);
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2015-08-03 12:39:36 +07:00
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void (*update_plane)(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane);
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void (*disable_plane)(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane);
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2016-01-05 19:52:51 +07:00
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void (*atomic_flush)(struct exynos_drm_crtc *crtc);
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2015-01-18 16:16:23 +07:00
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void (*te_handler)(struct exynos_drm_crtc *crtc);
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2011-10-04 17:19:01 +07:00
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};
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2016-03-23 20:25:58 +07:00
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struct exynos_drm_clk {
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void (*enable)(struct exynos_drm_clk *clk, bool enable);
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};
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2014-11-01 00:33:30 +07:00
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/*
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* Exynos specific crtc structure.
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*
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2014-11-04 03:20:29 +07:00
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* @base: crtc object.
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2014-11-06 04:51:35 +07:00
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* @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI.
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2015-01-18 16:16:23 +07:00
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* @ops: pointer to callbacks for exynos drm specific functionality
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* @ctx: A pointer to the crtc's implementation specific context
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2017-05-29 07:59:05 +07:00
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* @pipe_clk: A pointer to the crtc's pipeline clock.
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2014-11-01 00:33:30 +07:00
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*/
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struct exynos_drm_crtc {
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2014-11-04 03:20:29 +07:00
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struct drm_crtc base;
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2014-11-06 04:51:35 +07:00
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enum exynos_drm_output_type type;
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2015-05-07 07:04:45 +07:00
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const struct exynos_drm_crtc_ops *ops;
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2015-01-18 16:16:23 +07:00
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void *ctx;
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2016-03-23 20:25:58 +07:00
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struct exynos_drm_clk *pipe_clk;
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2017-08-24 20:33:53 +07:00
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bool i80_mode : 1;
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2014-11-01 00:33:30 +07:00
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};
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2016-03-23 20:25:58 +07:00
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static inline void exynos_drm_pipe_clk_enable(struct exynos_drm_crtc *crtc,
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bool enable)
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{
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if (crtc->pipe_clk)
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crtc->pipe_clk->enable(crtc->pipe_clk, enable);
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}
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2012-05-17 18:06:32 +07:00
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struct exynos_drm_g2d_private {
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struct device *dev;
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struct list_head inuse_cmdlist;
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struct list_head event_list;
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drm/exynos: add userptr feature for g2d module
This patch adds userptr feautre for G2D module.
The userptr means user space address allocated by malloc().
And the purpose of this feature is to make G2D's dma able
to access the user space region.
To user this feature, user should flag G2D_BUF_USRPTR to
offset variable of struct drm_exynos_g2d_cmd and fill
struct drm_exynos_g2d_userptr with user space address
and size for it and then should set a pointer to
drm_exynos_g2d_userptr object to data variable of struct
drm_exynos_g2d_cmd. The last bit of offset variable is used
to check if the cmdlist's buffer type is userptr or not.
If userptr, the g2d driver gets user space address and size
and then gets pages through get_user_pages().
(another case is counted as gem handle)
Below is sample codes:
static void set_cmd(struct drm_exynos_g2d_cmd *cmd,
unsigned long offset, unsigned long data)
{
cmd->offset = offset;
cmd->data = data;
}
static int solid_fill_test(int x, int y, unsigned long userptr)
{
struct drm_exynos_g2d_cmd cmd_gem[5];
struct drm_exynos_g2d_userptr g2d_userptr;
unsigned int gem_nr = 0;
...
g2d_userptr.userptr = userptr;
g2d_userptr.size = x * y * 4;
set_cmd(&cmd_gem[gem_nr++], DST_BASE_ADDR_REG |
G2D_BUF_USERPTR,
(unsigned long)&g2d_userptr);
...
}
int main(int argc, char **argv)
{
unsigned long addr;
...
addr = malloc(x * y * 4);
...
solid_fill_test(x, y, addr);
...
}
And next, the pages are mapped with iommu table and the device
address is set to cmdlist so that G2D's dma can access it.
As you may know, the pages from get_user_pages() are pinned.
In other words, they CAN NOT be migrated and also swapped out.
So the dma access would be safe.
But the use of userptr feature has performance overhead so
this patch also has memory pool to the userptr feature.
Please, assume that user sends cmdlist filled with userptr
and size every time to g2d driver, and the get_user_pages
funcion will be called every time.
The memory pool has maximum 64MB size and the userptr that
user had ever sent, is holded in the memory pool.
This meaning is that if the userptr from user is same as one
in the memory pool, device address to the userptr in the memory
pool is set to cmdlist.
And last, the pages from get_user_pages() will be freed once
user calls free() and the dma access is completed. Actually,
get_user_pages() takes 2 reference counts if the user process
has never accessed user region allocated by malloc(). Then, if
the user calls free(), the page reference count becomes 1 and
becomes 0 with put_page() call. And the reverse holds as well.
This means how the pages backed are used by dma and freed.
This patch is based on "drm/exynos: add iommu support for g2d",
https://patchwork.kernel.org/patch/1629481/
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-11-04 20:48:52 +07:00
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struct list_head userptr_list;
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2012-05-17 18:06:32 +07:00
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};
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struct drm_exynos_file_private {
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struct exynos_drm_g2d_private *g2d_priv;
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2014-07-03 20:10:28 +07:00
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struct device *ipp_dev;
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2012-05-17 18:06:32 +07:00
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};
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2011-10-04 17:19:01 +07:00
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/*
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* Exynos drm private structure.
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2012-10-20 21:53:42 +07:00
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*
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* @da_start: start address to device address space.
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* with iommu, device address space starts from this address
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* otherwise default one.
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* @da_space_size: size of device address space.
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* if 0 then default value is used for it.
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2015-08-15 23:26:17 +07:00
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* @pending: the crtcs that have pending updates to finish
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* @lock: protect access to @pending
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* @wait: wait an atomic commit to finish
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2011-10-04 17:19:01 +07:00
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*/
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struct exynos_drm_private {
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struct drm_fb_helper *fb_helper;
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2016-02-29 15:50:53 +07:00
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struct device *dma_dev;
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void *mapping;
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2014-05-09 12:25:20 +07:00
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2015-08-15 23:26:17 +07:00
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/* for atomic commit */
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u32 pending;
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spinlock_t lock;
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wait_queue_head_t wait;
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2011-10-04 17:19:01 +07:00
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};
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2016-02-29 15:50:53 +07:00
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static inline struct device *to_dma_dev(struct drm_device *dev)
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{
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struct exynos_drm_private *priv = dev->dev_private;
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return priv->dma_dev;
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}
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2011-10-04 17:19:01 +07:00
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/*
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* Exynos drm sub driver structure.
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*
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* @list: sub driver has its own list object to register to exynos drm driver.
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2012-04-05 18:49:27 +07:00
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* @dev: pointer to device object for subdrv device driver.
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2011-10-04 17:19:01 +07:00
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* @drm_dev: pointer to drm_device and this pointer would be set
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* when sub driver calls exynos_drm_subdrv_register().
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* @probe: this callback would be called by exynos drm driver after
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2014-05-09 12:25:20 +07:00
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* subdrv is registered to it.
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2011-10-04 17:19:01 +07:00
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* @remove: this callback is used to release resources created
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2014-05-09 12:25:20 +07:00
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* by probe callback.
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2012-03-16 16:47:09 +07:00
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* @open: this would be called with drm device file open.
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* @close: this would be called with drm device file close.
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2011-10-04 17:19:01 +07:00
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*/
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struct exynos_drm_subdrv {
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struct list_head list;
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2012-04-05 18:49:27 +07:00
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struct device *dev;
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2011-10-04 17:19:01 +07:00
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struct drm_device *drm_dev;
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2011-10-14 11:29:48 +07:00
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int (*probe)(struct drm_device *drm_dev, struct device *dev);
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2012-09-05 12:12:06 +07:00
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void (*remove)(struct drm_device *drm_dev, struct device *dev);
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2012-03-16 16:47:09 +07:00
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int (*open)(struct drm_device *drm_dev, struct device *dev,
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struct drm_file *file);
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void (*close)(struct drm_device *drm_dev, struct device *dev,
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struct drm_file *file);
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2011-10-04 17:19:01 +07:00
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};
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2014-05-09 12:25:20 +07:00
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/* This function would be called by non kms drivers such as g2d and ipp. */
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2011-10-04 17:19:01 +07:00
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int exynos_drm_subdrv_register(struct exynos_drm_subdrv *drm_subdrv);
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2012-03-16 16:47:08 +07:00
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/* this function removes subdrv list from exynos drm driver */
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2011-10-04 17:19:01 +07:00
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int exynos_drm_subdrv_unregister(struct exynos_drm_subdrv *drm_subdrv);
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2014-05-09 12:25:20 +07:00
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int exynos_drm_device_subdrv_probe(struct drm_device *dev);
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int exynos_drm_device_subdrv_remove(struct drm_device *dev);
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2012-03-16 16:47:09 +07:00
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int exynos_drm_subdrv_open(struct drm_device *dev, struct drm_file *file);
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void exynos_drm_subdrv_close(struct drm_device *dev, struct drm_file *file);
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2014-03-17 19:03:56 +07:00
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#ifdef CONFIG_DRM_EXYNOS_DPI
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2015-08-15 22:14:08 +07:00
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struct drm_encoder *exynos_dpi_probe(struct device *dev);
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int exynos_dpi_remove(struct drm_encoder *encoder);
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int exynos_dpi_bind(struct drm_device *dev, struct drm_encoder *encoder);
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2014-03-17 19:03:56 +07:00
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#else
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2015-08-15 22:14:08 +07:00
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static inline struct drm_encoder *
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2014-06-11 13:36:23 +07:00
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exynos_dpi_probe(struct device *dev) { return NULL; }
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2015-08-15 22:14:08 +07:00
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static inline int exynos_dpi_remove(struct drm_encoder *encoder)
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2014-11-25 00:19:49 +07:00
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{
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return 0;
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}
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2015-08-06 06:24:20 +07:00
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static inline int exynos_dpi_bind(struct drm_device *dev,
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2015-08-15 22:14:08 +07:00
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struct drm_encoder *encoder)
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2015-08-06 06:24:20 +07:00
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{
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return 0;
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}
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2014-03-17 19:03:56 +07:00
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#endif
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2015-08-15 23:26:17 +07:00
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int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state,
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2016-04-26 21:11:37 +07:00
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bool nonblock);
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2016-10-10 21:50:56 +07:00
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int exynos_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
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2015-08-15 23:26:17 +07:00
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2014-05-09 12:25:20 +07:00
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extern struct platform_driver fimd_driver;
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2015-06-12 19:59:00 +07:00
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extern struct platform_driver exynos5433_decon_driver;
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2015-02-05 22:54:04 +07:00
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extern struct platform_driver decon_driver;
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2014-01-31 04:19:23 +07:00
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extern struct platform_driver dp_driver;
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2014-04-03 23:19:56 +07:00
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extern struct platform_driver dsi_driver;
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2012-03-16 16:47:08 +07:00
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extern struct platform_driver mixer_driver;
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2014-05-09 12:25:20 +07:00
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extern struct platform_driver hdmi_driver;
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2012-03-21 08:55:26 +07:00
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extern struct platform_driver vidi_driver;
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2012-05-17 18:06:32 +07:00
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extern struct platform_driver g2d_driver;
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2012-12-14 15:58:55 +07:00
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extern struct platform_driver fimc_driver;
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2012-12-14 15:58:56 +07:00
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extern struct platform_driver rotator_driver;
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2012-12-14 15:58:57 +07:00
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extern struct platform_driver gsc_driver;
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drm/exynos: add ipp subsystem
This patch adds Image Post Processing(IPP) support for exynos drm driver.
IPP supports image scaler/rotator and input/output DMA operations
using IPP subsystem framework to control FIMC, Rotator and GSC hardware
and supports some user interfaces for user side.
And each IPP-based drivers support Memory to Memory operations
with various converting. And in case of FIMC hardware, it also supports
Writeback and Display output operations through local path.
Features:
- Memory to Memory operation support.
- Various pixel formats support.
- Image scaling support.
- Color Space Conversion support.
- Image crop operation support.
- Rotate operation support to 90, 180 or 270 degree.
- Flip operation support to vertical, horizontal or both.
- Writeback operation support to display blended image of FIMD fifo on screen
A summary to IPP Subsystem operations:
First of all, user should get property capabilities from IPP subsystem
and set these properties to hardware registers for desired operations.
The properties could be pixel format, position, rotation degree and
flip operation.
And next, user should set source and destination buffer data using
DRM_EXYNOS_IPP_QUEUE_BUF ioctl command with gem handles to source and
destinition buffers.
And next, user can control user-desired hardware with desired operations
such as play, stop, pause and resume controls.
And finally, user can aware of dma operation completion and also get
destination buffer that it contains user-desried result through dequeue
command.
IOCTL commands:
- DRM_EXYNOS_IPP_GET_PROPERTY
. get ipp driver capabilitis and id.
- DRM_EXYNOS_IPP_SET_PROPERTY
. set format, position, rotation, flip to source and destination buffers
- DRM_EXYNOS_IPP_QUEUE_BUF
. enqueue/dequeue buffer and make event list.
- DRM_EXYNOS_IPP_CMD_CTRL
. play/stop/pause/resume control.
Event:
- DRM_EXYNOS_IPP_EVENT
. a event to notify dma operation completion to user side.
Basic control flow:
Open -> Get properties -> User choose desired IPP sub driver(FIMC, Rotator
or GSCALER) -> Set Property -> Create gem handle -> Enqueue to source and
destination buffers -> Command control(Play) -> Event is notified to User
-> User gets destinition buffer complated -> (Enqueue to source and
destination buffers -> Event is notified to User) * N -> Queue/Dequeue to
source and destination buffers -> Command control(Stop) -> Free gem handle
-> Close
Changelog v1 ~ v5:
- added comments, code fixups and cleanups.
Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com>
Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-12-14 16:10:31 +07:00
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extern struct platform_driver ipp_driver;
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2015-06-12 19:59:02 +07:00
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extern struct platform_driver mic_driver;
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2011-10-04 17:19:01 +07:00
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#endif
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