linux_dsm_epyc7002/drivers/clk/imx/clk-fixup-mux.c

107 lines
2.6 KiB
C
Raw Normal View History

/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include "clk.h"
/**
* struct clk_fixup_mux - imx integer fixup multiplexer clock
* @mux: the parent class
* @ops: pointer to clk_ops of parent class
* @fixup: a hook to fixup the write value
*
* The imx fixup multiplexer clock is a subclass of basic clk_mux
* with an addtional fixup hook.
*/
struct clk_fixup_mux {
struct clk_mux mux;
const struct clk_ops *ops;
void (*fixup)(u32 *val);
};
static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
return container_of(mux, struct clk_fixup_mux, mux);
}
static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
{
struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
}
static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
struct clk_mux *mux = to_clk_mux(hw);
unsigned long flags = 0;
u32 val;
spin_lock_irqsave(mux->lock, flags);
val = readl(mux->reg);
val &= ~(mux->mask << mux->shift);
val |= index << mux->shift;
fixup_mux->fixup(&val);
writel(val, mux->reg);
spin_unlock_irqrestore(mux->lock, flags);
return 0;
}
static const struct clk_ops clk_fixup_mux_ops = {
.get_parent = clk_fixup_mux_get_parent,
.set_parent = clk_fixup_mux_set_parent,
};
struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char **parents,
int num_parents, void (*fixup)(u32 *val))
{
struct clk_fixup_mux *fixup_mux;
struct clk *clk;
struct clk_init_data init;
if (!fixup)
return ERR_PTR(-EINVAL);
fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL);
if (!fixup_mux)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &clk_fixup_mux_ops;
init.parent_names = parents;
init.num_parents = num_parents;
ARM: imx: initialize clk_init_data.flags for clk-fixup-mux The clk_init_data.flags of clk-fixup-mux is left there without initialization. It may hold some random data and cause clock framework interpret the clock in an unexpected way. At least on imx6sl, the following division by zero error with sched_clock is seen because of it. Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.11.0-rc3+ #19 Backtrace: [<80011af0>] (dump_backtrace+0x0/0x10c) from [<80011c90>] (show_stack+0x18/0x1c) r6:3b9aca00 r5:00000020 r4:00000000 r3:00000000 [<80011c78>] (show_stack+0x0/0x1c) from [<8055e02c>] (dump_stack+0x78/0x94) [<8055dfb4>] (dump_stack+0x0/0x94) from [<80011924>] (__div0+0x18/0x20) r4:00000000 r3:00000000 [<8001190c>] (__div0+0x0/0x20) from [<8026c408>] (Ldiv0_64+0x8/0x18) [<8006330c>] (clocks_calc_mult_shift+0x0/0xf8) from [<8072f604>] (setup_sched_clock+0x88/0x1f0) [<8072f57c>] (setup_sched_clock+0x0/0x1f0) from [<8071ad48>] (mxc_timer_init+0xe8/0x17c) [<8071ac60>] (mxc_timer_init+0x0/0x17c) from [<807290b0>] (imx6sl_clocks_init+0x1db8/0x1dc0) r8:807a9ca4 r7:00000000 r6:80777564 r5:8100c1f4 r4:c0820000 [<807272f8>] (imx6sl_clocks_init+0x0/0x1dc0) from [<807420ac>] (of_clk_init+0x40/0x6c) [<8074206c>] (of_clk_init+0x0/0x6c) from [<807290cc>] (imx6sl_timer_init+0x14/0x18) r5:807a8e80 r4:ffffffff [<807290b8>] (imx6sl_timer_init+0x0/0x18) from [<80716e1c>] (time_init+0x24/0x34) [<80716df8>] (time_init+0x0/0x34) from [<80713738>] (start_kernel+0x1b0/0x310) [<80713588>] (start_kernel+0x0/0x310) from [<80008074>] (0x80008074) r7:80770b08 r6:80754cd4 r5:8076c8c4 r4:10c53c7d sched_clock: 32 bits at 0 Hz, resolution 0ns, wraps every 0ms Fix the bug by initializing init.flags as zero. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-09-04 19:49:04 +07:00
init.flags = 0;
fixup_mux->mux.reg = reg;
fixup_mux->mux.shift = shift;
fixup_mux->mux.mask = BIT(width) - 1;
fixup_mux->mux.lock = &imx_ccm_lock;
fixup_mux->mux.hw.init = &init;
fixup_mux->ops = &clk_mux_ops;
fixup_mux->fixup = fixup;
clk = clk_register(NULL, &fixup_mux->mux.hw);
if (IS_ERR(clk))
kfree(fixup_mux);
return clk;
}