2016-03-07 17:00:53 +07:00
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/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* ARM Mali DP plane manipulation routines.
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*/
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#include <drm/drmP.h>
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2016-11-25 21:28:54 +07:00
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#include <drm/drm_atomic.h>
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2016-03-07 17:00:53 +07:00
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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2017-01-23 22:12:02 +07:00
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#include <drm/drm_print.h>
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2016-03-07 17:00:53 +07:00
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#include "malidp_hw.h"
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#include "malidp_drv.h"
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/* Layer specific register offsets */
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#define MALIDP_LAYER_FORMAT 0x000
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#define MALIDP_LAYER_CONTROL 0x004
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#define LAYER_ENABLE (1 << 0)
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2017-02-13 22:14:05 +07:00
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#define LAYER_FLOWCFG_MASK 7
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#define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1)
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#define LAYER_FLOWCFG_SCALE_SE 3
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2016-03-07 17:00:53 +07:00
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#define LAYER_ROT_OFFSET 8
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#define LAYER_H_FLIP (1 << 10)
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#define LAYER_V_FLIP (1 << 11)
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#define LAYER_ROT_MASK (0xf << 8)
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2016-10-11 21:26:08 +07:00
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#define LAYER_COMP_MASK (0x3 << 12)
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#define LAYER_COMP_PIXEL (0x3 << 12)
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#define LAYER_COMP_PLANE (0x2 << 12)
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#define MALIDP_LAYER_COMPOSE 0x008
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2016-03-07 17:00:53 +07:00
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#define MALIDP_LAYER_SIZE 0x00c
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#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
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#define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
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#define MALIDP_LAYER_COMP_SIZE 0x010
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#define MALIDP_LAYER_OFFSET 0x014
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2017-02-09 18:32:00 +07:00
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#define MALIDP550_LS_ENABLE 0x01c
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#define MALIDP550_LS_R1_IN_SIZE 0x020
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2016-03-07 17:00:53 +07:00
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2016-10-11 21:26:08 +07:00
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/*
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* This 4-entry look-up-table is used to determine the full 8-bit alpha value
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* for formats with 1- or 2-bit alpha channels.
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* We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
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* opacity for 2-bit formats.
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*/
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#define MALIDP_ALPHA_LUT 0xffaa5500
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2016-03-07 17:00:53 +07:00
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static void malidp_de_plane_destroy(struct drm_plane *plane)
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{
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struct malidp_plane *mp = to_malidp_plane(plane);
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if (mp->base.fb)
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2017-08-11 19:32:48 +07:00
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drm_framebuffer_put(mp->base.fb);
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2016-03-07 17:00:53 +07:00
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drm_plane_helper_disable(plane);
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drm_plane_cleanup(plane);
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devm_kfree(plane->dev->dev, mp);
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}
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2016-12-01 19:19:58 +07:00
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/*
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* Replicate what the default ->reset hook does: free the state pointer and
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* allocate a new empty object. We just need enough space to store
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* a malidp_plane_state instead of a drm_plane_state.
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*/
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static void malidp_plane_reset(struct drm_plane *plane)
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{
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struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
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if (state)
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__drm_atomic_helper_plane_destroy_state(&state->base);
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kfree(state);
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plane->state = NULL;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state) {
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state->base.plane = plane;
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2017-05-20 03:50:17 +07:00
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state->base.rotation = DRM_MODE_ROTATE_0;
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2016-12-01 19:19:58 +07:00
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plane->state = &state->base;
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}
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}
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2016-10-22 16:13:01 +07:00
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static struct
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drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
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2016-03-07 17:00:53 +07:00
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{
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struct malidp_plane_state *state, *m_state;
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if (!plane->state)
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return NULL;
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state = kmalloc(sizeof(*state), GFP_KERNEL);
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2016-11-11 20:35:00 +07:00
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if (!state)
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return NULL;
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m_state = to_malidp_plane_state(plane->state);
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__drm_atomic_helper_plane_duplicate_state(plane, &state->base);
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state->rotmem_size = m_state->rotmem_size;
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state->format = m_state->format;
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state->n_planes = m_state->n_planes;
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2016-03-07 17:00:53 +07:00
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return &state->base;
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}
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2016-10-22 16:13:01 +07:00
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static void malidp_destroy_plane_state(struct drm_plane *plane,
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struct drm_plane_state *state)
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2016-03-07 17:00:53 +07:00
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{
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struct malidp_plane_state *m_state = to_malidp_plane_state(state);
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__drm_atomic_helper_plane_destroy_state(state);
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kfree(m_state);
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}
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2017-01-23 22:12:02 +07:00
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static void malidp_plane_atomic_print_state(struct drm_printer *p,
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const struct drm_plane_state *state)
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{
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struct malidp_plane_state *ms = to_malidp_plane_state(state);
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drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
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drm_printf(p, "\tformat_id=%u\n", ms->format);
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drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
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}
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2016-03-07 17:00:53 +07:00
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static const struct drm_plane_funcs malidp_de_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = malidp_de_plane_destroy,
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2016-12-01 19:19:58 +07:00
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.reset = malidp_plane_reset,
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2016-03-07 17:00:53 +07:00
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.atomic_duplicate_state = malidp_duplicate_plane_state,
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.atomic_destroy_state = malidp_destroy_plane_state,
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2017-01-23 22:12:02 +07:00
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.atomic_print_state = malidp_plane_atomic_print_state,
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2016-03-07 17:00:53 +07:00
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};
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2017-02-13 22:14:05 +07:00
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static int malidp_se_check_scaling(struct malidp_plane *mp,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state =
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drm_atomic_get_existing_crtc_state(state->state, state->crtc);
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struct malidp_crtc_state *mc;
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struct drm_rect clip = { 0 };
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u32 src_w, src_h;
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int ret;
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if (!crtc_state)
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return -EINVAL;
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2017-11-24 02:04:51 +07:00
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if (crtc_state->enable)
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drm_mode_get_hv_timing(&crtc_state->mode,
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&clip.x2, &clip.y2);
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2017-11-02 03:16:19 +07:00
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ret = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
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0, INT_MAX, true, true);
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2017-02-13 22:14:05 +07:00
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if (ret)
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return ret;
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src_w = state->src_w >> 16;
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src_h = state->src_h >> 16;
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if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
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/* Scaling not necessary for this plane. */
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mc->scaled_planes_mask &= ~(mp->layer->id);
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return 0;
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}
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if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
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return -EINVAL;
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mc = to_malidp_crtc_state(crtc_state);
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mc->scaled_planes_mask |= mp->layer->id;
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/* Defer scaling requirements calculation to the crtc check. */
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return 0;
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}
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2016-03-07 17:00:53 +07:00
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static int malidp_de_plane_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct malidp_plane *mp = to_malidp_plane(plane);
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struct malidp_plane_state *ms = to_malidp_plane_state(state);
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2016-10-11 21:26:05 +07:00
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struct drm_framebuffer *fb;
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2016-11-25 21:28:54 +07:00
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int i, ret;
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2016-03-07 17:00:53 +07:00
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if (!state->crtc || !state->fb)
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return 0;
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2016-10-11 21:26:05 +07:00
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fb = state->fb;
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2017-08-31 21:48:43 +07:00
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ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
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mp->layer->id,
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fb->format->format);
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2016-10-11 21:26:09 +07:00
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if (ms->format == MALIDP_INVALID_FORMAT_ID)
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2016-03-07 17:00:53 +07:00
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return -EINVAL;
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2016-12-15 04:30:22 +07:00
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ms->n_planes = fb->format->num_planes;
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2016-10-11 21:26:09 +07:00
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for (i = 0; i < ms->n_planes; i++) {
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2016-10-11 21:26:05 +07:00
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if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
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DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
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fb->pitches[i], i);
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return -EINVAL;
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}
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}
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2016-03-07 17:00:53 +07:00
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if ((state->crtc_w > mp->hwdev->max_line_size) ||
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(state->crtc_h > mp->hwdev->max_line_size) ||
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(state->crtc_w < mp->hwdev->min_line_size) ||
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2016-12-07 20:14:51 +07:00
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(state->crtc_h < mp->hwdev->min_line_size))
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2016-03-07 17:00:53 +07:00
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return -EINVAL;
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2017-01-23 22:24:35 +07:00
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/*
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* DP550/650 video layers can accept 3 plane formats only if
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* fb->pitches[1] == fb->pitches[2] since they don't have a
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* third plane stride register.
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*/
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if (ms->n_planes == 3 &&
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2017-08-31 21:48:43 +07:00
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!(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
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2017-01-23 22:24:35 +07:00
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(state->fb->pitches[1] != state->fb->pitches[2]))
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return -EINVAL;
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2017-02-13 22:14:05 +07:00
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ret = malidp_se_check_scaling(mp, state);
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if (ret)
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return ret;
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2016-03-07 17:00:53 +07:00
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/* packed RGB888 / BGR888 can't be rotated or flipped */
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2017-05-20 03:50:17 +07:00
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if (state->rotation != DRM_MODE_ROTATE_0 &&
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2016-12-15 04:32:55 +07:00
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(fb->format->format == DRM_FORMAT_RGB888 ||
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fb->format->format == DRM_FORMAT_BGR888))
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2016-03-07 17:00:53 +07:00
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return -EINVAL;
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ms->rotmem_size = 0;
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if (state->rotation & MALIDP_ROTATED_MASK) {
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int val;
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2017-08-31 21:48:43 +07:00
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val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
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state->crtc_w,
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fb->format->format);
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2016-03-07 17:00:53 +07:00
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if (val < 0)
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return val;
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ms->rotmem_size = val;
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}
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return 0;
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}
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2017-01-23 22:24:35 +07:00
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static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
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int num_planes, unsigned int pitches[3])
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{
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int i;
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int num_strides = num_planes;
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if (!mp->layer->stride_offset)
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return;
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if (num_planes == 3)
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2017-08-31 21:48:43 +07:00
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num_strides = (mp->hwdev->hw->features &
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2017-01-23 22:24:35 +07:00
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MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
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for (i = 0; i < num_strides; ++i)
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malidp_hw_write(mp->hwdev, pitches[i],
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mp->layer->base +
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mp->layer->stride_offset + i * 4);
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}
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2016-03-07 17:00:53 +07:00
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static void malidp_de_plane_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct malidp_plane *mp;
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2016-10-11 21:26:09 +07:00
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struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
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u32 src_w, src_h, dest_w, dest_h, val;
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int i;
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2016-03-07 17:00:53 +07:00
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mp = to_malidp_plane(plane);
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/* convert src values from Q16 fixed point to integer */
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src_w = plane->state->src_w >> 16;
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src_h = plane->state->src_h >> 16;
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2016-12-07 20:17:21 +07:00
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dest_w = plane->state->crtc_w;
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dest_h = plane->state->crtc_h;
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2016-03-07 17:00:53 +07:00
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2016-10-11 21:26:09 +07:00
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malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
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2016-03-07 17:00:53 +07:00
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2016-10-11 21:26:09 +07:00
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for (i = 0; i < ms->n_planes; i++) {
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2016-03-07 17:00:53 +07:00
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/* calculate the offset for the layer's plane registers */
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2017-06-13 18:20:39 +07:00
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u16 ptr = mp->layer->ptr + (i << 4);
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dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
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plane->state, i);
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2016-03-07 17:00:53 +07:00
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2017-06-13 18:20:39 +07:00
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malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
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malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
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2016-03-07 17:00:53 +07:00
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}
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2017-01-23 22:24:35 +07:00
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malidp_de_set_plane_pitches(mp, ms->n_planes,
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plane->state->fb->pitches);
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2016-03-07 17:00:53 +07:00
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malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
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|
|
mp->layer->base + MALIDP_LAYER_SIZE);
|
|
|
|
|
|
|
|
malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
|
|
|
|
mp->layer->base + MALIDP_LAYER_COMP_SIZE);
|
|
|
|
|
|
|
|
malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
|
|
|
|
LAYER_V_VAL(plane->state->crtc_y),
|
|
|
|
mp->layer->base + MALIDP_LAYER_OFFSET);
|
|
|
|
|
2017-02-09 18:32:00 +07:00
|
|
|
if (mp->layer->id == DE_SMART)
|
|
|
|
malidp_hw_write(mp->hwdev,
|
|
|
|
LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
|
|
|
|
mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
|
|
|
|
|
2016-10-11 21:26:08 +07:00
|
|
|
/* first clear the rotation bits */
|
|
|
|
val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
|
|
|
|
val &= ~LAYER_ROT_MASK;
|
2016-03-07 17:00:53 +07:00
|
|
|
|
|
|
|
/* setup the rotation and axis flip bits */
|
2017-05-20 03:50:17 +07:00
|
|
|
if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
|
|
|
|
val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
|
2016-12-23 16:57:20 +07:00
|
|
|
LAYER_ROT_OFFSET;
|
2017-05-20 03:50:17 +07:00
|
|
|
if (plane->state->rotation & DRM_MODE_REFLECT_X)
|
2016-03-07 17:00:53 +07:00
|
|
|
val |= LAYER_H_FLIP;
|
2017-05-20 03:50:17 +07:00
|
|
|
if (plane->state->rotation & DRM_MODE_REFLECT_Y)
|
2016-12-07 20:20:28 +07:00
|
|
|
val |= LAYER_V_FLIP;
|
2016-03-07 17:00:53 +07:00
|
|
|
|
2016-10-11 21:26:08 +07:00
|
|
|
/*
|
|
|
|
* always enable pixel alpha blending until we have a way to change
|
|
|
|
* blend modes
|
|
|
|
*/
|
|
|
|
val &= ~LAYER_COMP_MASK;
|
|
|
|
val |= LAYER_COMP_PIXEL;
|
|
|
|
|
2017-02-13 22:14:05 +07:00
|
|
|
val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
|
|
|
|
if (plane->state->crtc) {
|
|
|
|
struct malidp_crtc_state *m =
|
|
|
|
to_malidp_crtc_state(plane->state->crtc->state);
|
|
|
|
|
|
|
|
if (m->scaler_config.scale_enable &&
|
|
|
|
m->scaler_config.plane_src_id == mp->layer->id)
|
|
|
|
val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
|
|
|
|
}
|
|
|
|
|
2016-03-07 17:00:53 +07:00
|
|
|
/* set the 'enable layer' bit */
|
|
|
|
val |= LAYER_ENABLE;
|
|
|
|
|
2016-10-11 21:26:08 +07:00
|
|
|
malidp_hw_write(mp->hwdev, val,
|
|
|
|
mp->layer->base + MALIDP_LAYER_CONTROL);
|
2016-03-07 17:00:53 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void malidp_de_plane_disable(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *state)
|
|
|
|
{
|
|
|
|
struct malidp_plane *mp = to_malidp_plane(plane);
|
|
|
|
|
2017-02-13 22:14:05 +07:00
|
|
|
malidp_hw_clearbits(mp->hwdev,
|
|
|
|
LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
|
2016-03-07 17:00:53 +07:00
|
|
|
mp->layer->base + MALIDP_LAYER_CONTROL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
|
|
|
|
.atomic_check = malidp_de_plane_check,
|
|
|
|
.atomic_update = malidp_de_plane_update,
|
|
|
|
.atomic_disable = malidp_de_plane_disable,
|
|
|
|
};
|
|
|
|
|
|
|
|
int malidp_de_planes_init(struct drm_device *drm)
|
|
|
|
{
|
|
|
|
struct malidp_drm *malidp = drm->dev_private;
|
2017-08-31 21:48:43 +07:00
|
|
|
const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
|
2016-03-07 17:00:53 +07:00
|
|
|
struct malidp_plane *plane = NULL;
|
|
|
|
enum drm_plane_type plane_type;
|
|
|
|
unsigned long crtcs = 1 << drm->mode_config.num_crtc;
|
2017-05-20 03:50:17 +07:00
|
|
|
unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
|
|
|
|
DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
|
2016-03-07 17:00:53 +07:00
|
|
|
u32 *formats;
|
|
|
|
int ret, i, j, n;
|
|
|
|
|
2016-10-03 21:08:12 +07:00
|
|
|
formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
|
2016-03-07 17:00:53 +07:00
|
|
|
if (!formats) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < map->n_layers; i++) {
|
|
|
|
u8 id = map->layers[i].id;
|
|
|
|
|
|
|
|
plane = kzalloc(sizeof(*plane), GFP_KERNEL);
|
|
|
|
if (!plane) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto cleanup;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* build the list of DRM supported formats based on the map */
|
2016-10-03 21:08:12 +07:00
|
|
|
for (n = 0, j = 0; j < map->n_pixel_formats; j++) {
|
|
|
|
if ((map->pixel_formats[j].layer & id) == id)
|
|
|
|
formats[n++] = map->pixel_formats[j].format;
|
2016-03-07 17:00:53 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
|
|
|
|
DRM_PLANE_TYPE_OVERLAY;
|
|
|
|
ret = drm_universal_plane_init(drm, &plane->base, crtcs,
|
|
|
|
&malidp_de_plane_funcs, formats,
|
2017-07-24 10:46:38 +07:00
|
|
|
n, NULL, plane_type, NULL);
|
2016-03-07 17:00:53 +07:00
|
|
|
if (ret < 0)
|
|
|
|
goto cleanup;
|
|
|
|
|
|
|
|
drm_plane_helper_add(&plane->base,
|
|
|
|
&malidp_de_plane_helper_funcs);
|
|
|
|
plane->hwdev = malidp->dev;
|
|
|
|
plane->layer = &map->layers[i];
|
2016-10-11 21:26:07 +07:00
|
|
|
|
2017-02-09 18:32:00 +07:00
|
|
|
if (id == DE_SMART) {
|
|
|
|
/*
|
|
|
|
* Enable the first rectangle in the SMART layer to be
|
|
|
|
* able to use it as a drm plane.
|
|
|
|
*/
|
|
|
|
malidp_hw_write(malidp->dev, 1,
|
|
|
|
plane->layer->base + MALIDP550_LS_ENABLE);
|
|
|
|
/* Skip the features which the SMART layer doesn't have. */
|
2016-10-11 21:26:07 +07:00
|
|
|
continue;
|
2017-02-09 18:32:00 +07:00
|
|
|
}
|
2016-10-11 21:26:07 +07:00
|
|
|
|
2017-05-20 03:50:17 +07:00
|
|
|
drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
|
2016-10-11 21:26:08 +07:00
|
|
|
malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
|
|
|
|
plane->layer->base + MALIDP_LAYER_COMPOSE);
|
2016-03-07 17:00:53 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
kfree(formats);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cleanup:
|
|
|
|
malidp_de_planes_destroy(drm);
|
|
|
|
kfree(formats);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void malidp_de_planes_destroy(struct drm_device *drm)
|
|
|
|
{
|
|
|
|
struct drm_plane *p, *pt;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
|
|
|
|
drm_plane_cleanup(p);
|
|
|
|
kfree(p);
|
|
|
|
}
|
|
|
|
}
|