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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
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/*
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* GICv3 ITS emulation
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*
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* Copyright (C) 2015,2016 ARM Ltd.
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* Author: Andre Przywara <andre.przywara@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
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{ \
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.reg_offset = off, \
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.len = length, \
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.access_flags = acc, \
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.its_read = rd, \
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.its_write = wr, \
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}
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static unsigned long its_mmio_read_raz(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return 0;
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}
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static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len, unsigned long val)
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{
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/* Ignore */
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}
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static struct vgic_register_region its_registers[] = {
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REGISTER_ITS_DESC(GITS_CTLR,
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its_mmio_read_raz, its_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IIDR,
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its_mmio_read_raz, its_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_TYPER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CBASER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CWRITER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CREADR,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_BASER,
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its_mmio_read_raz, its_mmio_write_wi, 0x40,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IDREGS_BASE,
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its_mmio_read_raz, its_mmio_write_wi, 0x30,
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VGIC_ACCESS_32bit),
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};
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static int vgic_its_init_its(struct kvm *kvm, struct vgic_its *its)
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{
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struct vgic_io_device *iodev = &its->iodev;
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int ret;
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if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
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return -ENXIO;
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iodev->regions = its_registers;
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iodev->nr_regions = ARRAY_SIZE(its_registers);
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kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
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iodev->base_addr = its->vgic_its_base;
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iodev->iodev_type = IODEV_ITS;
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iodev->its = its;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
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KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
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mutex_unlock(&kvm->slots_lock);
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return ret;
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}
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