2005-04-17 05:20:36 +07:00
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/*
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* PCI Express PCI Hot Plug Driver
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*
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* Copyright (C) 1995,2001 Compaq Computer Corporation
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* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
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* Copyright (C) 2001 IBM Corp.
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* Copyright (C) 2003-2004 Intel Corporation
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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2005-08-17 05:16:10 +07:00
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* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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2005-04-17 05:20:36 +07:00
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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2006-01-08 16:02:05 +07:00
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#include <linux/signal.h>
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#include <linux/jiffies.h>
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#include <linux/timer.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/pci.h>
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2005-11-14 07:06:39 +07:00
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#include <linux/interrupt.h>
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2007-01-10 04:02:36 +07:00
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#include <linux/time.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/slab.h>
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2005-11-14 07:06:39 +07:00
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2005-04-17 05:20:36 +07:00
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#include "../pci.h"
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#include "pciehp.h"
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2013-05-10 00:26:16 +07:00
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static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
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2006-12-22 08:01:06 +07:00
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{
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2013-05-10 00:26:16 +07:00
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return ctrl->pcie->port;
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2006-12-22 08:01:06 +07:00
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}
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2005-04-17 05:20:36 +07:00
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2006-12-22 08:01:04 +07:00
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static irqreturn_t pcie_isr(int irq, void *dev_id);
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static void start_int_poll_timer(struct controller *ctrl, int sec);
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2005-04-17 05:20:36 +07:00
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/* This is the interrupt polling timeout function. */
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2006-12-22 08:01:04 +07:00
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static void int_poll_timeout(unsigned long data)
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2005-04-17 05:20:36 +07:00
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{
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2006-12-22 08:01:04 +07:00
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struct controller *ctrl = (struct controller *)data;
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2005-04-17 05:20:36 +07:00
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/* Poll for interrupt events. regs == NULL => polling */
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2006-12-22 08:01:04 +07:00
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pcie_isr(0, ctrl);
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2005-04-17 05:20:36 +07:00
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2006-12-22 08:01:04 +07:00
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init_timer(&ctrl->poll_timer);
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2005-04-17 05:20:36 +07:00
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if (!pciehp_poll_time)
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2007-08-10 06:09:38 +07:00
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pciehp_poll_time = 2; /* default polling interval is 2 sec */
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2005-04-17 05:20:36 +07:00
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2006-12-22 08:01:04 +07:00
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start_int_poll_timer(ctrl, pciehp_poll_time);
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2005-04-17 05:20:36 +07:00
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}
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/* This function starts the interrupt polling timer. */
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2006-12-22 08:01:04 +07:00
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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2005-04-17 05:20:36 +07:00
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{
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2006-12-22 08:01:04 +07:00
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/* Clamp to sane value */
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if ((sec <= 0) || (sec > 60))
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2013-11-15 01:28:18 +07:00
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sec = 2;
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2006-12-22 08:01:04 +07:00
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ctrl->poll_timer.function = &int_poll_timeout;
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ctrl->poll_timer.data = (unsigned long)ctrl;
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ctrl->poll_timer.expires = jiffies + sec * HZ;
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add_timer(&ctrl->poll_timer);
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2005-04-17 05:20:36 +07:00
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}
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2008-04-26 04:39:08 +07:00
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static inline int pciehp_request_irq(struct controller *ctrl)
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{
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2008-08-22 15:16:48 +07:00
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int retval, irq = ctrl->pcie->irq;
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2008-04-26 04:39:08 +07:00
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/* Install interrupt polling timer. Start with 10 sec delay */
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if (pciehp_poll_mode) {
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init_timer(&ctrl->poll_timer);
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start_int_poll_timer(ctrl, 10);
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return 0;
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}
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/* Installs the interrupt handler */
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retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
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if (retval)
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2008-09-05 10:11:26 +07:00
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ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
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irq);
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2008-04-26 04:39:08 +07:00
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return retval;
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}
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static inline void pciehp_free_irq(struct controller *ctrl)
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{
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if (pciehp_poll_mode)
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del_timer_sync(&ctrl->poll_timer);
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else
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2008-08-22 15:16:48 +07:00
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free_irq(ctrl->pcie->irq, ctrl);
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2008-04-26 04:39:08 +07:00
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}
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PCI: pciehp: Compute timeout from hotplug command start time
If we issue a hotplug command, go do something else, then come back and
wait for the command to complete, we don't have to wait the whole timeout
period, because some of it elapsed while we were doing something else.
Keep track of the time we issued the command, and wait only until the
timeout period from that point has elapsed.
For controllers with errata like Intel CF118, we previously timed out
before issuing the second hotplug command:
At time T1 (during boot):
- Write DLLSCE, ABPE, PDCE, etc. to Slot Control
At time T2 (hotplug event):
- Wait for command completion (CC) in Slot Status
- Timeout at T2 + 1 second because CC is never set in Slot Status
- Write PCC, PIC, etc. to Slot Control
With this change, we wait until T1 + 1 second instead of T2 + 1 second.
If the hotplug event is more than 1 second after the boot-time
initialization, we won't wait for the timeout at all.
We still emit a "Timeout on hotplug command" message if it timed out; we
should see this on the first hotplug event on every controller with this
erratum, as well as on real errors on controllers without the erratum.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 22:55:49 +07:00
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static int pcie_poll_cmd(struct controller *ctrl, int timeout)
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2008-05-27 17:05:26 +07:00
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{
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2013-05-10 00:26:16 +07:00
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struct pci_dev *pdev = ctrl_dev(ctrl);
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2008-05-27 17:05:26 +07:00
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u16 slot_status;
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2015-06-19 14:57:45 +07:00
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while (true) {
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2013-12-15 03:06:07 +07:00
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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PCI: pciehp: Handle invalid data when reading from non-existent devices
It's platform-dependent, but an MMIO read to a non-existent PCI device
generally returns data with all bits set. This happens when the host
bridge or Root Complex times out waiting for a response from the device and
fabricates return data to complete the CPU's read.
One example, reported in the bugzilla below, involved this hierarchy:
pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port
pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port
pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port
pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port
pci 0000:06:00.0: PCI bridge to [bus 07] Thunderbolt Downstream Port
pci 0000:07:00.0: BCM57762 NIC
Unplugging the Thunderbolt switch and the NIC below it resulted in this:
pciehp 0000:03:03.0: Surprise Removal
tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff
pciehp 0000:06:00.0: unloading service driver pciehp
pciehp 0000:06:00.0: pcie_isr: intr_loc 11f
pciehp 0000:06:00.0: Switch interrupt received
pciehp 0000:06:00.0: Latch open on Slot
pciehp 0000:06:00.0: Attention button interrupt received
pciehp 0000:06:00.0: Button pressed on Slot
pciehp 0000:06:00.0: Presence/Notify input change
pciehp 0000:06:00.0: Card present on Slot
pciehp 0000:06:00.0: Power fault interrupt received
pciehp 0000:06:00.0: Data Link Layer State change
pciehp 0000:06:00.0: Link Up event
The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0
and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver
remove methods.
Since the NIC was already gone, tg3 received 0xffffffff when it tried to
read from the device. The resulting timeout is a tg3 issue and not of
interest here.
Similarly, since the 06:00.0 Thunderbolt switch was already gone,
pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp
thought that was valid status showing that many events had happened: the
latch had been opened, the attention button had been pressed, a card was
now present, and the link was now up. These are all wrong, of course, but
pciehp went on to try to power up and enumerate devices below the
non-existent bridge:
pciehp 0000:06:00.0: PCI slot - powering on due to button press
pciehp 0000:06:00.0: Surprise Insertion
pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff
[bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-07-21 23:25:30 +07:00
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if (slot_status == (u16) ~0) {
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ctrl_info(ctrl, "%s: no response from device\n",
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__func__);
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return 0;
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}
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2013-12-15 03:06:07 +07:00
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if (slot_status & PCI_EXP_SLTSTA_CC) {
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2013-05-10 00:26:16 +07:00
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
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PCI_EXP_SLTSTA_CC);
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2008-12-19 13:19:02 +07:00
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return 1;
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2008-06-20 10:04:33 +07:00
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}
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2015-06-19 14:57:45 +07:00
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if (timeout < 0)
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break;
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msleep(10);
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timeout -= 10;
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2008-05-27 17:05:26 +07:00
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}
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return 0; /* timeout */
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}
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2014-06-14 02:58:35 +07:00
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static void pcie_wait_cmd(struct controller *ctrl)
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2006-12-22 08:01:09 +07:00
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{
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2006-12-22 08:01:10 +07:00
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unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
|
PCI: pciehp: Compute timeout from hotplug command start time
If we issue a hotplug command, go do something else, then come back and
wait for the command to complete, we don't have to wait the whole timeout
period, because some of it elapsed while we were doing something else.
Keep track of the time we issued the command, and wait only until the
timeout period from that point has elapsed.
For controllers with errata like Intel CF118, we previously timed out
before issuing the second hotplug command:
At time T1 (during boot):
- Write DLLSCE, ABPE, PDCE, etc. to Slot Control
At time T2 (hotplug event):
- Wait for command completion (CC) in Slot Status
- Timeout at T2 + 1 second because CC is never set in Slot Status
- Write PCC, PIC, etc. to Slot Control
With this change, we wait until T1 + 1 second instead of T2 + 1 second.
If the hotplug event is more than 1 second after the boot-time
initialization, we won't wait for the timeout at all.
We still emit a "Timeout on hotplug command" message if it timed out; we
should see this on the first hotplug event on every controller with this
erratum, as well as on real errors on controllers without the erratum.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 22:55:49 +07:00
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unsigned long duration = msecs_to_jiffies(msecs);
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unsigned long cmd_timeout = ctrl->cmd_started + duration;
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unsigned long now, timeout;
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2006-12-22 08:01:10 +07:00
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int rc;
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2014-06-14 02:58:35 +07:00
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/*
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* If the controller does not generate notifications for command
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* completions, we never need to wait between writes.
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*/
|
2014-06-27 01:58:55 +07:00
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if (NO_CMD_CMPL(ctrl))
|
2014-06-14 02:58:35 +07:00
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return;
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if (!ctrl->cmd_busy)
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return;
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|
|
|
|
PCI: pciehp: Compute timeout from hotplug command start time
If we issue a hotplug command, go do something else, then come back and
wait for the command to complete, we don't have to wait the whole timeout
period, because some of it elapsed while we were doing something else.
Keep track of the time we issued the command, and wait only until the
timeout period from that point has elapsed.
For controllers with errata like Intel CF118, we previously timed out
before issuing the second hotplug command:
At time T1 (during boot):
- Write DLLSCE, ABPE, PDCE, etc. to Slot Control
At time T2 (hotplug event):
- Wait for command completion (CC) in Slot Status
- Timeout at T2 + 1 second because CC is never set in Slot Status
- Write PCC, PIC, etc. to Slot Control
With this change, we wait until T1 + 1 second instead of T2 + 1 second.
If the hotplug event is more than 1 second after the boot-time
initialization, we won't wait for the timeout at all.
We still emit a "Timeout on hotplug command" message if it timed out; we
should see this on the first hotplug event on every controller with this
erratum, as well as on real errors on controllers without the erratum.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 22:55:49 +07:00
|
|
|
/*
|
|
|
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* Even if the command has already timed out, we want to call
|
|
|
|
* pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
|
|
|
|
*/
|
|
|
|
now = jiffies;
|
|
|
|
if (time_before_eq(cmd_timeout, now))
|
|
|
|
timeout = 1;
|
|
|
|
else
|
|
|
|
timeout = cmd_timeout - now;
|
|
|
|
|
2014-06-14 02:58:35 +07:00
|
|
|
if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
|
|
|
|
ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
|
2008-05-28 12:59:44 +07:00
|
|
|
rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
|
2014-06-14 02:58:35 +07:00
|
|
|
else
|
2014-09-23 09:05:45 +07:00
|
|
|
rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
|
PCI: pciehp: Compute timeout from hotplug command start time
If we issue a hotplug command, go do something else, then come back and
wait for the command to complete, we don't have to wait the whole timeout
period, because some of it elapsed while we were doing something else.
Keep track of the time we issued the command, and wait only until the
timeout period from that point has elapsed.
For controllers with errata like Intel CF118, we previously timed out
before issuing the second hotplug command:
At time T1 (during boot):
- Write DLLSCE, ABPE, PDCE, etc. to Slot Control
At time T2 (hotplug event):
- Wait for command completion (CC) in Slot Status
- Timeout at T2 + 1 second because CC is never set in Slot Status
- Write PCC, PIC, etc. to Slot Control
With this change, we wait until T1 + 1 second instead of T2 + 1 second.
If the hotplug event is more than 1 second after the boot-time
initialization, we won't wait for the timeout at all.
We still emit a "Timeout on hotplug command" message if it timed out; we
should see this on the first hotplug event on every controller with this
erratum, as well as on real errors on controllers without the erratum.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 22:55:49 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Controllers with errata like Intel CF118 don't generate
|
|
|
|
* completion notifications unless the power/indicator/interlock
|
|
|
|
* control bits are changed. On such controllers, we'll emit this
|
|
|
|
* timeout message when we wait for completion of commands that
|
|
|
|
* don't change those bits, e.g., commands that merely enable
|
|
|
|
* interrupts.
|
|
|
|
*/
|
2006-12-22 08:01:10 +07:00
|
|
|
if (!rc)
|
2014-08-16 06:18:44 +07:00
|
|
|
ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
|
PCI: pciehp: Compute timeout from hotplug command start time
If we issue a hotplug command, go do something else, then come back and
wait for the command to complete, we don't have to wait the whole timeout
period, because some of it elapsed while we were doing something else.
Keep track of the time we issued the command, and wait only until the
timeout period from that point has elapsed.
For controllers with errata like Intel CF118, we previously timed out
before issuing the second hotplug command:
At time T1 (during boot):
- Write DLLSCE, ABPE, PDCE, etc. to Slot Control
At time T2 (hotplug event):
- Wait for command completion (CC) in Slot Status
- Timeout at T2 + 1 second because CC is never set in Slot Status
- Write PCC, PIC, etc. to Slot Control
With this change, we wait until T1 + 1 second instead of T2 + 1 second.
If the hotplug event is more than 1 second after the boot-time
initialization, we won't wait for the timeout at all.
We still emit a "Timeout on hotplug command" message if it timed out; we
should see this on the first hotplug event on every controller with this
erratum, as well as on real errors on controllers without the erratum.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 22:55:49 +07:00
|
|
|
ctrl->slot_ctrl,
|
2014-09-23 09:07:35 +07:00
|
|
|
jiffies_to_msecs(jiffies - ctrl->cmd_started));
|
2006-12-22 08:01:09 +07:00
|
|
|
}
|
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
|
|
|
|
u16 mask, bool wait)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2007-05-31 23:43:34 +07:00
|
|
|
u16 slot_ctrl;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2006-12-22 08:01:09 +07:00
|
|
|
mutex_lock(&ctrl->ctrl_lock);
|
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
/*
|
|
|
|
* Always wait for any previous command that might still be in progress
|
|
|
|
*/
|
PCI: pciehp: Wait for hotplug command completion lazily
Previously we issued a hotplug command and waited for it to complete. But
there's no need to wait until we're ready to issue the *next* command. The
next command will probably be much later, so the first one may have already
completed and we may not have to actually wait at all.
Because of hardware errata, some controllers generate command completion
events for some commands but not others. In the case of Intel CF118 (see
spec update reference), the controller indicates command completion only
for Slot Control writes that change the value of the following bits:
Power Controller Control
Power Indicator Control
Attention Indicator Control
Electromechanical Interlock Control
Changes to other bits, e.g., the interrupt enable bits, do not cause the
Command Completed bit to be set. Controllers from AMD and Nvidia are
reported to have similar errata.
These errata cause timeouts when pcie_enable_notification() enables
interrupts. Previously that timeout occurred at boot-time. With this
change, the timeout occurs later, when we change the state of the slot
power, indicators, or interlock. This speeds up boot but causes a timeout
at the first hotplug event on the slot. Subsequent events don't timeout
because only the first (boot-time) hotplug command updates Slot Control
without touching the power/indicator/interlock controls.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 04:06:40 +07:00
|
|
|
pcie_wait_cmd(ctrl);
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
|
PCI: pciehp: Handle invalid data when reading from non-existent devices
It's platform-dependent, but an MMIO read to a non-existent PCI device
generally returns data with all bits set. This happens when the host
bridge or Root Complex times out waiting for a response from the device and
fabricates return data to complete the CPU's read.
One example, reported in the bugzilla below, involved this hierarchy:
pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port
pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port
pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port
pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port
pci 0000:06:00.0: PCI bridge to [bus 07] Thunderbolt Downstream Port
pci 0000:07:00.0: BCM57762 NIC
Unplugging the Thunderbolt switch and the NIC below it resulted in this:
pciehp 0000:03:03.0: Surprise Removal
tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff
pciehp 0000:06:00.0: unloading service driver pciehp
pciehp 0000:06:00.0: pcie_isr: intr_loc 11f
pciehp 0000:06:00.0: Switch interrupt received
pciehp 0000:06:00.0: Latch open on Slot
pciehp 0000:06:00.0: Attention button interrupt received
pciehp 0000:06:00.0: Button pressed on Slot
pciehp 0000:06:00.0: Presence/Notify input change
pciehp 0000:06:00.0: Card present on Slot
pciehp 0000:06:00.0: Power fault interrupt received
pciehp 0000:06:00.0: Data Link Layer State change
pciehp 0000:06:00.0: Link Up event
The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0
and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver
remove methods.
Since the NIC was already gone, tg3 received 0xffffffff when it tried to
read from the device. The resulting timeout is a tg3 issue and not of
interest here.
Similarly, since the 06:00.0 Thunderbolt switch was already gone,
pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp
thought that was valid status showing that many events had happened: the
latch had been opened, the attention button had been pressed, a card was
now present, and the link was now up. These are all wrong, of course, but
pciehp went on to try to power up and enumerate devices below the
non-existent bridge:
pciehp 0000:06:00.0: PCI slot - powering on due to button press
pciehp 0000:06:00.0: Surprise Insertion
pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff
[bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-07-21 23:25:30 +07:00
|
|
|
if (slot_ctrl == (u16) ~0) {
|
|
|
|
ctrl_info(ctrl, "%s: no response from device\n", __func__);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2007-05-31 23:43:34 +07:00
|
|
|
slot_ctrl &= ~mask;
|
2008-04-26 04:39:14 +07:00
|
|
|
slot_ctrl |= (cmd & mask);
|
2007-05-31 23:43:34 +07:00
|
|
|
ctrl->cmd_busy = 1;
|
2008-04-26 04:39:02 +07:00
|
|
|
smp_mb();
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
|
PCI: pciehp: Compute timeout from hotplug command start time
If we issue a hotplug command, go do something else, then come back and
wait for the command to complete, we don't have to wait the whole timeout
period, because some of it elapsed while we were doing something else.
Keep track of the time we issued the command, and wait only until the
timeout period from that point has elapsed.
For controllers with errata like Intel CF118, we previously timed out
before issuing the second hotplug command:
At time T1 (during boot):
- Write DLLSCE, ABPE, PDCE, etc. to Slot Control
At time T2 (hotplug event):
- Wait for command completion (CC) in Slot Status
- Timeout at T2 + 1 second because CC is never set in Slot Status
- Write PCC, PIC, etc. to Slot Control
With this change, we wait until T1 + 1 second instead of T2 + 1 second.
If the hotplug event is more than 1 second after the boot-time
initialization, we won't wait for the timeout at all.
We still emit a "Timeout on hotplug command" message if it timed out; we
should see this on the first hotplug event on every controller with this
erratum, as well as on real errors on controllers without the erratum.
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Tested-by: Rajat Jain <rajatxjain@gmail.com> (IDT 807a controller)
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
2014-06-14 22:55:49 +07:00
|
|
|
ctrl->cmd_started = jiffies;
|
2014-06-14 02:58:35 +07:00
|
|
|
ctrl->slot_ctrl = slot_ctrl;
|
2007-05-31 23:43:34 +07:00
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
/*
|
|
|
|
* Optionally wait for the hardware to be ready for a new command,
|
|
|
|
* indicating completion of the above issued command.
|
|
|
|
*/
|
|
|
|
if (wait)
|
|
|
|
pcie_wait_cmd(ctrl);
|
|
|
|
|
PCI: pciehp: Handle invalid data when reading from non-existent devices
It's platform-dependent, but an MMIO read to a non-existent PCI device
generally returns data with all bits set. This happens when the host
bridge or Root Complex times out waiting for a response from the device and
fabricates return data to complete the CPU's read.
One example, reported in the bugzilla below, involved this hierarchy:
pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port
pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port
pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port
pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port
pci 0000:06:00.0: PCI bridge to [bus 07] Thunderbolt Downstream Port
pci 0000:07:00.0: BCM57762 NIC
Unplugging the Thunderbolt switch and the NIC below it resulted in this:
pciehp 0000:03:03.0: Surprise Removal
tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff
pciehp 0000:06:00.0: unloading service driver pciehp
pciehp 0000:06:00.0: pcie_isr: intr_loc 11f
pciehp 0000:06:00.0: Switch interrupt received
pciehp 0000:06:00.0: Latch open on Slot
pciehp 0000:06:00.0: Attention button interrupt received
pciehp 0000:06:00.0: Button pressed on Slot
pciehp 0000:06:00.0: Presence/Notify input change
pciehp 0000:06:00.0: Card present on Slot
pciehp 0000:06:00.0: Power fault interrupt received
pciehp 0000:06:00.0: Data Link Layer State change
pciehp 0000:06:00.0: Link Up event
The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0
and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver
remove methods.
Since the NIC was already gone, tg3 received 0xffffffff when it tried to
read from the device. The resulting timeout is a tg3 issue and not of
interest here.
Similarly, since the 06:00.0 Thunderbolt switch was already gone,
pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp
thought that was valid status showing that many events had happened: the
latch had been opened, the attention button had been pressed, a card was
now present, and the link was now up. These are all wrong, of course, but
pciehp went on to try to power up and enumerate devices below the
non-existent bridge:
pciehp 0000:06:00.0: PCI slot - powering on due to button press
pciehp 0000:06:00.0: Surprise Insertion
pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff
[bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-07-21 23:25:30 +07:00
|
|
|
out:
|
2006-12-22 08:01:09 +07:00
|
|
|
mutex_unlock(&ctrl->ctrl_lock);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
/**
|
|
|
|
* pcie_write_cmd - Issue controller command
|
|
|
|
* @ctrl: controller to which the command is issued
|
|
|
|
* @cmd: command value written to slot control register
|
|
|
|
* @mask: bitmask of slot control register to be modified
|
|
|
|
*/
|
|
|
|
static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
|
|
|
|
{
|
|
|
|
pcie_do_write_cmd(ctrl, cmd, mask, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Same as above without waiting for the hardware to latch */
|
|
|
|
static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
|
|
|
|
{
|
|
|
|
pcie_do_write_cmd(ctrl, cmd, mask, false);
|
|
|
|
}
|
|
|
|
|
2014-02-05 09:28:43 +07:00
|
|
|
bool pciehp_check_link_active(struct controller *ctrl)
|
2008-10-22 12:31:44 +07:00
|
|
|
{
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2012-01-28 01:55:12 +07:00
|
|
|
u16 lnk_status;
|
2013-12-15 03:06:07 +07:00
|
|
|
bool ret;
|
2008-10-22 12:31:44 +07:00
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
|
2012-01-28 01:55:12 +07:00
|
|
|
ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
|
|
|
|
|
|
|
|
return ret;
|
2008-10-22 12:31:44 +07:00
|
|
|
}
|
|
|
|
|
2012-01-28 01:55:13 +07:00
|
|
|
static void __pcie_wait_link_active(struct controller *ctrl, bool active)
|
2008-10-22 12:31:44 +07:00
|
|
|
{
|
|
|
|
int timeout = 1000;
|
|
|
|
|
2014-02-05 09:28:43 +07:00
|
|
|
if (pciehp_check_link_active(ctrl) == active)
|
2008-10-22 12:31:44 +07:00
|
|
|
return;
|
|
|
|
while (timeout > 0) {
|
|
|
|
msleep(10);
|
|
|
|
timeout -= 10;
|
2014-02-05 09:28:43 +07:00
|
|
|
if (pciehp_check_link_active(ctrl) == active)
|
2008-10-22 12:31:44 +07:00
|
|
|
return;
|
|
|
|
}
|
2012-01-28 01:55:13 +07:00
|
|
|
ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
|
|
|
|
active ? "set" : "cleared");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pcie_wait_link_active(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
__pcie_wait_link_active(ctrl, true);
|
|
|
|
}
|
|
|
|
|
2012-01-28 01:55:11 +07:00
|
|
|
static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
|
|
|
|
{
|
|
|
|
u32 l;
|
|
|
|
int count = 0;
|
|
|
|
int delay = 1000, step = 20;
|
|
|
|
bool found = false;
|
|
|
|
|
|
|
|
do {
|
|
|
|
found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
|
|
|
|
count++;
|
|
|
|
|
|
|
|
if (found)
|
|
|
|
break;
|
|
|
|
|
|
|
|
msleep(step);
|
|
|
|
delay -= step;
|
|
|
|
} while (delay > 0);
|
|
|
|
|
|
|
|
if (count > 1 && pciehp_debug)
|
|
|
|
printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
|
|
|
|
pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
|
|
|
|
PCI_FUNC(devfn), count, step, l);
|
|
|
|
|
|
|
|
return found;
|
|
|
|
}
|
|
|
|
|
2009-09-15 15:30:48 +07:00
|
|
|
int pciehp_check_link_status(struct controller *ctrl)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2013-12-15 03:06:07 +07:00
|
|
|
bool found;
|
2005-04-17 05:20:36 +07:00
|
|
|
u16 lnk_status;
|
|
|
|
|
2014-04-19 07:13:49 +07:00
|
|
|
/*
|
|
|
|
* Data Link Layer Link Active Reporting must be capable for
|
|
|
|
* hot-plug capable downstream port. But old controller might
|
|
|
|
* not implement it. In this case, we wait for 1000 ms.
|
|
|
|
*/
|
|
|
|
if (ctrl->link_active_reporting)
|
|
|
|
pcie_wait_link_active(ctrl);
|
|
|
|
else
|
|
|
|
msleep(1000);
|
2008-10-22 12:31:44 +07:00
|
|
|
|
2012-01-28 01:55:11 +07:00
|
|
|
/* wait 100ms before read pci conf, and try in 1s */
|
|
|
|
msleep(100);
|
|
|
|
found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
|
|
|
|
PCI_DEVFN(0, 0));
|
2011-11-10 14:40:37 +07:00
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
|
2008-09-05 10:11:26 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
|
2008-12-19 13:19:02 +07:00
|
|
|
if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
|
|
|
|
!(lnk_status & PCI_EXP_LNKSTA_NLW)) {
|
2015-06-16 04:28:29 +07:00
|
|
|
ctrl_err(ctrl, "link training error: status %#06x\n",
|
|
|
|
lnk_status);
|
2013-12-15 03:06:07 +07:00
|
|
|
return -1;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2011-11-07 22:53:23 +07:00
|
|
|
pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
if (!found)
|
|
|
|
return -1;
|
2012-01-28 01:55:11 +07:00
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
return 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2012-01-28 01:55:14 +07:00
|
|
|
static int __pciehp_link_set(struct controller *ctrl, bool enable)
|
|
|
|
{
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2012-01-28 01:55:14 +07:00
|
|
|
u16 lnk_ctrl;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
|
2012-01-28 01:55:14 +07:00
|
|
|
|
|
|
|
if (enable)
|
|
|
|
lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
|
|
|
|
else
|
|
|
|
lnk_ctrl |= PCI_EXP_LNKCTL_LD;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
|
2012-01-28 01:55:14 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
|
2013-12-15 03:06:07 +07:00
|
|
|
return 0;
|
2012-01-28 01:55:14 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pciehp_link_enable(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
return __pciehp_link_set(ctrl, true);
|
|
|
|
}
|
|
|
|
|
2013-12-15 03:06:16 +07:00
|
|
|
void pciehp_get_attention_status(struct slot *slot, u8 *status)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
u16 slot_ctrl;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-12-15 03:06:53 +07:00
|
|
|
switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
|
|
|
|
case PCI_EXP_SLTCTL_ATTN_IND_ON:
|
2005-04-17 05:20:36 +07:00
|
|
|
*status = 1; /* On */
|
|
|
|
break;
|
2013-12-15 03:06:53 +07:00
|
|
|
case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
|
2005-04-17 05:20:36 +07:00
|
|
|
*status = 2; /* Blink */
|
|
|
|
break;
|
2013-12-15 03:06:53 +07:00
|
|
|
case PCI_EXP_SLTCTL_ATTN_IND_OFF:
|
2005-04-17 05:20:36 +07:00
|
|
|
*status = 0; /* Off */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
*status = 0xFF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-15 03:06:16 +07:00
|
|
|
void pciehp_get_power_status(struct slot *slot, u8 *status)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
u16 slot_ctrl;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-12-15 03:06:53 +07:00
|
|
|
switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
|
|
|
|
case PCI_EXP_SLTCTL_PWR_ON:
|
|
|
|
*status = 1; /* On */
|
2005-04-17 05:20:36 +07:00
|
|
|
break;
|
2013-12-15 03:06:53 +07:00
|
|
|
case PCI_EXP_SLTCTL_PWR_OFF:
|
|
|
|
*status = 0; /* Off */
|
2005-04-17 05:20:36 +07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
*status = 0xFF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-15 03:06:16 +07:00
|
|
|
void pciehp_get_latch_status(struct slot *slot, u8 *status)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-12-15 03:06:07 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(slot->ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
u16 slot_status;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
2008-12-19 13:19:02 +07:00
|
|
|
*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2013-12-15 03:06:16 +07:00
|
|
|
void pciehp_get_adapter_status(struct slot *slot, u8 *status)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-12-15 03:06:07 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(slot->ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
u16 slot_status;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
2008-12-19 13:19:02 +07:00
|
|
|
*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2009-09-15 15:30:48 +07:00
|
|
|
int pciehp_query_power_fault(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-12-15 03:06:07 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(slot->ctrl);
|
2005-04-17 05:20:36 +07:00
|
|
|
u16 slot_status;
|
|
|
|
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
2008-12-19 13:19:02 +07:00
|
|
|
return !!(slot_status & PCI_EXP_SLTSTA_PFD);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2013-12-15 03:06:16 +07:00
|
|
|
void pciehp_set_attention_status(struct slot *slot, u8 value)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-05-31 23:43:34 +07:00
|
|
|
u16 slot_cmd;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-12-16 07:23:54 +07:00
|
|
|
if (!ATTN_LED(ctrl))
|
|
|
|
return;
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
switch (value) {
|
2014-04-19 07:13:49 +07:00
|
|
|
case 0: /* turn off */
|
2013-12-15 03:06:53 +07:00
|
|
|
slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
|
2009-10-05 15:42:59 +07:00
|
|
|
break;
|
|
|
|
case 1: /* turn on */
|
2013-12-15 03:06:53 +07:00
|
|
|
slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
|
2009-10-05 15:42:59 +07:00
|
|
|
break;
|
|
|
|
case 2: /* turn blink */
|
2013-12-15 03:06:53 +07:00
|
|
|
slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
|
2009-10-05 15:42:59 +07:00
|
|
|
break;
|
|
|
|
default:
|
2013-12-15 03:06:16 +07:00
|
|
|
return;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2015-06-09 06:10:50 +07:00
|
|
|
pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2009-09-15 15:30:48 +07:00
|
|
|
void pciehp_green_led_on(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-08-10 06:09:34 +07:00
|
|
|
|
2013-12-16 07:23:54 +07:00
|
|
|
if (!PWR_LED(ctrl))
|
|
|
|
return;
|
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
|
|
|
|
PCI_EXP_SLTCTL_PIC);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
2013-12-15 03:06:53 +07:00
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
|
|
PCI_EXP_SLTCTL_PWR_IND_ON);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2009-09-15 15:30:48 +07:00
|
|
|
void pciehp_green_led_off(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-12-16 07:23:54 +07:00
|
|
|
if (!PWR_LED(ctrl))
|
|
|
|
return;
|
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
|
|
|
|
PCI_EXP_SLTCTL_PIC);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
2013-12-15 03:06:53 +07:00
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
|
|
PCI_EXP_SLTCTL_PWR_IND_OFF);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2009-09-15 15:30:48 +07:00
|
|
|
void pciehp_green_led_blink(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-08-10 06:09:34 +07:00
|
|
|
|
2013-12-16 07:23:54 +07:00
|
|
|
if (!PWR_LED(ctrl))
|
|
|
|
return;
|
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
|
|
|
|
PCI_EXP_SLTCTL_PIC);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
2013-12-15 03:06:53 +07:00
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
|
|
PCI_EXP_SLTCTL_PWR_IND_BLINK);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2014-04-19 07:13:49 +07:00
|
|
|
int pciehp_power_on_slot(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2007-05-31 23:43:34 +07:00
|
|
|
u16 slot_status;
|
2013-12-15 03:06:07 +07:00
|
|
|
int retval;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2005-11-24 06:44:54 +07:00
|
|
|
/* Clear sticky power-fault bit from previous power failures */
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
|
2013-12-15 03:06:40 +07:00
|
|
|
if (slot_status & PCI_EXP_SLTSTA_PFD)
|
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
|
|
PCI_EXP_SLTSTA_PFD);
|
2009-11-13 13:14:10 +07:00
|
|
|
ctrl->power_fault_detected = 0;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-12-15 03:06:53 +07:00
|
|
|
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
2013-12-15 03:06:53 +07:00
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
|
|
PCI_EXP_SLTCTL_PWR_ON);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-01-28 01:55:15 +07:00
|
|
|
retval = pciehp_link_enable(ctrl);
|
|
|
|
if (retval)
|
|
|
|
ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2014-04-19 07:13:49 +07:00
|
|
|
void pciehp_power_off_slot(struct slot *slot)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = slot->ctrl;
|
2007-12-20 17:45:09 +07:00
|
|
|
|
2013-12-15 03:06:53 +07:00
|
|
|
pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
|
2009-11-11 12:34:52 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
2013-12-15 03:06:53 +07:00
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
|
|
|
|
PCI_EXP_SLTCTL_PWR_OFF);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2006-12-22 08:01:04 +07:00
|
|
|
static irqreturn_t pcie_isr(int irq, void *dev_id)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2006-12-22 08:01:04 +07:00
|
|
|
struct controller *ctrl = (struct controller *)dev_id;
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device
Powering off a hot-pluggable device, e.g., with pci_set_power_state(D3cold),
normally generates a hot-remove event that unbinds the driver.
Some drivers expect to remain bound to a device even while they power it
off and back on again. This can be dangerous, because if the device is
removed or replaced while it is powered off, the driver doesn't know that
anything changed. But some drivers accept that risk.
Add pci_ignore_hotplug() for use by drivers that know their device cannot
be removed. Using pci_ignore_hotplug() tells the PCI core that hot-plug
events for the device should be ignored.
The radeon and nouveau drivers use this to switch between a low-power,
integrated GPU and a higher-power, higher-performance discrete GPU. They
power off the unused GPU, but they want to remain bound to it.
This is a reimplementation of f244d8b623da ("ACPIPHP / radeon / nouveau:
Fix VGA switcheroo problem related to hotplug") but extends it to work with
both acpiphp and pciehp.
This fixes a problem where systems with dual GPUs using the radeon drivers
become unusable, freezing every few seconds (see bugzillas below). The
resume of the radeon device may also fail, e.g.,
This fixes problems on dual GPU systems where the radeon driver becomes
unusable because of problems while suspending the device, as in bug 79701:
[drm] radeon: finishing device.
radeon 0000:01:00.0: Userspace still has active objects !
radeon 0000:01:00.0: ffff8800cb4ec288 ffff8800cb4ec000 16384 4294967297 force free
...
WARNING: CPU: 0 PID: 67 at /home/apw/COD/linux/drivers/gpu/drm/radeon/radeon_gart.c:234 radeon_gart_unbind+0xd2/0xe0 [radeon]()
trying to unbind memory from uninitialized GART !
or while resuming it, as in bug 77261:
radeon 0000:01:00.0: ring 0 stalled for more than 10158msec
radeon 0000:01:00.0: GPU lockup ...
radeon 0000:01:00.0: GPU pci config reset
pciehp 0000:00:01.0:pcie04: Card not present on Slot(1-1)
radeon 0000:01:00.0: GPU reset succeeded, trying to resume
*ERROR* radeon: dpm resume failed
radeon 0000:01:00.0: Wait for MC idle timedout !
Link: https://bugzilla.kernel.org/show_bug.cgi?id=77261
Link: https://bugzilla.kernel.org/show_bug.cgi?id=79701
Reported-by: Shawn Starr <shawn.starr@rogers.com>
Reported-by: Jose P. <lbdkmjdf@sharklasers.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Rajat Jain <rajatxjain@gmail.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Dave Airlie <airlied@redhat.com>
CC: stable@vger.kernel.org # v3.15+
2014-09-11 02:45:01 +07:00
|
|
|
struct pci_bus *subordinate = pdev->subordinate;
|
|
|
|
struct pci_dev *dev;
|
2009-09-15 15:24:46 +07:00
|
|
|
struct slot *slot = ctrl->slot;
|
2008-04-26 04:38:57 +07:00
|
|
|
u16 detected, intr_loc;
|
2015-06-15 09:35:13 +07:00
|
|
|
u8 open, present;
|
|
|
|
bool link;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2008-04-26 04:38:57 +07:00
|
|
|
/*
|
|
|
|
* In order to guarantee that all interrupt events are
|
|
|
|
* serviced, we need to re-inspect Slot Status register after
|
|
|
|
* clearing what is presumed to be the last pending interrupt.
|
|
|
|
*/
|
|
|
|
intr_loc = 0;
|
|
|
|
do {
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
|
PCI: pciehp: Handle invalid data when reading from non-existent devices
It's platform-dependent, but an MMIO read to a non-existent PCI device
generally returns data with all bits set. This happens when the host
bridge or Root Complex times out waiting for a response from the device and
fabricates return data to complete the CPU's read.
One example, reported in the bugzilla below, involved this hierarchy:
pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port
pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port
pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port
pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port
pci 0000:06:00.0: PCI bridge to [bus 07] Thunderbolt Downstream Port
pci 0000:07:00.0: BCM57762 NIC
Unplugging the Thunderbolt switch and the NIC below it resulted in this:
pciehp 0000:03:03.0: Surprise Removal
tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff
pciehp 0000:06:00.0: unloading service driver pciehp
pciehp 0000:06:00.0: pcie_isr: intr_loc 11f
pciehp 0000:06:00.0: Switch interrupt received
pciehp 0000:06:00.0: Latch open on Slot
pciehp 0000:06:00.0: Attention button interrupt received
pciehp 0000:06:00.0: Button pressed on Slot
pciehp 0000:06:00.0: Presence/Notify input change
pciehp 0000:06:00.0: Card present on Slot
pciehp 0000:06:00.0: Power fault interrupt received
pciehp 0000:06:00.0: Data Link Layer State change
pciehp 0000:06:00.0: Link Up event
The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0
and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver
remove methods.
Since the NIC was already gone, tg3 received 0xffffffff when it tried to
read from the device. The resulting timeout is a tg3 issue and not of
interest here.
Similarly, since the 06:00.0 Thunderbolt switch was already gone,
pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp
thought that was valid status showing that many events had happened: the
latch had been opened, the attention button had been pressed, a card was
now present, and the link was now up. These are all wrong, of course, but
pciehp went on to try to power up and enumerate devices below the
non-existent bridge:
pciehp 0000:06:00.0: PCI slot - powering on due to button press
pciehp 0000:06:00.0: Surprise Insertion
pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff
[bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-07-21 23:25:30 +07:00
|
|
|
if (detected == (u16) ~0) {
|
|
|
|
ctrl_info(ctrl, "%s: no response from device\n",
|
|
|
|
__func__);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2008-12-19 13:19:02 +07:00
|
|
|
detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
|
|
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
|
2014-02-05 09:29:10 +07:00
|
|
|
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
|
2009-02-03 13:06:13 +07:00
|
|
|
detected &= ~intr_loc;
|
2008-04-26 04:38:57 +07:00
|
|
|
intr_loc |= detected;
|
|
|
|
if (!intr_loc)
|
2005-04-17 05:20:36 +07:00
|
|
|
return IRQ_NONE;
|
2013-12-15 03:06:07 +07:00
|
|
|
if (detected)
|
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
|
|
intr_loc);
|
2008-04-26 04:38:57 +07:00
|
|
|
} while (detected);
|
2007-08-10 06:09:34 +07:00
|
|
|
|
2015-06-16 04:28:29 +07:00
|
|
|
ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc);
|
2007-08-10 06:09:34 +07:00
|
|
|
|
2008-04-26 04:38:57 +07:00
|
|
|
/* Check Command Complete Interrupt Pending */
|
2008-12-19 13:19:02 +07:00
|
|
|
if (intr_loc & PCI_EXP_SLTSTA_CC) {
|
2006-12-22 08:01:10 +07:00
|
|
|
ctrl->cmd_busy = 0;
|
2008-04-26 04:39:02 +07:00
|
|
|
smp_mb();
|
2008-05-28 12:59:44 +07:00
|
|
|
wake_up(&ctrl->queue);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device
Powering off a hot-pluggable device, e.g., with pci_set_power_state(D3cold),
normally generates a hot-remove event that unbinds the driver.
Some drivers expect to remain bound to a device even while they power it
off and back on again. This can be dangerous, because if the device is
removed or replaced while it is powered off, the driver doesn't know that
anything changed. But some drivers accept that risk.
Add pci_ignore_hotplug() for use by drivers that know their device cannot
be removed. Using pci_ignore_hotplug() tells the PCI core that hot-plug
events for the device should be ignored.
The radeon and nouveau drivers use this to switch between a low-power,
integrated GPU and a higher-power, higher-performance discrete GPU. They
power off the unused GPU, but they want to remain bound to it.
This is a reimplementation of f244d8b623da ("ACPIPHP / radeon / nouveau:
Fix VGA switcheroo problem related to hotplug") but extends it to work with
both acpiphp and pciehp.
This fixes a problem where systems with dual GPUs using the radeon drivers
become unusable, freezing every few seconds (see bugzillas below). The
resume of the radeon device may also fail, e.g.,
This fixes problems on dual GPU systems where the radeon driver becomes
unusable because of problems while suspending the device, as in bug 79701:
[drm] radeon: finishing device.
radeon 0000:01:00.0: Userspace still has active objects !
radeon 0000:01:00.0: ffff8800cb4ec288 ffff8800cb4ec000 16384 4294967297 force free
...
WARNING: CPU: 0 PID: 67 at /home/apw/COD/linux/drivers/gpu/drm/radeon/radeon_gart.c:234 radeon_gart_unbind+0xd2/0xe0 [radeon]()
trying to unbind memory from uninitialized GART !
or while resuming it, as in bug 77261:
radeon 0000:01:00.0: ring 0 stalled for more than 10158msec
radeon 0000:01:00.0: GPU lockup ...
radeon 0000:01:00.0: GPU pci config reset
pciehp 0000:00:01.0:pcie04: Card not present on Slot(1-1)
radeon 0000:01:00.0: GPU reset succeeded, trying to resume
*ERROR* radeon: dpm resume failed
radeon 0000:01:00.0: Wait for MC idle timedout !
Link: https://bugzilla.kernel.org/show_bug.cgi?id=77261
Link: https://bugzilla.kernel.org/show_bug.cgi?id=79701
Reported-by: Shawn Starr <shawn.starr@rogers.com>
Reported-by: Jose P. <lbdkmjdf@sharklasers.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Rajat Jain <rajatxjain@gmail.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Dave Airlie <airlied@redhat.com>
CC: stable@vger.kernel.org # v3.15+
2014-09-11 02:45:01 +07:00
|
|
|
if (subordinate) {
|
|
|
|
list_for_each_entry(dev, &subordinate->devices, bus_list) {
|
|
|
|
if (dev->ignore_hotplug) {
|
|
|
|
ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
|
|
|
|
intr_loc, pci_name(dev));
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-12-19 13:19:02 +07:00
|
|
|
if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
|
2008-05-27 17:03:16 +07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
2008-04-26 04:38:57 +07:00
|
|
|
/* Check MRL Sensor Changed */
|
2015-06-15 09:35:13 +07:00
|
|
|
if (intr_loc & PCI_EXP_SLTSTA_MRLSC) {
|
|
|
|
pciehp_get_latch_status(slot, &open);
|
|
|
|
ctrl_info(ctrl, "Latch %s on Slot(%s)\n",
|
|
|
|
open ? "open" : "close", slot_name(slot));
|
|
|
|
pciehp_queue_interrupt_event(slot, open ? INT_SWITCH_OPEN :
|
|
|
|
INT_SWITCH_CLOSE);
|
|
|
|
}
|
2006-12-22 08:01:04 +07:00
|
|
|
|
2008-04-26 04:38:57 +07:00
|
|
|
/* Check Attention Button Pressed */
|
2015-06-15 09:35:13 +07:00
|
|
|
if (intr_loc & PCI_EXP_SLTSTA_ABP) {
|
|
|
|
ctrl_info(ctrl, "Button pressed on Slot(%s)\n",
|
|
|
|
slot_name(slot));
|
|
|
|
pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
|
|
|
|
}
|
2006-12-22 08:01:04 +07:00
|
|
|
|
2008-04-26 04:38:57 +07:00
|
|
|
/* Check Presence Detect Changed */
|
2015-06-15 09:35:13 +07:00
|
|
|
if (intr_loc & PCI_EXP_SLTSTA_PDC) {
|
|
|
|
pciehp_get_adapter_status(slot, &present);
|
|
|
|
ctrl_info(ctrl, "Card %spresent on Slot(%s)\n",
|
|
|
|
present ? "" : "not ", slot_name(slot));
|
|
|
|
pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
|
|
|
|
INT_PRESENCE_OFF);
|
|
|
|
}
|
2006-12-22 08:01:04 +07:00
|
|
|
|
2008-04-26 04:38:57 +07:00
|
|
|
/* Check Power Fault Detected */
|
2009-02-03 13:06:16 +07:00
|
|
|
if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
|
|
|
|
ctrl->power_fault_detected = 1;
|
2015-06-15 09:35:13 +07:00
|
|
|
ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(slot));
|
|
|
|
pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
|
2009-02-03 13:06:16 +07:00
|
|
|
}
|
2014-02-05 09:29:10 +07:00
|
|
|
|
2015-06-15 09:35:13 +07:00
|
|
|
if (intr_loc & PCI_EXP_SLTSTA_DLLSC) {
|
|
|
|
link = pciehp_check_link_active(ctrl);
|
|
|
|
ctrl_info(ctrl, "slot(%s): Link %s event\n",
|
|
|
|
slot_name(slot), link ? "Up" : "Down");
|
|
|
|
pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
|
|
|
|
INT_LINK_DOWN);
|
|
|
|
}
|
2014-02-05 09:29:10 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2013-12-15 03:06:16 +07:00
|
|
|
void pcie_enable_notification(struct controller *ctrl)
|
2007-11-22 06:07:55 +07:00
|
|
|
{
|
2008-04-26 04:39:05 +07:00
|
|
|
u16 cmd, mask;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2009-11-13 13:14:10 +07:00
|
|
|
/*
|
|
|
|
* TBD: Power fault detected software notification support.
|
|
|
|
*
|
|
|
|
* Power fault detected software notification is not enabled
|
|
|
|
* now, because it caused power fault detected interrupt storm
|
|
|
|
* on some machines. On those machines, power fault detected
|
|
|
|
* bit in the slot status register was set again immediately
|
|
|
|
* when it is cleared in the interrupt service routine, and
|
|
|
|
* next power fault detected interrupt was notified again.
|
|
|
|
*/
|
2014-02-05 09:29:23 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Always enable link events: thus link-up and link-down shall
|
|
|
|
* always be treated as hotplug and unplug respectively. Enable
|
|
|
|
* presence detect only if Attention Button is not present.
|
|
|
|
*/
|
|
|
|
cmd = PCI_EXP_SLTCTL_DLLSCE;
|
2008-04-26 04:39:06 +07:00
|
|
|
if (ATTN_BUTTN(ctrl))
|
2008-12-19 13:19:02 +07:00
|
|
|
cmd |= PCI_EXP_SLTCTL_ABPE;
|
2014-02-05 09:29:23 +07:00
|
|
|
else
|
|
|
|
cmd |= PCI_EXP_SLTCTL_PDCE;
|
2008-04-26 04:39:06 +07:00
|
|
|
if (MRL_SENS(ctrl))
|
2008-12-19 13:19:02 +07:00
|
|
|
cmd |= PCI_EXP_SLTCTL_MRLSCE;
|
2008-04-26 04:39:05 +07:00
|
|
|
if (!pciehp_poll_mode)
|
2008-12-19 13:19:02 +07:00
|
|
|
cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
|
2008-04-26 04:39:05 +07:00
|
|
|
|
2008-12-19 13:19:02 +07:00
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
|
|
PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
|
2014-02-05 09:29:23 +07:00
|
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
|
|
|
PCI_EXP_SLTCTL_DLLSCE);
|
2008-04-26 04:39:05 +07:00
|
|
|
|
2015-06-09 06:10:50 +07:00
|
|
|
pcie_write_cmd_nowait(ctrl, cmd, mask);
|
2014-09-23 09:36:09 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
|
2008-06-20 10:07:08 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pcie_disable_notification(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
u16 mask;
|
2013-12-15 03:06:16 +07:00
|
|
|
|
2008-12-19 13:19:02 +07:00
|
|
|
mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
|
|
|
|
PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
|
2009-10-05 15:40:02 +07:00
|
|
|
PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
|
|
|
|
PCI_EXP_SLTCTL_DLLSCE);
|
2013-12-15 03:06:16 +07:00
|
|
|
pcie_write_cmd(ctrl, 0, mask);
|
2014-09-23 09:36:09 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
|
2008-06-20 10:07:08 +07:00
|
|
|
}
|
|
|
|
|
2013-08-09 03:09:37 +07:00
|
|
|
/*
|
|
|
|
* pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
|
2014-02-19 09:53:19 +07:00
|
|
|
* bus reset of the bridge, but at the same time we want to ensure that it is
|
|
|
|
* not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
|
|
|
|
* disable link state notification and presence detection change notification
|
|
|
|
* momentarily, if we see that they could interfere. Also, clear any spurious
|
2013-08-09 03:09:37 +07:00
|
|
|
* events after.
|
|
|
|
*/
|
|
|
|
int pciehp_reset_slot(struct slot *slot, int probe)
|
|
|
|
{
|
|
|
|
struct controller *ctrl = slot->ctrl;
|
2013-05-10 00:26:16 +07:00
|
|
|
struct pci_dev *pdev = ctrl_dev(ctrl);
|
2014-02-05 09:30:40 +07:00
|
|
|
u16 stat_mask = 0, ctrl_mask = 0;
|
2013-08-09 03:09:37 +07:00
|
|
|
|
|
|
|
if (probe)
|
|
|
|
return 0;
|
|
|
|
|
2014-02-19 09:53:19 +07:00
|
|
|
if (!ATTN_BUTTN(ctrl)) {
|
2014-02-05 09:30:40 +07:00
|
|
|
ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
|
|
|
|
stat_mask |= PCI_EXP_SLTSTA_PDC;
|
2013-08-09 03:09:37 +07:00
|
|
|
}
|
2014-02-05 09:30:40 +07:00
|
|
|
ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
|
|
|
|
stat_mask |= PCI_EXP_SLTSTA_DLLSC;
|
|
|
|
|
|
|
|
pcie_write_cmd(ctrl, 0, ctrl_mask);
|
2014-09-23 09:36:09 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
|
2014-02-05 09:30:40 +07:00
|
|
|
if (pciehp_poll_mode)
|
|
|
|
del_timer_sync(&ctrl->poll_timer);
|
2013-08-09 03:09:37 +07:00
|
|
|
|
|
|
|
pci_reset_bridge_secondary_bus(ctrl->pcie->port);
|
|
|
|
|
2014-02-05 09:30:40 +07:00
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
|
2015-06-09 06:10:50 +07:00
|
|
|
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
|
2014-09-23 09:36:09 +07:00
|
|
|
ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
|
|
|
|
pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
|
2014-02-05 09:30:40 +07:00
|
|
|
if (pciehp_poll_mode)
|
|
|
|
int_poll_timeout(ctrl->poll_timer.data);
|
2013-08-09 03:09:37 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-01-29 10:31:18 +07:00
|
|
|
int pcie_init_notification(struct controller *ctrl)
|
2008-06-20 10:07:08 +07:00
|
|
|
{
|
|
|
|
if (pciehp_request_irq(ctrl))
|
|
|
|
return -1;
|
2013-12-15 03:06:16 +07:00
|
|
|
pcie_enable_notification(ctrl);
|
2009-01-29 10:31:18 +07:00
|
|
|
ctrl->notification_enabled = 1;
|
2008-06-20 10:07:08 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pcie_shutdown_notification(struct controller *ctrl)
|
|
|
|
{
|
2009-01-29 10:31:18 +07:00
|
|
|
if (ctrl->notification_enabled) {
|
|
|
|
pcie_disable_notification(ctrl);
|
|
|
|
pciehp_free_irq(ctrl);
|
|
|
|
ctrl->notification_enabled = 0;
|
|
|
|
}
|
2008-06-20 10:07:08 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pcie_init_slot(struct controller *ctrl)
|
|
|
|
{
|
|
|
|
struct slot *slot;
|
|
|
|
|
|
|
|
slot = kzalloc(sizeof(*slot), GFP_KERNEL);
|
|
|
|
if (!slot)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2013-07-04 05:04:57 +07:00
|
|
|
slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
|
2013-01-11 09:15:54 +07:00
|
|
|
if (!slot->wq)
|
|
|
|
goto abort;
|
|
|
|
|
2008-06-20 10:07:08 +07:00
|
|
|
slot->ctrl = ctrl;
|
|
|
|
mutex_init(&slot->lock);
|
2014-02-05 09:31:11 +07:00
|
|
|
mutex_init(&slot->hotplug_lock);
|
2008-06-20 10:07:08 +07:00
|
|
|
INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
|
2009-09-15 15:24:46 +07:00
|
|
|
ctrl->slot = slot;
|
2005-04-17 05:20:36 +07:00
|
|
|
return 0;
|
2013-01-11 09:15:54 +07:00
|
|
|
abort:
|
|
|
|
kfree(slot);
|
|
|
|
return -ENOMEM;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2007-11-29 06:11:46 +07:00
|
|
|
|
2008-06-20 10:07:08 +07:00
|
|
|
static void pcie_cleanup_slot(struct controller *ctrl)
|
|
|
|
{
|
2009-09-15 15:24:46 +07:00
|
|
|
struct slot *slot = ctrl->slot;
|
2008-06-20 10:07:08 +07:00
|
|
|
cancel_delayed_work(&slot->work);
|
2013-01-11 09:15:54 +07:00
|
|
|
destroy_workqueue(slot->wq);
|
2008-06-20 10:07:08 +07:00
|
|
|
kfree(slot);
|
|
|
|
}
|
|
|
|
|
2008-04-26 04:39:08 +07:00
|
|
|
static inline void dbg_ctrl(struct controller *ctrl)
|
2007-11-29 06:11:46 +07:00
|
|
|
{
|
2009-09-15 15:30:14 +07:00
|
|
|
struct pci_dev *pdev = ctrl->pcie->port;
|
2015-06-16 04:28:29 +07:00
|
|
|
u16 reg16;
|
2007-11-29 06:11:46 +07:00
|
|
|
|
2008-04-26 04:39:08 +07:00
|
|
|
if (!pciehp_debug)
|
|
|
|
return;
|
2007-11-29 06:11:46 +07:00
|
|
|
|
2008-09-05 10:11:26 +07:00
|
|
|
ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
|
2013-05-10 00:26:16 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
|
2008-09-05 10:11:26 +07:00
|
|
|
ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
|
2013-05-10 00:26:16 +07:00
|
|
|
pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
|
2008-09-05 10:11:26 +07:00
|
|
|
ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
|
2008-04-26 04:39:08 +07:00
|
|
|
}
|
2007-11-29 06:11:46 +07:00
|
|
|
|
2014-04-19 07:13:49 +07:00
|
|
|
#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
|
2013-12-15 03:06:36 +07:00
|
|
|
|
2008-06-20 10:07:08 +07:00
|
|
|
struct controller *pcie_init(struct pcie_device *dev)
|
2008-04-26 04:39:08 +07:00
|
|
|
{
|
2008-06-20 10:07:08 +07:00
|
|
|
struct controller *ctrl;
|
2008-10-22 12:31:44 +07:00
|
|
|
u32 slot_cap, link_cap;
|
2008-04-26 04:39:08 +07:00
|
|
|
struct pci_dev *pdev = dev->port;
|
2007-11-29 06:11:46 +07:00
|
|
|
|
2008-06-20 10:07:08 +07:00
|
|
|
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
|
|
|
|
if (!ctrl) {
|
2008-10-23 09:47:32 +07:00
|
|
|
dev_err(&dev->device, "%s: Out of memory\n", __func__);
|
2008-06-20 10:07:08 +07:00
|
|
|
goto abort;
|
|
|
|
}
|
2008-08-22 15:16:48 +07:00
|
|
|
ctrl->pcie = dev;
|
2013-12-15 03:06:07 +07:00
|
|
|
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
|
2008-04-26 04:39:08 +07:00
|
|
|
ctrl->slot_cap = slot_cap;
|
2007-11-29 06:11:46 +07:00
|
|
|
mutex_init(&ctrl->ctrl_lock);
|
|
|
|
init_waitqueue_head(&ctrl->queue);
|
2008-04-26 04:39:08 +07:00
|
|
|
dbg_ctrl(ctrl);
|
2014-06-14 23:56:31 +07:00
|
|
|
|
2014-04-19 07:13:49 +07:00
|
|
|
/* Check if Data Link Layer Link Active Reporting is implemented */
|
|
|
|
pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
|
2015-06-16 04:28:29 +07:00
|
|
|
if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
|
2014-04-19 07:13:49 +07:00
|
|
|
ctrl->link_active_reporting = 1;
|
2008-10-22 12:31:44 +07:00
|
|
|
|
2008-06-20 10:07:08 +07:00
|
|
|
/* Clear all remaining event bits in Slot Status register */
|
2013-12-15 03:06:47 +07:00
|
|
|
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
|
|
|
|
PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
|
|
|
|
PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
|
2014-06-18 02:27:34 +07:00
|
|
|
PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
|
2007-11-29 06:11:46 +07:00
|
|
|
|
2015-06-16 04:28:29 +07:00
|
|
|
ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
|
2013-12-15 03:06:36 +07:00
|
|
|
(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
|
2015-06-16 04:28:29 +07:00
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
|
2013-12-15 03:06:36 +07:00
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
|
|
|
|
FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
|
|
|
|
FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
|
2008-06-20 10:07:08 +07:00
|
|
|
|
|
|
|
if (pcie_init_slot(ctrl))
|
|
|
|
goto abort_ctrl;
|
2008-04-26 04:39:08 +07:00
|
|
|
|
2008-06-20 10:07:08 +07:00
|
|
|
return ctrl;
|
|
|
|
|
|
|
|
abort_ctrl:
|
|
|
|
kfree(ctrl);
|
2007-11-29 06:11:46 +07:00
|
|
|
abort:
|
2008-06-20 10:07:08 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2009-09-15 15:30:48 +07:00
|
|
|
void pciehp_release_ctrl(struct controller *ctrl)
|
2008-06-20 10:07:08 +07:00
|
|
|
{
|
|
|
|
pcie_shutdown_notification(ctrl);
|
|
|
|
pcie_cleanup_slot(ctrl);
|
|
|
|
kfree(ctrl);
|
2007-11-29 06:11:46 +07:00
|
|
|
}
|