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linux_dsm_epyc7002/arch/arm/mach-shmobile/headsmp.S

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ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 14:56:55 +07:00
/*
* SMP support for R-Mobile / SH-Mobile
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2010 Takashi Yoshii
*
* Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-30 22:29:12 +07:00
#include <asm/assembler.h>
ARM: mach-shmobile: Clean up headsmp.S Use PAGE_OFFSET and PHYS_OFFSET for secondary_startup entry point as recommended by Russell King. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-20 18:04:50 +07:00
#include <asm/memory.h>
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 14:56:55 +07:00
ARM / mach-shmobile: Invalidate caches when booting secondary cores Make sure L1 caches are invalidated when booting secondary cores. Needed to boot all mach-shmobile SMP systems that are using Cortex-A9 including sh73a0, r8a7779 and EMEV2. Thanks to imx and tegra guys for actual code. Signed-off-by: Magnus Damm <damm@opensource.se> Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-05-09 14:24:59 +07:00
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(shmobile_invalidate_start)
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 14:56:55 +07:00
/*
* Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register.
* We need _long_ jump to the physical address.
*/
ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs Instructions start from boot vector must be ARM mode. This patch specify ARM mode explicitly and use 'bx' instruction to be able to change to Thumb mode. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-10 08:56:36 +07:00
.arm
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 14:56:55 +07:00
.align 12
ARM: shmobile: Add SMP boot function and argument Add code for mach-shmobile to allow specifying boot function and argument. Will initially be used for SMP together with SCU but may in the future also be used for deep sleep resume. This patch removes one inline virtual to physical address conversion. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-10 16:19:36 +07:00
ENTRY(shmobile_boot_vector)
ldr r0, 2f
ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs Instructions start from boot vector must be ARM mode. This patch specify ARM mode explicitly and use 'bx' instruction to be able to change to Thumb mode. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-10 08:56:36 +07:00
ldr r1, 1f
bx r1
ARM: shmobile: Add SMP boot function and argument Add code for mach-shmobile to allow specifying boot function and argument. Will initially be used for SMP together with SCU but may in the future also be used for deep sleep resume. This patch removes one inline virtual to physical address conversion. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-10 16:19:36 +07:00
ENDPROC(shmobile_boot_vector)
ARM: shmobile: Insert align directives before 4 bytes data In thumb2 mode instructions are not align to 4 byte. This patch insert align directives before putting 4 byte data. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-10 08:56:37 +07:00
.align 2
ARM: shmobile: Add SMP boot function and argument Add code for mach-shmobile to allow specifying boot function and argument. Will initially be used for SMP together with SCU but may in the future also be used for deep sleep resume. This patch removes one inline virtual to physical address conversion. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-10 16:19:36 +07:00
.globl shmobile_boot_fn
shmobile_boot_fn:
1: .space 4
.globl shmobile_boot_arg
shmobile_boot_arg:
2: .space 4
ARM: shmobile: Introduce shmobile_boot_size Introduce shmobile_boot_size that can be used by future SMP code to determine the size of the boot code that needs to be copied to internal SRAM. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-08-08 05:14:07 +07:00
.globl shmobile_boot_size
shmobile_boot_size:
.long . - shmobile_boot_vector
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-08-01 01:38:18 +07:00
/*
* Per-CPU SMP boot function/argument selection code based on MPIDR
*/
ENTRY(shmobile_smp_boot)
@ r0 = MPIDR_HWID_BITMASK
mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
and r0, r1, r0 @ r0 = cpu_logical_map() value
mov r1, #0 @ r1 = CPU index
adr r5, 1f @ array of per-cpu mpidr values
adr r6, 2f @ array of per-cpu functions
adr r7, 3f @ array of per-cpu arguments
shmobile_smp_boot_find_mpidr:
ldr r8, [r5, r1, lsl #2]
cmp r8, r0
bne shmobile_smp_boot_next
ldr r9, [r6, r1, lsl #2]
cmp r9, #0
bne shmobile_smp_boot_found
shmobile_smp_boot_next:
add r1, r1, #1
cmp r1, #CONFIG_NR_CPUS
blo shmobile_smp_boot_find_mpidr
b shmobile_smp_sleep
shmobile_smp_boot_found:
ldr r0, [r7, r1, lsl #2]
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-30 22:29:12 +07:00
ret r9
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-08-01 01:38:18 +07:00
ENDPROC(shmobile_smp_boot)
ENTRY(shmobile_smp_sleep)
wfi
b shmobile_smp_boot
ENDPROC(shmobile_smp_sleep)
.globl shmobile_smp_mpidr
shmobile_smp_mpidr:
1: .space CONFIG_NR_CPUS * 4
.globl shmobile_smp_fn
shmobile_smp_fn:
2: .space CONFIG_NR_CPUS * 4
.globl shmobile_smp_arg
shmobile_smp_arg:
3: .space CONFIG_NR_CPUS * 4
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