2019-05-03 03:23:30 +07:00
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/* SPDX-License-Identifier: GPL-2.0
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* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
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* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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#ifndef _SJA1105_H
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#define _SJA1105_H
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#include <linux/dsa/sja1105.h>
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#include <net/dsa.h>
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#include "sja1105_static_config.h"
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#define SJA1105_NUM_PORTS 5
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#define SJA1105_NUM_TC 8
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#define SJA1105ET_FDB_BIN_SIZE 4
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/* Keeps the different addresses between E/T and P/Q/R/S */
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struct sja1105_regs {
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u64 device_id;
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u64 prod_id;
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u64 status;
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u64 rgu;
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u64 config;
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u64 rmii_pll1;
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u64 pad_mii_tx[SJA1105_NUM_PORTS];
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u64 cgu_idiv[SJA1105_NUM_PORTS];
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u64 rgmii_pad_mii_tx[SJA1105_NUM_PORTS];
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u64 mii_tx_clk[SJA1105_NUM_PORTS];
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u64 mii_rx_clk[SJA1105_NUM_PORTS];
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u64 mii_ext_tx_clk[SJA1105_NUM_PORTS];
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u64 mii_ext_rx_clk[SJA1105_NUM_PORTS];
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u64 rgmii_tx_clk[SJA1105_NUM_PORTS];
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u64 rmii_ref_clk[SJA1105_NUM_PORTS];
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u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS];
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u64 mac[SJA1105_NUM_PORTS];
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u64 mac_hl1[SJA1105_NUM_PORTS];
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u64 mac_hl2[SJA1105_NUM_PORTS];
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u64 qlevel[SJA1105_NUM_PORTS];
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};
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struct sja1105_info {
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u64 device_id;
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/* Needed for distinction between P and R, and between Q and S
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* (since the parts with/without SGMII share the same
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* switch core and device_id)
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*/
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u64 part_no;
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const struct sja1105_dynamic_table_ops *dyn_ops;
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const struct sja1105_table_ops *static_ops;
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const struct sja1105_regs *regs;
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int (*reset_cmd)(const void *ctx, const void *data);
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net: dsa: sja1105: Error out if RGMII delays are requested in DT
Documentation/devicetree/bindings/net/ethernet.txt is confusing because
it says what the MAC should not do, but not what it *should* do:
* "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
should not add an RX delay in this case)
The gap in semantics is threefold:
1. Is it illegal for the MAC to apply the Rx internal delay by itself,
and simplify the phy_mode (mask off "rgmii-rxid" into "rgmii") before
passing it to of_phy_connect? The documentation would suggest yes.
1. For "rgmii-rxid", while the situation with the Rx clock skew is more
or less clear (needs to be added by the PHY), what should the MAC
driver do about the Tx delays? Is it an implicit wild card for the
MAC to apply delays in the Tx direction if it can? What if those were
already added as serpentine PCB traces, how could that be made more
obvious through DT bindings so that the MAC doesn't attempt to add
them twice and again potentially break the link?
3. If the interface is a fixed-link and therefore the PHY object is
fixed (a purely software entity that obviously cannot add clock
skew), what is the meaning of the above property?
So an interpretation of the RGMII bindings was chosen that hopefully
does not contradict their intention but also makes them more applied.
The SJA1105 driver understands to act upon "rgmii-*id" phy-mode bindings
if the port is in the PHY role (either explicitly, or if it is a
fixed-link). Otherwise it always passes the duty of setting up delays to
the PHY driver.
The error behavior that this patch adds is required on SJA1105E/T where
the MAC really cannot apply internal delays. If the other end of the
fixed-link cannot apply RGMII delays either (this would be specified
through its own DT bindings), then the situation requires PCB delays.
For SJA1105P/Q/R/S, this is however hardware supported and the error is
thus only temporary. I created a stub function pointer for configuring
delays per-port on RXC and TXC, and will implement it when I have access
to a board with this hardware setup.
Meanwhile do not allow the user to select an invalid configuration.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-05-03 03:23:32 +07:00
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int (*setup_rgmii_delay)(const void *ctx, int port);
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2019-05-03 03:23:30 +07:00
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const char *name;
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};
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struct sja1105_private {
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struct sja1105_static_config static_config;
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net: dsa: sja1105: Error out if RGMII delays are requested in DT
Documentation/devicetree/bindings/net/ethernet.txt is confusing because
it says what the MAC should not do, but not what it *should* do:
* "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
should not add an RX delay in this case)
The gap in semantics is threefold:
1. Is it illegal for the MAC to apply the Rx internal delay by itself,
and simplify the phy_mode (mask off "rgmii-rxid" into "rgmii") before
passing it to of_phy_connect? The documentation would suggest yes.
1. For "rgmii-rxid", while the situation with the Rx clock skew is more
or less clear (needs to be added by the PHY), what should the MAC
driver do about the Tx delays? Is it an implicit wild card for the
MAC to apply delays in the Tx direction if it can? What if those were
already added as serpentine PCB traces, how could that be made more
obvious through DT bindings so that the MAC doesn't attempt to add
them twice and again potentially break the link?
3. If the interface is a fixed-link and therefore the PHY object is
fixed (a purely software entity that obviously cannot add clock
skew), what is the meaning of the above property?
So an interpretation of the RGMII bindings was chosen that hopefully
does not contradict their intention but also makes them more applied.
The SJA1105 driver understands to act upon "rgmii-*id" phy-mode bindings
if the port is in the PHY role (either explicitly, or if it is a
fixed-link). Otherwise it always passes the duty of setting up delays to
the PHY driver.
The error behavior that this patch adds is required on SJA1105E/T where
the MAC really cannot apply internal delays. If the other end of the
fixed-link cannot apply RGMII delays either (this would be specified
through its own DT bindings), then the situation requires PCB delays.
For SJA1105P/Q/R/S, this is however hardware supported and the error is
thus only temporary. I created a stub function pointer for configuring
delays per-port on RXC and TXC, and will implement it when I have access
to a board with this hardware setup.
Meanwhile do not allow the user to select an invalid configuration.
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-05-03 03:23:32 +07:00
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bool rgmii_rx_delay[SJA1105_NUM_PORTS];
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bool rgmii_tx_delay[SJA1105_NUM_PORTS];
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2019-05-03 03:23:30 +07:00
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const struct sja1105_info *info;
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struct gpio_desc *reset_gpio;
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struct spi_device *spidev;
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struct dsa_switch *ds;
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};
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#include "sja1105_dynamic_config.h"
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struct sja1105_spi_message {
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u64 access;
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u64 read_count;
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u64 address;
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};
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typedef enum {
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SPI_READ = 0,
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SPI_WRITE = 1,
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} sja1105_spi_rw_mode_t;
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/* From sja1105_spi.c */
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int sja1105_spi_send_packed_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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void *packed_buf, size_t size_bytes);
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int sja1105_spi_send_int(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 reg_addr,
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u64 *value, u64 size_bytes);
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int sja1105_spi_send_long_packed_buf(const struct sja1105_private *priv,
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sja1105_spi_rw_mode_t rw, u64 base_addr,
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void *packed_buf, u64 buf_len);
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int sja1105_static_config_upload(struct sja1105_private *priv);
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extern struct sja1105_info sja1105e_info;
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extern struct sja1105_info sja1105t_info;
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extern struct sja1105_info sja1105p_info;
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extern struct sja1105_info sja1105q_info;
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extern struct sja1105_info sja1105r_info;
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extern struct sja1105_info sja1105s_info;
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/* From sja1105_clocking.c */
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typedef enum {
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XMII_MAC = 0,
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XMII_PHY = 1,
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} sja1105_mii_role_t;
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typedef enum {
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XMII_MODE_MII = 0,
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XMII_MODE_RMII = 1,
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XMII_MODE_RGMII = 2,
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} sja1105_phy_interface_t;
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typedef enum {
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SJA1105_SPEED_10MBPS = 3,
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SJA1105_SPEED_100MBPS = 2,
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SJA1105_SPEED_1000MBPS = 1,
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SJA1105_SPEED_AUTO = 0,
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} sja1105_speed_t;
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int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
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int sja1105_clocking_setup(struct sja1105_private *priv);
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2019-05-03 03:23:35 +07:00
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/* From sja1105_ethtool.c */
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void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
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void sja1105_get_strings(struct dsa_switch *ds, int port,
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u32 stringset, u8 *data);
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int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
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2019-05-03 03:23:30 +07:00
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2019-05-03 03:23:35 +07:00
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/* From sja1105_dynamic_config.c */
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2019-05-03 03:23:30 +07:00
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int sja1105_dynamic_config_read(struct sja1105_private *priv,
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enum sja1105_blk_idx blk_idx,
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int index, void *entry);
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int sja1105_dynamic_config_write(struct sja1105_private *priv,
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enum sja1105_blk_idx blk_idx,
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int index, void *entry, bool keep);
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2019-05-03 03:23:31 +07:00
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u8 sja1105_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
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2019-05-03 03:23:30 +07:00
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/* Common implementations for the static and dynamic configs */
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size_t sja1105_l2_forwarding_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105pqrs_l2_lookup_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105et_l2_lookup_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105_vlan_lookup_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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size_t sja1105pqrs_mac_config_entry_packing(void *buf, void *entry_ptr,
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enum packing_op op);
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#endif
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