mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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229 lines
6.4 KiB
C
229 lines
6.4 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2018 Intel Corp
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*
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* Author:
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* Manasi Navare <manasi.d.navare@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/byteorder/generic.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_dsc.h>
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/**
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* DOC: dsc helpers
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*
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* These functions contain some common logic and helpers to deal with VESA
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* Display Stream Compression standard required for DSC on Display Port/eDP or
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* MIPI display interfaces.
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*/
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/**
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* drm_dsc_dp_pps_header_init() - Initializes the PPS Header
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* for DisplayPort as per the DP 1.4 spec.
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* @pps_sdp: Secondary data packet for DSC Picture Parameter Set
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*/
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void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
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{
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memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
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pps_sdp->pps_header.HB1 = DP_SDP_PPS;
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pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
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}
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EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
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/**
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* drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
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* using the DSC configuration parameters in the order expected
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* by the DSC Display Sink device. For the DSC, the sink device
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* expects the PPS payload in the big endian format for the fields
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* that span more than 1 byte.
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*
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* @pps_sdp:
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* Secondary data packet for DSC Picture Parameter Set
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* @dsc_cfg:
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* DSC Configuration data filled by driver
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*/
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void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
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const struct drm_dsc_config *dsc_cfg)
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{
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int i;
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/* Protect against someone accidently changing struct size */
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BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
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DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
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memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
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/* PPS 0 */
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pps_sdp->pps_payload.dsc_version =
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dsc_cfg->dsc_version_minor |
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dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
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/* PPS 1, 2 is 0 */
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/* PPS 3 */
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pps_sdp->pps_payload.pps_3 =
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dsc_cfg->line_buf_depth |
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dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
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/* PPS 4 */
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pps_sdp->pps_payload.pps_4 =
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((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
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DSC_PPS_MSB_SHIFT) |
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dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
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dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
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dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
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dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
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/* PPS 5 */
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pps_sdp->pps_payload.bits_per_pixel_low =
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(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
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/*
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* The DSC panel expects the PPS packet to have big endian format
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* for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
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* to big endian format. If format is little endian, it will swap
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* bytes to convert to Big endian else keep it unchanged.
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*/
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/* PPS 6, 7 */
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pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
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/* PPS 8, 9 */
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pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
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/* PPS 10, 11 */
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pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
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/* PPS 12, 13 */
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pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
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/* PPS 14, 15 */
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pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
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/* PPS 16 */
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pps_sdp->pps_payload.initial_xmit_delay_high =
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((dsc_cfg->initial_xmit_delay &
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DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
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DSC_PPS_MSB_SHIFT);
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/* PPS 17 */
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pps_sdp->pps_payload.initial_xmit_delay_low =
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(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
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/* PPS 18, 19 */
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pps_sdp->pps_payload.initial_dec_delay =
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cpu_to_be16(dsc_cfg->initial_dec_delay);
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/* PPS 20 is 0 */
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/* PPS 21 */
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pps_sdp->pps_payload.initial_scale_value =
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dsc_cfg->initial_scale_value;
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/* PPS 22, 23 */
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pps_sdp->pps_payload.scale_increment_interval =
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cpu_to_be16(dsc_cfg->scale_increment_interval);
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/* PPS 24 */
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pps_sdp->pps_payload.scale_decrement_interval_high =
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((dsc_cfg->scale_decrement_interval &
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DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
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DSC_PPS_MSB_SHIFT);
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/* PPS 25 */
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pps_sdp->pps_payload.scale_decrement_interval_low =
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(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
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/* PPS 26[7:0], PPS 27[7:5] RESERVED */
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/* PPS 27 */
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pps_sdp->pps_payload.first_line_bpg_offset =
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dsc_cfg->first_line_bpg_offset;
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/* PPS 28, 29 */
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pps_sdp->pps_payload.nfl_bpg_offset =
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cpu_to_be16(dsc_cfg->nfl_bpg_offset);
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/* PPS 30, 31 */
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pps_sdp->pps_payload.slice_bpg_offset =
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cpu_to_be16(dsc_cfg->slice_bpg_offset);
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/* PPS 32, 33 */
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pps_sdp->pps_payload.initial_offset =
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cpu_to_be16(dsc_cfg->initial_offset);
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/* PPS 34, 35 */
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pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
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/* PPS 36 */
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pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp;
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/* PPS 37 */
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pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp;
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/* PPS 38, 39 */
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pps_sdp->pps_payload.rc_model_size =
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cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
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/* PPS 40 */
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pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
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/* PPS 41 */
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pps_sdp->pps_payload.rc_quant_incr_limit0 =
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dsc_cfg->rc_quant_incr_limit0;
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/* PPS 42 */
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pps_sdp->pps_payload.rc_quant_incr_limit1 =
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dsc_cfg->rc_quant_incr_limit1;
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/* PPS 43 */
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pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
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DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
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/* PPS 44 - 57 */
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for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
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pps_sdp->pps_payload.rc_buf_thresh[i] =
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dsc_cfg->rc_buf_thresh[i];
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/* PPS 58 - 87 */
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/*
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* For DSC sink programming the RC Range parameter fields
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* are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
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*/
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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pps_sdp->pps_payload.rc_range_parameters[i] =
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((dsc_cfg->rc_range_params[i].range_min_qp <<
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DSC_PPS_RC_RANGE_MINQP_SHIFT) |
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(dsc_cfg->rc_range_params[i].range_max_qp <<
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DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
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(dsc_cfg->rc_range_params[i].range_bpg_offset));
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pps_sdp->pps_payload.rc_range_parameters[i] =
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cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
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}
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/* PPS 88 */
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pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 |
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dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
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/* PPS 89 */
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pps_sdp->pps_payload.second_line_bpg_offset =
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dsc_cfg->second_line_bpg_offset;
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/* PPS 90, 91 */
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pps_sdp->pps_payload.nsl_bpg_offset =
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cpu_to_be16(dsc_cfg->nsl_bpg_offset);
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/* PPS 92, 93 */
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pps_sdp->pps_payload.second_line_offset_adj =
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cpu_to_be16(dsc_cfg->second_line_offset_adj);
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/* PPS 94 - 127 are O */
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}
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EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
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