DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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2010-07-21 05:44:45 +07:00
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* Copyright © 2006-2008,2010 Intel Corporation
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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2010-07-21 05:44:45 +07:00
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* Chris Wilson <chris@chris-wilson.co.uk>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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*/
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2019-05-02 22:02:47 +07:00
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2011-08-31 05:16:33 +07:00
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#include <linux/export.h>
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2019-05-02 22:02:47 +07:00
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#include <linux/i2c-algo-bit.h>
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#include <linux/i2c.h>
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2018-01-09 02:55:41 +07:00
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#include <drm/drm_hdcp.h>
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2012-10-03 00:01:07 +07:00
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#include <drm/i915_drm.h>
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2019-05-02 22:02:47 +07:00
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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#include "i915_drv.h"
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2019-05-02 22:02:47 +07:00
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#include "intel_drv.h"
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#include "intel_gmbus.h"
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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2015-04-01 14:55:04 +07:00
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struct gmbus_pin {
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2012-03-28 01:36:15 +07:00
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const char *name;
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2018-07-28 02:36:47 +07:00
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enum i915_gpio gpio;
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2012-03-28 01:36:15 +07:00
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};
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2015-04-01 14:55:04 +07:00
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/* Map gmbus pin pairs to names and registers. */
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static const struct gmbus_pin gmbus_pins[] = {
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[GMBUS_PIN_SSC] = { "ssc", GPIOB },
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[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
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[GMBUS_PIN_PANEL] = { "panel", GPIOC },
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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2012-03-28 01:36:15 +07:00
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};
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2015-05-06 19:33:43 +07:00
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static const struct gmbus_pin gmbus_pins_bdw[] = {
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[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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2015-05-06 19:33:44 +07:00
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static const struct gmbus_pin gmbus_pins_skl[] = {
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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2015-04-01 14:58:05 +07:00
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static const struct gmbus_pin gmbus_pins_bxt[] = {
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2015-11-05 04:20:00 +07:00
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[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
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[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
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2015-04-01 14:58:05 +07:00
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};
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2017-06-03 03:06:43 +07:00
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static const struct gmbus_pin gmbus_pins_cnp[] = {
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[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
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[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
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[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
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};
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2018-01-12 01:00:09 +07:00
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static const struct gmbus_pin gmbus_pins_icp[] = {
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2018-06-12 07:25:11 +07:00
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[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
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[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
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[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
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[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
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[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
|
2018-01-12 01:00:09 +07:00
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};
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2015-04-01 14:58:05 +07:00
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/* pin is expected to be valid */
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static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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2018-01-12 01:00:09 +07:00
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if (HAS_PCH_ICP(dev_priv))
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return &gmbus_pins_icp[pin];
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else if (HAS_PCH_CNP(dev_priv))
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2017-06-03 03:06:43 +07:00
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return &gmbus_pins_cnp[pin];
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else if (IS_GEN9_LP(dev_priv))
|
2015-04-01 14:58:05 +07:00
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return &gmbus_pins_bxt[pin];
|
2017-01-24 01:32:37 +07:00
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else if (IS_GEN9_BC(dev_priv))
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2015-05-06 19:33:44 +07:00
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return &gmbus_pins_skl[pin];
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2015-05-06 19:33:43 +07:00
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else if (IS_BROADWELL(dev_priv))
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return &gmbus_pins_bdw[pin];
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2015-04-01 14:58:05 +07:00
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else
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return &gmbus_pins[pin];
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}
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2015-03-27 05:20:22 +07:00
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bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
|
2015-04-01 14:58:05 +07:00
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unsigned int size;
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|
2018-01-12 01:00:09 +07:00
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if (HAS_PCH_ICP(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_icp);
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else if (HAS_PCH_CNP(dev_priv))
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2017-06-03 03:06:43 +07:00
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size = ARRAY_SIZE(gmbus_pins_cnp);
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else if (IS_GEN9_LP(dev_priv))
|
2015-04-01 14:58:05 +07:00
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size = ARRAY_SIZE(gmbus_pins_bxt);
|
2017-01-24 01:32:37 +07:00
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else if (IS_GEN9_BC(dev_priv))
|
2015-05-06 19:33:44 +07:00
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size = ARRAY_SIZE(gmbus_pins_skl);
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2015-05-06 19:33:43 +07:00
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else if (IS_BROADWELL(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bdw);
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2015-04-01 14:58:05 +07:00
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else
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size = ARRAY_SIZE(gmbus_pins);
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2018-07-28 02:36:47 +07:00
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return pin < size && get_gmbus_pin(dev_priv, pin)->name;
|
2015-03-27 05:20:22 +07:00
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}
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|
2010-07-21 05:44:45 +07:00
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/* Intel GPIO access functions */
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2012-01-28 17:07:09 +07:00
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#define I2C_RISEFALL_TIME 10
|
2010-07-21 05:44:45 +07:00
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2010-09-24 18:52:03 +07:00
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static inline struct intel_gmbus *
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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return container_of(i2c, struct intel_gmbus, adapter);
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}
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|
2010-07-21 05:44:45 +07:00
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void
|
2019-05-02 22:02:47 +07:00
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intel_gmbus_reset(struct drm_i915_private *dev_priv)
|
2009-04-07 10:02:28 +07:00
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{
|
2015-09-19 00:03:38 +07:00
|
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I915_WRITE(GMBUS0, 0);
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|
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I915_WRITE(GMBUS4, 0);
|
2010-07-21 05:44:45 +07:00
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}
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|
2017-12-09 04:37:38 +07:00
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static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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bool enable)
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2010-07-21 05:44:45 +07:00
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{
|
2010-09-12 03:48:25 +07:00
|
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u32 val;
|
2009-04-07 10:02:28 +07:00
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
|
2010-09-12 03:48:25 +07:00
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val = I915_READ(DSPCLK_GATE_D);
|
2017-12-09 04:37:38 +07:00
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if (!enable)
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val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
|
2009-04-07 10:02:28 +07:00
|
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else
|
2017-12-09 04:37:38 +07:00
|
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|
val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
|
2010-09-12 03:48:25 +07:00
|
|
|
I915_WRITE(DSPCLK_GATE_D, val);
|
2009-04-07 10:02:28 +07:00
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}
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|
2017-12-22 03:24:32 +07:00
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static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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bool enable)
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|
{
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u32 val;
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val = I915_READ(SOUTH_DSPCLK_GATE_D);
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if (!enable)
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val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
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}
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|
|
static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
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bool enable)
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{
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|
u32 val;
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|
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val = I915_READ(GEN9_CLKGATE_DIS_4);
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if (!enable)
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val |= BXT_GMBUS_GATING_DIS;
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|
else
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val &= ~BXT_GMBUS_GATING_DIS;
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I915_WRITE(GEN9_CLKGATE_DIS_4, val);
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|
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|
}
|
|
|
|
|
2012-02-15 04:37:22 +07:00
|
|
|
static u32 get_reserved(struct intel_gmbus *bus)
|
2010-09-24 18:52:03 +07:00
|
|
|
{
|
2012-02-15 04:37:22 +07:00
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
2010-09-24 18:52:03 +07:00
|
|
|
u32 reserved = 0;
|
|
|
|
|
|
|
|
/* On most chips, these bits must be preserved in software. */
|
2016-11-30 22:43:04 +07:00
|
|
|
if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
|
2012-02-15 04:37:22 +07:00
|
|
|
reserved = I915_READ_NOTRACE(bus->gpio_reg) &
|
2010-11-08 16:58:16 +07:00
|
|
|
(GPIO_DATA_PULLUP_DISABLE |
|
|
|
|
GPIO_CLOCK_PULLUP_DISABLE);
|
2010-09-24 18:52:03 +07:00
|
|
|
|
|
|
|
return reserved;
|
|
|
|
}
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
static int get_clock(void *data)
|
|
|
|
{
|
2012-02-15 04:37:22 +07:00
|
|
|
struct intel_gmbus *bus = data;
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
u32 reserved = get_reserved(bus);
|
|
|
|
I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
|
|
|
|
I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
|
|
|
|
return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int get_data(void *data)
|
|
|
|
{
|
2012-02-15 04:37:22 +07:00
|
|
|
struct intel_gmbus *bus = data;
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
u32 reserved = get_reserved(bus);
|
|
|
|
I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
|
|
|
|
I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
|
|
|
|
return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_clock(void *data, int state_high)
|
|
|
|
{
|
2012-02-15 04:37:22 +07:00
|
|
|
struct intel_gmbus *bus = data;
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
u32 reserved = get_reserved(bus);
|
2010-09-24 18:52:03 +07:00
|
|
|
u32 clock_bits;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
|
|
|
if (state_high)
|
|
|
|
clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
|
|
|
|
else
|
|
|
|
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
|
|
|
|
GPIO_CLOCK_VAL_MASK;
|
2010-07-21 05:44:45 +07:00
|
|
|
|
2012-02-15 04:37:22 +07:00
|
|
|
I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
|
|
|
|
POSTING_READ(bus->gpio_reg);
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void set_data(void *data, int state_high)
|
|
|
|
{
|
2012-02-15 04:37:22 +07:00
|
|
|
struct intel_gmbus *bus = data;
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
u32 reserved = get_reserved(bus);
|
2010-09-24 18:52:03 +07:00
|
|
|
u32 data_bits;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
|
|
|
|
if (state_high)
|
|
|
|
data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
|
|
|
|
else
|
|
|
|
data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
|
|
|
|
GPIO_DATA_VAL_MASK;
|
|
|
|
|
2012-02-15 04:37:22 +07:00
|
|
|
I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
|
|
|
|
POSTING_READ(bus->gpio_reg);
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
}
|
|
|
|
|
2012-03-28 01:36:13 +07:00
|
|
|
static int
|
|
|
|
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct intel_gmbus *bus = container_of(adapter,
|
|
|
|
struct intel_gmbus,
|
|
|
|
adapter);
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
|
2019-05-02 22:02:47 +07:00
|
|
|
intel_gmbus_reset(dev_priv);
|
2017-12-09 04:37:38 +07:00
|
|
|
|
|
|
|
if (IS_PINEVIEW(dev_priv))
|
|
|
|
pnv_gmbus_clock_gating(dev_priv, false);
|
|
|
|
|
2012-03-28 01:36:13 +07:00
|
|
|
set_data(bus, 1);
|
|
|
|
set_clock(bus, 1);
|
|
|
|
udelay(I2C_RISEFALL_TIME);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
intel_gpio_post_xfer(struct i2c_adapter *adapter)
|
|
|
|
{
|
|
|
|
struct intel_gmbus *bus = container_of(adapter,
|
|
|
|
struct intel_gmbus,
|
|
|
|
adapter);
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
|
|
|
|
set_data(bus, 1);
|
|
|
|
set_clock(bus, 1);
|
2017-12-09 04:37:38 +07:00
|
|
|
|
|
|
|
if (IS_PINEVIEW(dev_priv))
|
|
|
|
pnv_gmbus_clock_gating(dev_priv, true);
|
2012-03-28 01:36:13 +07:00
|
|
|
}
|
|
|
|
|
2012-03-28 01:36:15 +07:00
|
|
|
static void
|
2015-04-01 14:55:04 +07:00
|
|
|
intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
|
2009-12-02 02:56:30 +07:00
|
|
|
{
|
2012-02-15 04:37:22 +07:00
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
struct i2c_algo_bit_data *algo;
|
2009-12-02 02:56:30 +07:00
|
|
|
|
2012-02-28 06:43:09 +07:00
|
|
|
algo = &bus->bit_algo;
|
2012-02-15 04:37:22 +07:00
|
|
|
|
2018-07-28 02:36:47 +07:00
|
|
|
bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
|
2012-02-28 06:43:09 +07:00
|
|
|
bus->adapter.algo_data = algo;
|
2012-02-15 04:37:22 +07:00
|
|
|
algo->setsda = set_data;
|
|
|
|
algo->setscl = set_clock;
|
|
|
|
algo->getsda = get_data;
|
|
|
|
algo->getscl = get_clock;
|
2012-03-28 01:36:13 +07:00
|
|
|
algo->pre_xfer = intel_gpio_pre_xfer;
|
|
|
|
algo->post_xfer = intel_gpio_post_xfer;
|
2012-02-15 04:37:22 +07:00
|
|
|
algo->udelay = I2C_RISEFALL_TIME;
|
|
|
|
algo->timeout = usecs_to_jiffies(2200);
|
|
|
|
algo->data = bus;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
}
|
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
|
2012-12-01 19:53:43 +07:00
|
|
|
{
|
2012-12-01 19:53:45 +07:00
|
|
|
DEFINE_WAIT(wait);
|
2016-08-19 23:45:02 +07:00
|
|
|
u32 gmbus2;
|
|
|
|
int ret;
|
2013-03-19 15:56:57 +07:00
|
|
|
|
2012-12-01 19:53:45 +07:00
|
|
|
/* Important: The hw handles only the first bit, so set only one! Since
|
|
|
|
* we also need to check for NAKs besides the hw ready/idle signal, we
|
2016-08-19 23:45:02 +07:00
|
|
|
* need to wake up periodically and check that ourselves.
|
|
|
|
*/
|
|
|
|
if (!HAS_GMBUS_IRQ(dev_priv))
|
|
|
|
irq_en = 0;
|
2012-12-01 19:53:45 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
|
|
|
I915_WRITE_FW(GMBUS4, irq_en);
|
2012-12-01 19:53:43 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
status |= GMBUS_SATOER;
|
|
|
|
ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
|
|
|
|
if (ret)
|
|
|
|
ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
|
2012-12-01 19:53:45 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS4, 0);
|
|
|
|
remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
2012-12-01 19:53:43 +07:00
|
|
|
|
|
|
|
if (gmbus2 & GMBUS_SATOER)
|
|
|
|
return -ENXIO;
|
2016-08-19 23:45:02 +07:00
|
|
|
|
|
|
|
return ret;
|
2012-12-01 19:53:43 +07:00
|
|
|
}
|
|
|
|
|
2012-12-01 19:53:46 +07:00
|
|
|
static int
|
|
|
|
gmbus_wait_idle(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2016-08-19 23:45:02 +07:00
|
|
|
DEFINE_WAIT(wait);
|
|
|
|
u32 irq_enable;
|
2012-12-01 19:53:46 +07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Important: The hw handles only the first bit, so set only one! */
|
2016-08-19 23:45:02 +07:00
|
|
|
irq_enable = 0;
|
|
|
|
if (HAS_GMBUS_IRQ(dev_priv))
|
|
|
|
irq_enable = GMBUS_IDLE_EN;
|
2012-12-01 19:53:46 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
|
|
|
I915_WRITE_FW(GMBUS4, irq_enable);
|
2012-12-01 19:53:46 +07:00
|
|
|
|
2019-03-26 04:49:38 +07:00
|
|
|
ret = intel_wait_for_register_fw(&dev_priv->uncore,
|
2016-08-19 23:45:02 +07:00
|
|
|
GMBUS2, GMBUS_ACTIVE, 0,
|
|
|
|
10);
|
2012-12-01 19:53:46 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS4, 0);
|
|
|
|
remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
|
|
|
|
|
|
|
|
return ret;
|
2012-12-01 19:53:46 +07:00
|
|
|
}
|
|
|
|
|
2018-06-28 20:34:48 +07:00
|
|
|
static inline
|
|
|
|
unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
|
|
|
|
GMBUS_BYTE_COUNT_MAX;
|
|
|
|
}
|
|
|
|
|
2012-03-28 01:36:10 +07:00
|
|
|
static int
|
2015-04-21 23:49:11 +07:00
|
|
|
gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned short addr, u8 *buf, unsigned int len,
|
2018-06-28 20:34:49 +07:00
|
|
|
u32 gmbus0_reg, u32 gmbus1_index)
|
2012-03-28 01:36:10 +07:00
|
|
|
{
|
2018-06-28 20:34:49 +07:00
|
|
|
unsigned int size = len;
|
|
|
|
bool burst_read = len > gmbus_max_xfer_size(dev_priv);
|
|
|
|
bool extra_byte_added = false;
|
|
|
|
|
|
|
|
if (burst_read) {
|
|
|
|
/*
|
|
|
|
* As per HW Spec, for 512Bytes need to read extra Byte and
|
|
|
|
* Ignore the extra byte read.
|
|
|
|
*/
|
|
|
|
if (len == 512) {
|
|
|
|
extra_byte_added = true;
|
|
|
|
len++;
|
|
|
|
}
|
|
|
|
size = len % 256 + 256;
|
|
|
|
I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
|
|
|
|
}
|
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS1,
|
|
|
|
gmbus1_index |
|
|
|
|
GMBUS_CYCLE_WAIT |
|
2018-06-28 20:34:49 +07:00
|
|
|
(size << GMBUS_BYTE_COUNT_SHIFT) |
|
2016-08-19 23:45:02 +07:00
|
|
|
(addr << GMBUS_SLAVE_ADDR_SHIFT) |
|
|
|
|
GMBUS_SLAVE_READ | GMBUS_SW_RDY);
|
2012-04-13 18:47:53 +07:00
|
|
|
while (len) {
|
2012-03-30 18:46:41 +07:00
|
|
|
int ret;
|
2012-03-28 01:36:10 +07:00
|
|
|
u32 val, loop = 0;
|
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
|
2012-03-30 18:46:41 +07:00
|
|
|
if (ret)
|
2012-12-01 19:53:43 +07:00
|
|
|
return ret;
|
2012-03-28 01:36:10 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
val = I915_READ_FW(GMBUS3);
|
2012-03-28 01:36:10 +07:00
|
|
|
do {
|
2018-06-28 20:34:49 +07:00
|
|
|
if (extra_byte_added && len == 1)
|
|
|
|
break;
|
|
|
|
|
2012-03-28 01:36:10 +07:00
|
|
|
*buf++ = val & 0xff;
|
|
|
|
val >>= 8;
|
|
|
|
} while (--len && ++loop < 4);
|
2018-06-28 20:34:49 +07:00
|
|
|
|
|
|
|
if (burst_read && len == size - 4)
|
|
|
|
/* Reset the override bit */
|
|
|
|
I915_WRITE_FW(GMBUS0, gmbus0_reg);
|
2012-04-13 18:47:53 +07:00
|
|
|
}
|
2012-03-28 01:36:10 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-06-28 20:34:49 +07:00
|
|
|
/*
|
|
|
|
* HW spec says that 512Bytes in Burst read need special treatment.
|
|
|
|
* But it doesn't talk about other multiple of 256Bytes. And couldn't locate
|
|
|
|
* an I2C slave, which supports such a lengthy burst read too for experiments.
|
|
|
|
*
|
|
|
|
* So until things get clarified on HW support, to avoid the burst read length
|
|
|
|
* in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
|
|
|
|
*/
|
|
|
|
#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
|
|
|
|
|
2012-03-28 01:36:10 +07:00
|
|
|
static int
|
2015-04-21 23:49:11 +07:00
|
|
|
gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
|
2018-06-28 20:34:49 +07:00
|
|
|
u32 gmbus0_reg, u32 gmbus1_index)
|
2012-03-28 01:36:10 +07:00
|
|
|
{
|
|
|
|
u8 *buf = msg->buf;
|
2015-04-21 23:49:11 +07:00
|
|
|
unsigned int rx_size = msg->len;
|
|
|
|
unsigned int len;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
do {
|
2018-06-28 20:34:49 +07:00
|
|
|
if (HAS_GMBUS_BURST_READ(dev_priv))
|
|
|
|
len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
|
|
|
|
else
|
|
|
|
len = min(rx_size, gmbus_max_xfer_size(dev_priv));
|
2015-04-21 23:49:11 +07:00
|
|
|
|
2018-06-28 20:34:49 +07:00
|
|
|
ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
|
|
|
|
gmbus0_reg, gmbus1_index);
|
2015-04-21 23:49:11 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
rx_size -= len;
|
|
|
|
buf += len;
|
|
|
|
} while (rx_size != 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
|
2018-01-09 02:55:40 +07:00
|
|
|
unsigned short addr, u8 *buf, unsigned int len,
|
|
|
|
u32 gmbus1_index)
|
2015-04-21 23:49:11 +07:00
|
|
|
{
|
|
|
|
unsigned int chunk_size = len;
|
2012-03-28 01:36:10 +07:00
|
|
|
u32 val, loop;
|
|
|
|
|
|
|
|
val = loop = 0;
|
2012-03-30 18:46:36 +07:00
|
|
|
while (len && loop < 4) {
|
|
|
|
val |= *buf++ << (8 * loop++);
|
|
|
|
len -= 1;
|
|
|
|
}
|
2012-03-28 01:36:10 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS3, val);
|
|
|
|
I915_WRITE_FW(GMBUS1,
|
2018-01-09 02:55:40 +07:00
|
|
|
gmbus1_index | GMBUS_CYCLE_WAIT |
|
2016-08-19 23:45:02 +07:00
|
|
|
(chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
|
|
|
|
(addr << GMBUS_SLAVE_ADDR_SHIFT) |
|
|
|
|
GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
|
2012-03-28 01:36:10 +07:00
|
|
|
while (len) {
|
2012-03-30 18:46:41 +07:00
|
|
|
int ret;
|
|
|
|
|
2012-03-28 01:36:10 +07:00
|
|
|
val = loop = 0;
|
|
|
|
do {
|
|
|
|
val |= *buf++ << (8 * loop);
|
|
|
|
} while (--len && ++loop < 4);
|
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS3, val);
|
2012-03-30 18:46:37 +07:00
|
|
|
|
2016-08-19 23:45:02 +07:00
|
|
|
ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
|
2012-03-30 18:46:41 +07:00
|
|
|
if (ret)
|
2012-12-01 19:53:43 +07:00
|
|
|
return ret;
|
2012-03-28 01:36:10 +07:00
|
|
|
}
|
2015-04-21 23:49:11 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2018-01-09 02:55:40 +07:00
|
|
|
gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
|
|
|
|
u32 gmbus1_index)
|
2015-04-21 23:49:11 +07:00
|
|
|
{
|
|
|
|
u8 *buf = msg->buf;
|
|
|
|
unsigned int tx_size = msg->len;
|
|
|
|
unsigned int len;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
do {
|
2018-06-28 20:34:48 +07:00
|
|
|
len = min(tx_size, gmbus_max_xfer_size(dev_priv));
|
2015-04-21 23:49:11 +07:00
|
|
|
|
2018-01-09 02:55:40 +07:00
|
|
|
ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
|
|
|
|
gmbus1_index);
|
2015-04-21 23:49:11 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
buf += len;
|
|
|
|
tx_size -= len;
|
|
|
|
} while (tx_size != 0);
|
|
|
|
|
2012-03-28 01:36:10 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-30 18:46:40 +07:00
|
|
|
/*
|
2018-01-09 02:55:40 +07:00
|
|
|
* The gmbus controller can combine a 1 or 2 byte write with another read/write
|
|
|
|
* that immediately follows it by using an "INDEX" cycle.
|
2012-03-30 18:46:40 +07:00
|
|
|
*/
|
|
|
|
static bool
|
2018-01-09 02:55:40 +07:00
|
|
|
gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
|
2012-03-30 18:46:40 +07:00
|
|
|
{
|
|
|
|
return (i + 1 < num &&
|
2017-11-24 02:41:56 +07:00
|
|
|
msgs[i].addr == msgs[i + 1].addr &&
|
2017-11-24 02:41:57 +07:00
|
|
|
!(msgs[i].flags & I2C_M_RD) &&
|
|
|
|
(msgs[i].len == 1 || msgs[i].len == 2) &&
|
2018-01-09 02:55:40 +07:00
|
|
|
msgs[i + 1].len > 0);
|
2012-03-30 18:46:40 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2018-06-28 20:34:49 +07:00
|
|
|
gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
|
|
|
|
u32 gmbus0_reg)
|
2012-03-30 18:46:40 +07:00
|
|
|
{
|
|
|
|
u32 gmbus1_index = 0;
|
|
|
|
u32 gmbus5 = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (msgs[0].len == 2)
|
|
|
|
gmbus5 = GMBUS_2BYTE_INDEX_EN |
|
|
|
|
msgs[0].buf[1] | (msgs[0].buf[0] << 8);
|
|
|
|
if (msgs[0].len == 1)
|
|
|
|
gmbus1_index = GMBUS_CYCLE_INDEX |
|
|
|
|
(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
|
|
|
|
|
|
|
|
/* GMBUS5 holds 16-bit index */
|
|
|
|
if (gmbus5)
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS5, gmbus5);
|
2012-03-30 18:46:40 +07:00
|
|
|
|
2018-01-09 02:55:40 +07:00
|
|
|
if (msgs[1].flags & I2C_M_RD)
|
2018-06-28 20:34:49 +07:00
|
|
|
ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
|
|
|
|
gmbus1_index);
|
2018-01-09 02:55:40 +07:00
|
|
|
else
|
|
|
|
ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
|
2012-03-30 18:46:40 +07:00
|
|
|
|
|
|
|
/* Clear GMBUS5 after each index transfer */
|
|
|
|
if (gmbus5)
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS5, 0);
|
2012-03-30 18:46:40 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-07-21 05:44:45 +07:00
|
|
|
static int
|
2018-01-09 02:55:41 +07:00
|
|
|
do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
|
|
|
|
u32 gmbus0_source)
|
2010-07-21 05:44:45 +07:00
|
|
|
{
|
|
|
|
struct intel_gmbus *bus = container_of(adapter,
|
|
|
|
struct intel_gmbus,
|
|
|
|
adapter);
|
2012-02-15 04:37:19 +07:00
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
2015-09-19 00:03:38 +07:00
|
|
|
int i = 0, inc, try = 0;
|
drm/i915/intel_i2c: use WAIT cycle, not STOP
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the device has finished (and is in a WAIT phase), and then either
start the next transaction, or, if there are no more transactions,
generate a STOP cycle.
Note: Theoretically, the last transaction of a multi-transaction sequence
could initiate a STOP cycle. However, this slight optimization is left
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
[danvet: added comment to the code that gmbus can't generate STOP on
the very first cycle.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-03-30 18:46:39 +07:00
|
|
|
int ret = 0;
|
2010-07-21 05:44:45 +07:00
|
|
|
|
2017-12-22 03:24:32 +07:00
|
|
|
/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
|
|
|
|
if (IS_GEN9_LP(dev_priv))
|
|
|
|
bxt_gmbus_clock_gating(dev_priv, false);
|
2019-05-06 22:26:27 +07:00
|
|
|
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
|
2017-12-22 03:24:32 +07:00
|
|
|
pch_gmbus_clock_gating(dev_priv, false);
|
|
|
|
|
drm/i915: Fix DDC probe for passive adapters
Passive DP->DVI/HDMI dongles on DP++ ports show up to the system as HDMI
devices, as they do not have a sink device in them to respond to any AUX
traffic. When probing these dongles over the DDC, sometimes they will
NAK the first attempt even though the transaction is valid and they
support the DDC protocol. The retry loop inside of
drm_do_probe_ddc_edid() would normally catch this case and try the
transaction again, resulting in success.
That, however, was thwarted by the fix for [1]:
commit 9292f37e1f5c79400254dca46f83313488093825
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Thu Jan 5 09:34:28 2012 -0200
drm: give up on edid retries when i2c bus is not responding
This added code to exit immediately if the return code from the
i2c_transfer function was -ENXIO in order to reduce the amount of time
spent in waiting for unresponsive or disconnected devices. That was
possible because the underlying i2c bit banging algorithm had retries of
its own (which, of course, were part of the reason for the bug the
commit fixes).
Since its introduction in
commit f899fc64cda8569d0529452aafc0da31c042df2e
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Jul 20 15:44:45 2010 -0700
drm/i915: use GMBUS to manage i2c links
we've been flipping back and forth enabling the GMBUS transfers, but
we've settled since then. The GMBUS implementation does not do any
retries, however, bailing out of the drm_do_probe_ddc_edid() retry loop
on first encounter of -ENXIO. This, combined with Eugeni's commit, broke
the retry on -ENXIO.
Retry GMBUS once on -ENXIO on first message to mitigate the issues with
passive adapters.
This patch is based on the work, and commit message, by Todd Previte
<tprevite@gmail.com>.
[1] https://bugs.freedesktop.org/show_bug.cgi?id=41059
v2: Don't retry if using bit banging.
v3: Move retry within gmbux_xfer, retry only on first message.
v4: Initialize GMBUS0 on retry (Ville).
v5: Take index reads into account (Ville).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85924
Cc: Todd Previte <tprevite@gmail.com>
Cc: stable@vger.kernel.org
Tested-by: Oliver Grafe <oliver.grafe@ge.com> (v2)
Tested-by: Jim Bride <jim.bride@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-02 23:21:15 +07:00
|
|
|
retry:
|
2018-01-09 02:55:41 +07:00
|
|
|
I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
|
2010-07-21 05:44:45 +07:00
|
|
|
|
drm/i915: Fix DDC probe for passive adapters
Passive DP->DVI/HDMI dongles on DP++ ports show up to the system as HDMI
devices, as they do not have a sink device in them to respond to any AUX
traffic. When probing these dongles over the DDC, sometimes they will
NAK the first attempt even though the transaction is valid and they
support the DDC protocol. The retry loop inside of
drm_do_probe_ddc_edid() would normally catch this case and try the
transaction again, resulting in success.
That, however, was thwarted by the fix for [1]:
commit 9292f37e1f5c79400254dca46f83313488093825
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Thu Jan 5 09:34:28 2012 -0200
drm: give up on edid retries when i2c bus is not responding
This added code to exit immediately if the return code from the
i2c_transfer function was -ENXIO in order to reduce the amount of time
spent in waiting for unresponsive or disconnected devices. That was
possible because the underlying i2c bit banging algorithm had retries of
its own (which, of course, were part of the reason for the bug the
commit fixes).
Since its introduction in
commit f899fc64cda8569d0529452aafc0da31c042df2e
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Jul 20 15:44:45 2010 -0700
drm/i915: use GMBUS to manage i2c links
we've been flipping back and forth enabling the GMBUS transfers, but
we've settled since then. The GMBUS implementation does not do any
retries, however, bailing out of the drm_do_probe_ddc_edid() retry loop
on first encounter of -ENXIO. This, combined with Eugeni's commit, broke
the retry on -ENXIO.
Retry GMBUS once on -ENXIO on first message to mitigate the issues with
passive adapters.
This patch is based on the work, and commit message, by Todd Previte
<tprevite@gmail.com>.
[1] https://bugs.freedesktop.org/show_bug.cgi?id=41059
v2: Don't retry if using bit banging.
v3: Move retry within gmbux_xfer, retry only on first message.
v4: Initialize GMBUS0 on retry (Ville).
v5: Take index reads into account (Ville).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85924
Cc: Todd Previte <tprevite@gmail.com>
Cc: stable@vger.kernel.org
Tested-by: Oliver Grafe <oliver.grafe@ge.com> (v2)
Tested-by: Jim Bride <jim.bride@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-02 23:21:15 +07:00
|
|
|
for (; i < num; i += inc) {
|
|
|
|
inc = 1;
|
2018-01-09 02:55:40 +07:00
|
|
|
if (gmbus_is_index_xfer(msgs, i, num)) {
|
2018-06-28 20:34:49 +07:00
|
|
|
ret = gmbus_index_xfer(dev_priv, &msgs[i],
|
|
|
|
gmbus0_source | bus->reg0);
|
2018-01-09 02:55:40 +07:00
|
|
|
inc = 2; /* an index transmission is two msgs */
|
2012-03-30 18:46:40 +07:00
|
|
|
} else if (msgs[i].flags & I2C_M_RD) {
|
2018-06-28 20:34:49 +07:00
|
|
|
ret = gmbus_xfer_read(dev_priv, &msgs[i],
|
|
|
|
gmbus0_source | bus->reg0, 0);
|
2012-03-30 18:46:40 +07:00
|
|
|
} else {
|
2018-01-09 02:55:40 +07:00
|
|
|
ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
|
2012-03-30 18:46:40 +07:00
|
|
|
}
|
2012-03-28 01:36:10 +07:00
|
|
|
|
2015-12-01 21:29:25 +07:00
|
|
|
if (!ret)
|
2016-08-19 23:45:02 +07:00
|
|
|
ret = gmbus_wait(dev_priv,
|
|
|
|
GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
|
2012-03-28 01:36:10 +07:00
|
|
|
if (ret == -ETIMEDOUT)
|
|
|
|
goto timeout;
|
2015-12-01 21:29:25 +07:00
|
|
|
else if (ret)
|
2012-03-28 01:36:10 +07:00
|
|
|
goto clear_err;
|
2010-07-21 05:44:45 +07:00
|
|
|
}
|
|
|
|
|
drm/i915/intel_i2c: use WAIT cycle, not STOP
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the device has finished (and is in a WAIT phase), and then either
start the next transaction, or, if there are no more transactions,
generate a STOP cycle.
Note: Theoretically, the last transaction of a multi-transaction sequence
could initiate a STOP cycle. However, this slight optimization is left
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
[danvet: added comment to the code that gmbus can't generate STOP on
the very first cycle.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-03-30 18:46:39 +07:00
|
|
|
/* Generate a STOP condition on the bus. Note that gmbus can't generata
|
|
|
|
* a STOP on the very first cycle. To simplify the code we
|
|
|
|
* unconditionally generate the STOP condition with an additional gmbus
|
|
|
|
* cycle. */
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
|
drm/i915/intel_i2c: use WAIT cycle, not STOP
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the device has finished (and is in a WAIT phase), and then either
start the next transaction, or, if there are no more transactions,
generate a STOP cycle.
Note: Theoretically, the last transaction of a multi-transaction sequence
could initiate a STOP cycle. However, this slight optimization is left
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
[danvet: added comment to the code that gmbus can't generate STOP on
the very first cycle.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-03-30 18:46:39 +07:00
|
|
|
|
2012-03-30 18:46:38 +07:00
|
|
|
/* Mark the GMBUS interface as disabled after waiting for idle.
|
|
|
|
* We will re-enable it at the start of the next xfer,
|
|
|
|
* till then let it sleep.
|
|
|
|
*/
|
2012-12-01 19:53:46 +07:00
|
|
|
if (gmbus_wait_idle(dev_priv)) {
|
2012-04-13 18:47:54 +07:00
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
|
2012-03-30 18:46:38 +07:00
|
|
|
adapter->name);
|
drm/i915/intel_i2c: use WAIT cycle, not STOP
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the device has finished (and is in a WAIT phase), and then either
start the next transaction, or, if there are no more transactions,
generate a STOP cycle.
Note: Theoretically, the last transaction of a multi-transaction sequence
could initiate a STOP cycle. However, this slight optimization is left
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
[danvet: added comment to the code that gmbus can't generate STOP on
the very first cycle.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-03-30 18:46:39 +07:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
}
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS0, 0);
|
drm/i915/intel_i2c: use WAIT cycle, not STOP
The i915 is only able to generate a STOP cycle (i.e. finalize an i2c
transaction) during a DATA or WAIT phase. In other words, the
controller rejects a STOP requested as part of the first transaction in a
sequence.
Thus, for the first transaction we must always use a WAIT cycle, detect
when the device has finished (and is in a WAIT phase), and then either
start the next transaction, or, if there are no more transactions,
generate a STOP cycle.
Note: Theoretically, the last transaction of a multi-transaction sequence
could initiate a STOP cycle. However, this slight optimization is left
for another patch. We return -ETIMEDOUT if the hardware doesn't
deactivate after the STOP cycle.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
[danvet: added comment to the code that gmbus can't generate STOP on
the very first cycle.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-03-30 18:46:39 +07:00
|
|
|
ret = ret ?: i;
|
2012-03-30 18:46:38 +07:00
|
|
|
goto out;
|
2011-03-30 22:20:43 +07:00
|
|
|
|
|
|
|
clear_err:
|
2012-03-30 18:46:38 +07:00
|
|
|
/*
|
|
|
|
* Wait for bus to IDLE before clearing NAK.
|
|
|
|
* If we clear the NAK while bus is still active, then it will stay
|
|
|
|
* active and the next transaction may fail.
|
2012-05-22 01:19:48 +07:00
|
|
|
*
|
|
|
|
* If no ACK is received during the address phase of a transaction, the
|
|
|
|
* adapter must report -ENXIO. It is not clear what to return if no ACK
|
|
|
|
* is received at other times. But we have to be careful to not return
|
|
|
|
* spurious -ENXIO because that will prevent i2c and drm edid functions
|
|
|
|
* from retrying. So return -ENXIO only when gmbus properly quiescents -
|
|
|
|
* timing out seems to happen when there _is_ a ddc chip present, but
|
|
|
|
* it's slow responding and only answers on the 2nd retry.
|
2012-03-30 18:46:38 +07:00
|
|
|
*/
|
2012-05-22 01:19:48 +07:00
|
|
|
ret = -ENXIO;
|
2012-12-01 19:53:46 +07:00
|
|
|
if (gmbus_wait_idle(dev_priv)) {
|
2012-04-13 18:47:54 +07:00
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
|
|
|
|
adapter->name);
|
2012-05-22 01:19:48 +07:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
}
|
2012-03-30 18:46:38 +07:00
|
|
|
|
2011-03-30 22:20:43 +07:00
|
|
|
/* Toggle the Software Clear Interrupt bit. This has the effect
|
|
|
|
* of resetting the GMBUS controller and so clearing the
|
|
|
|
* BUS_ERROR raised by the slave's NAK.
|
|
|
|
*/
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
|
|
|
|
I915_WRITE_FW(GMBUS1, 0);
|
|
|
|
I915_WRITE_FW(GMBUS0, 0);
|
2011-03-30 22:20:43 +07:00
|
|
|
|
2012-04-13 18:47:54 +07:00
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
|
2012-03-30 18:46:38 +07:00
|
|
|
adapter->name, msgs[i].addr,
|
|
|
|
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
|
|
|
|
|
drm/i915: Fix DDC probe for passive adapters
Passive DP->DVI/HDMI dongles on DP++ ports show up to the system as HDMI
devices, as they do not have a sink device in them to respond to any AUX
traffic. When probing these dongles over the DDC, sometimes they will
NAK the first attempt even though the transaction is valid and they
support the DDC protocol. The retry loop inside of
drm_do_probe_ddc_edid() would normally catch this case and try the
transaction again, resulting in success.
That, however, was thwarted by the fix for [1]:
commit 9292f37e1f5c79400254dca46f83313488093825
Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Thu Jan 5 09:34:28 2012 -0200
drm: give up on edid retries when i2c bus is not responding
This added code to exit immediately if the return code from the
i2c_transfer function was -ENXIO in order to reduce the amount of time
spent in waiting for unresponsive or disconnected devices. That was
possible because the underlying i2c bit banging algorithm had retries of
its own (which, of course, were part of the reason for the bug the
commit fixes).
Since its introduction in
commit f899fc64cda8569d0529452aafc0da31c042df2e
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Jul 20 15:44:45 2010 -0700
drm/i915: use GMBUS to manage i2c links
we've been flipping back and forth enabling the GMBUS transfers, but
we've settled since then. The GMBUS implementation does not do any
retries, however, bailing out of the drm_do_probe_ddc_edid() retry loop
on first encounter of -ENXIO. This, combined with Eugeni's commit, broke
the retry on -ENXIO.
Retry GMBUS once on -ENXIO on first message to mitigate the issues with
passive adapters.
This patch is based on the work, and commit message, by Todd Previte
<tprevite@gmail.com>.
[1] https://bugs.freedesktop.org/show_bug.cgi?id=41059
v2: Don't retry if using bit banging.
v3: Move retry within gmbux_xfer, retry only on first message.
v4: Initialize GMBUS0 on retry (Ville).
v5: Take index reads into account (Ville).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85924
Cc: Todd Previte <tprevite@gmail.com>
Cc: stable@vger.kernel.org
Tested-by: Oliver Grafe <oliver.grafe@ge.com> (v2)
Tested-by: Jim Bride <jim.bride@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-06-02 23:21:15 +07:00
|
|
|
/*
|
|
|
|
* Passive adapters sometimes NAK the first probe. Retry the first
|
|
|
|
* message once on -ENXIO for GMBUS transfers; the bit banging algorithm
|
|
|
|
* has retries internally. See also the retry loop in
|
|
|
|
* drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
|
|
|
|
*/
|
|
|
|
if (ret == -ENXIO && i == 0 && try++ == 0) {
|
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
|
|
|
|
adapter->name);
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
|
2012-02-14 05:36:54 +07:00
|
|
|
goto out;
|
2010-07-21 05:44:45 +07:00
|
|
|
|
|
|
|
timeout:
|
2016-03-07 22:57:00 +07:00
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
|
|
|
|
bus->adapter.name, bus->reg0 & 0xff);
|
2016-08-19 23:45:02 +07:00
|
|
|
I915_WRITE_FW(GMBUS0, 0);
|
2011-03-30 22:20:43 +07:00
|
|
|
|
2015-12-01 21:29:26 +07:00
|
|
|
/*
|
|
|
|
* Hardware may not support GMBUS over these pins? Try GPIO bitbanging
|
|
|
|
* instead. Use EAGAIN to have i2c core retry.
|
|
|
|
*/
|
|
|
|
ret = -EAGAIN;
|
2012-03-28 01:36:13 +07:00
|
|
|
|
2012-02-14 05:36:54 +07:00
|
|
|
out:
|
2017-12-22 03:24:32 +07:00
|
|
|
/* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
|
|
|
|
if (IS_GEN9_LP(dev_priv))
|
|
|
|
bxt_gmbus_clock_gating(dev_priv, true);
|
2019-05-06 22:26:27 +07:00
|
|
|
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
|
2017-12-22 03:24:32 +07:00
|
|
|
pch_gmbus_clock_gating(dev_priv, true);
|
|
|
|
|
2015-12-01 21:29:26 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
|
|
|
|
{
|
2019-01-14 21:21:24 +07:00
|
|
|
struct intel_gmbus *bus =
|
|
|
|
container_of(adapter, struct intel_gmbus, adapter);
|
2015-12-01 21:29:26 +07:00
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_wakeref_t wakeref;
|
2015-12-01 21:29:26 +07:00
|
|
|
int ret;
|
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
|
2015-12-01 21:29:26 +07:00
|
|
|
|
2016-03-07 22:56:59 +07:00
|
|
|
if (bus->force_bit) {
|
2015-12-01 21:29:26 +07:00
|
|
|
ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
|
2016-03-07 22:56:59 +07:00
|
|
|
if (ret < 0)
|
|
|
|
bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
|
|
|
|
} else {
|
2018-01-09 02:55:41 +07:00
|
|
|
ret = do_gmbus_xfer(adapter, msgs, num, 0);
|
2016-03-07 22:56:59 +07:00
|
|
|
if (ret == -EAGAIN)
|
|
|
|
bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
|
|
|
|
}
|
2015-11-09 22:48:19 +07:00
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
|
2015-11-09 22:48:19 +07:00
|
|
|
|
2012-02-14 05:36:54 +07:00
|
|
|
return ret;
|
2010-07-21 05:44:45 +07:00
|
|
|
}
|
|
|
|
|
2018-01-09 02:55:41 +07:00
|
|
|
int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
|
|
|
|
{
|
2019-01-14 21:21:24 +07:00
|
|
|
struct intel_gmbus *bus =
|
|
|
|
container_of(adapter, struct intel_gmbus, adapter);
|
2018-01-09 02:55:41 +07:00
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
u8 cmd = DRM_HDCP_DDC_AKSV;
|
|
|
|
u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
|
|
|
|
struct i2c_msg msgs[] = {
|
|
|
|
{
|
|
|
|
.addr = DRM_HDCP_DDC_ADDR,
|
|
|
|
.flags = 0,
|
|
|
|
.len = sizeof(cmd),
|
|
|
|
.buf = &cmd,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.addr = DRM_HDCP_DDC_ADDR,
|
|
|
|
.flags = 0,
|
|
|
|
.len = sizeof(buf),
|
|
|
|
.buf = buf,
|
|
|
|
}
|
|
|
|
};
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_wakeref_t wakeref;
|
|
|
|
int ret;
|
2018-01-09 02:55:41 +07:00
|
|
|
|
2019-01-14 21:21:24 +07:00
|
|
|
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
|
2018-01-09 02:55:41 +07:00
|
|
|
mutex_lock(&dev_priv->gmbus_mutex);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In order to output Aksv to the receiver, use an indexed write to
|
|
|
|
* pass the i2c command, and tell GMBUS to use the HW-provided value
|
|
|
|
* instead of sourcing GMBUS3 for the data.
|
|
|
|
*/
|
|
|
|
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->gmbus_mutex);
|
2019-01-14 21:21:24 +07:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
|
2018-01-09 02:55:41 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-07-21 05:44:45 +07:00
|
|
|
static u32 gmbus_func(struct i2c_adapter *adapter)
|
|
|
|
{
|
2012-02-15 00:58:49 +07:00
|
|
|
return i2c_bit_algo.functionality(adapter) &
|
|
|
|
(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
|
2010-07-21 05:44:45 +07:00
|
|
|
/* I2C_FUNC_10BIT_ADDR | */
|
|
|
|
I2C_FUNC_SMBUS_READ_BLOCK_DATA |
|
|
|
|
I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm gmbus_algorithm = {
|
|
|
|
.master_xfer = gmbus_xfer,
|
|
|
|
.functionality = gmbus_func
|
|
|
|
};
|
|
|
|
|
2017-07-26 20:26:47 +07:00
|
|
|
static void gmbus_lock_bus(struct i2c_adapter *adapter,
|
|
|
|
unsigned int flags)
|
|
|
|
{
|
|
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->gmbus_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
|
|
|
|
unsigned int flags)
|
|
|
|
{
|
|
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
|
|
|
|
return mutex_trylock(&dev_priv->gmbus_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
|
|
|
|
unsigned int flags)
|
|
|
|
{
|
|
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->gmbus_mutex);
|
|
|
|
}
|
|
|
|
|
2017-09-01 21:31:22 +07:00
|
|
|
static const struct i2c_lock_operations gmbus_lock_ops = {
|
2017-07-26 20:26:47 +07:00
|
|
|
.lock_bus = gmbus_lock_bus,
|
|
|
|
.trylock_bus = gmbus_trylock_bus,
|
|
|
|
.unlock_bus = gmbus_unlock_bus,
|
|
|
|
};
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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/**
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2010-07-21 05:44:45 +07:00
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* intel_gmbus_setup - instantiate all Intel i2c GMBuses
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2016-12-01 21:16:42 +07:00
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* @dev_priv: i915 device private
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
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*/
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2019-05-02 22:02:47 +07:00
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int intel_gmbus_setup(struct drm_i915_private *dev_priv)
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2010-07-21 05:44:45 +07:00
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{
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2016-08-22 17:32:44 +07:00
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struct pci_dev *pdev = dev_priv->drm.pdev;
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2015-04-01 14:55:04 +07:00
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struct intel_gmbus *bus;
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unsigned int pin;
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int ret;
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2010-07-21 05:44:45 +07:00
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2018-12-01 06:20:47 +07:00
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if (!HAS_DISPLAY(dev_priv))
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2013-04-06 03:12:41 +07:00
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return 0;
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2015-11-05 04:20:00 +07:00
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2016-10-14 16:13:44 +07:00
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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2013-01-24 20:29:55 +07:00
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dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
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2019-02-05 05:25:38 +07:00
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else if (!HAS_GMCH(dev_priv))
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2018-07-28 02:36:47 +07:00
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/*
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* Broxton uses the same PCH offsets for South Display Engine,
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* even though it doesn't have a PCH.
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*/
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dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
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2012-03-24 05:43:36 +07:00
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2012-02-14 05:36:54 +07:00
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mutex_init(&dev_priv->gmbus_mutex);
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2012-12-01 19:53:45 +07:00
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init_waitqueue_head(&dev_priv->gmbus_wait_queue);
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2012-02-14 05:36:54 +07:00
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2015-04-01 14:55:04 +07:00
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for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
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2015-03-27 05:20:22 +07:00
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if (!intel_gmbus_is_valid_pin(dev_priv, pin))
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2015-04-01 14:55:04 +07:00
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continue;
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bus = &dev_priv->gmbus[pin];
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2010-07-21 05:44:45 +07:00
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bus->adapter.owner = THIS_MODULE;
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bus->adapter.class = I2C_CLASS_DDC;
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snprintf(bus->adapter.name,
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2010-11-06 00:51:34 +07:00
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sizeof(bus->adapter.name),
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"i915 gmbus %s",
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2015-04-01 14:58:05 +07:00
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get_gmbus_pin(dev_priv, pin)->name);
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2010-07-21 05:44:45 +07:00
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2016-08-22 17:32:44 +07:00
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bus->adapter.dev.parent = &pdev->dev;
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2012-02-15 04:37:19 +07:00
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bus->dev_priv = dev_priv;
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2010-07-21 05:44:45 +07:00
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bus->adapter.algo = &gmbus_algorithm;
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2017-07-26 20:26:47 +07:00
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bus->adapter.lock_ops = &gmbus_lock_ops;
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2010-07-21 05:44:45 +07:00
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2016-03-07 22:56:57 +07:00
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/*
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* We wish to retry with bit banging
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* after a timed out GMBUS attempt.
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*/
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bus->adapter.retries = 1;
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2010-09-24 18:52:03 +07:00
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/* By default use a conservative clock rate */
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2015-04-01 14:55:04 +07:00
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bus->reg0 = pin | GMBUS_RATE_100KHZ;
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2010-09-28 19:35:47 +07:00
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2012-05-13 19:44:20 +07:00
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/* gmbus seems to be broken on i830 */
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2016-10-13 17:02:58 +07:00
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if (IS_I830(dev_priv))
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2012-11-10 22:58:21 +07:00
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bus->force_bit = 1;
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2012-05-13 19:44:20 +07:00
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2015-04-01 14:55:04 +07:00
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intel_gpio_setup(bus, pin);
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2012-08-13 21:33:02 +07:00
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ret = i2c_add_adapter(&bus->adapter);
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if (ret)
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goto err;
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2010-07-21 05:44:45 +07:00
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}
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2019-05-02 22:02:47 +07:00
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intel_gmbus_reset(dev_priv);
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2010-07-21 05:44:45 +07:00
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return 0;
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err:
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2016-02-10 03:11:13 +07:00
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while (pin--) {
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2015-03-27 05:20:22 +07:00
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if (!intel_gmbus_is_valid_pin(dev_priv, pin))
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2015-04-01 14:55:04 +07:00
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continue;
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bus = &dev_priv->gmbus[pin];
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2010-07-21 05:44:45 +07:00
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i2c_del_adapter(&bus->adapter);
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}
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return ret;
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}
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2012-03-28 01:36:14 +07:00
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struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
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2015-03-27 05:20:20 +07:00
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unsigned int pin)
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2012-03-28 01:36:14 +07:00
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{
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2015-03-27 05:20:22 +07:00
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if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
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2015-04-01 14:55:04 +07:00
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return NULL;
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return &dev_priv->gmbus[pin].adapter;
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2012-03-28 01:36:14 +07:00
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}
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2010-09-24 18:52:03 +07:00
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void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
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{
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struct intel_gmbus *bus = to_intel_gmbus(adapter);
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2011-06-17 03:36:28 +07:00
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bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
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2010-09-24 18:52:03 +07:00
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}
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void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
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{
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struct intel_gmbus *bus = to_intel_gmbus(adapter);
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2016-03-07 22:56:58 +07:00
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struct drm_i915_private *dev_priv = bus->dev_priv;
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mutex_lock(&dev_priv->gmbus_mutex);
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2010-09-24 18:52:03 +07:00
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2012-11-10 22:58:21 +07:00
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bus->force_bit += force_bit ? 1 : -1;
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DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
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force_bit ? "en" : "dis", adapter->name,
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bus->force_bit);
|
2016-03-07 22:56:58 +07:00
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mutex_unlock(&dev_priv->gmbus_mutex);
|
2010-09-24 18:52:03 +07:00
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}
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|
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|
2019-05-02 22:02:47 +07:00
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bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
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|
|
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{
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struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
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return bus->force_bit;
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|
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}
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|
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|
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void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
{
|
2015-04-01 14:55:04 +07:00
|
|
|
struct intel_gmbus *bus;
|
|
|
|
unsigned int pin;
|
|
|
|
|
|
|
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for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
2015-03-27 05:20:22 +07:00
|
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
2015-04-01 14:55:04 +07:00
|
|
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continue;
|
2009-05-31 02:16:25 +07:00
|
|
|
|
2015-04-01 14:55:04 +07:00
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bus = &dev_priv->gmbus[pin];
|
2010-07-21 05:44:45 +07:00
|
|
|
i2c_del_adapter(&bus->adapter);
|
|
|
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}
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-08 05:24:08 +07:00
|
|
|
}
|