mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 06:45:09 +07:00
223 lines
10 KiB
C
223 lines
10 KiB
C
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/*
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* Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS4 - CPU PMU(Power Management Unit) support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/soc/samsung/exynos-regs-pmu.h>
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#include <linux/soc/samsung/exynos-pmu.h>
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#include "exynos-pmu.h"
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static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
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/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
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{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
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{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
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{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
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{ S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
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{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
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{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
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{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
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{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ PMU_TABLE_END,},
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};
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static const struct exynos_pmu_conf exynos4x12_pmu_config[] = {
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{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
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{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
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{ S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
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{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
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{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
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{ S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
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/* XXX_OPTION register should be set other field */
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{ S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
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{ S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
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{ S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
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{ S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
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{ S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
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{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
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{ S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
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{ S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
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{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
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{ S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
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{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
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{ S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
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{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
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{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
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{ S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
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{ S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
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{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
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{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
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{ S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
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||
|
|
{ S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||
|
|
{ PMU_TABLE_END,},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
|
||
|
|
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||
|
|
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
|
||
|
|
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
|
||
|
|
{ S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||
|
|
{ S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
|
||
|
|
{ S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
|
||
|
|
{ PMU_TABLE_END,},
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct exynos_pmu_data exynos4210_pmu_data = {
|
||
|
|
.pmu_config = exynos4210_pmu_config,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct exynos_pmu_data exynos4212_pmu_data = {
|
||
|
|
.pmu_config = exynos4x12_pmu_config,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct exynos_pmu_data exynos4412_pmu_data = {
|
||
|
|
.pmu_config = exynos4x12_pmu_config,
|
||
|
|
.pmu_config_extra = exynos4412_pmu_config,
|
||
|
|
};
|