2012-06-22 16:40:48 +07:00
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/*
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* Device Tree Source for AM33XX SoC
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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2013-06-03 21:12:23 +07:00
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#include <dt-bindings/gpio/gpio.h>
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2013-06-03 21:12:25 +07:00
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#include <dt-bindings/pinctrl/am33xx.h>
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2013-06-03 21:12:23 +07:00
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2013-06-03 21:12:22 +07:00
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#include "skeleton.dtsi"
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2012-06-22 16:40:48 +07:00
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/ {
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compatible = "ti,am33xx";
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2012-10-24 15:47:52 +07:00
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interrupt-parent = <&intc>;
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2012-06-22 16:40:48 +07:00
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aliases {
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2013-10-17 03:21:04 +07:00
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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2013-03-28 13:06:05 +07:00
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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2012-11-15 01:08:24 +07:00
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d_can0 = &dcan0;
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d_can1 = &dcan1;
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2013-07-05 19:51:33 +07:00
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usb0 = &usb0;
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usb1 = &usb1;
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phy0 = &usb0_phy;
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phy1 = &usb1_phy;
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2013-10-03 00:58:33 +07:00
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ethernet0 = &cpsw_emac0;
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ethernet1 = &cpsw_emac1;
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2012-06-22 16:40:48 +07:00
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};
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cpus {
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2013-04-19 00:35:59 +07:00
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#address-cells = <1>;
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#size-cells = <0>;
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2012-06-22 16:40:48 +07:00
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cpu@0 {
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compatible = "arm,cortex-a8";
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2013-04-19 00:35:59 +07:00
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device_type = "cpu";
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reg = <0>;
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2012-08-31 16:37:20 +07:00
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/*
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* To consider voltage drop between PMIC and SoC,
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* tolerance value is reduced to 2% from 4% and
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* voltage value is increased as a precaution.
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*/
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operating-points = <
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/* kHz uV */
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720000 1285000
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600000 1225000
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500000 1125000
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275000 1125000
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>;
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voltage-tolerance = <2>; /* 2 percentage */
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2014-01-30 01:19:17 +07:00
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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2012-08-31 16:37:20 +07:00
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clock-latency = <300000>; /* From omap-cpufreq driver */
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2012-06-22 16:40:48 +07:00
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};
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};
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2013-08-04 01:00:54 +07:00
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pmu {
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compatible = "arm,cortex-a8-pmu";
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interrupts = <3>;
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};
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2012-06-22 16:40:48 +07:00
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/*
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2014-03-28 17:11:37 +07:00
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* The soc node represents the soc top level view. It is used for IPs
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2012-06-22 16:40:48 +07:00
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the AM33XX interconnect.
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2014-03-28 17:11:39 +07:00
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* The real AM33XX interconnect network is quite complex. Since
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* it will not bring real advantage to represent that in DT
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2012-06-22 16:40:48 +07:00
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* for the moment, just use a fake OCP bus entry to represent
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* the whole bus hierarchy.
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*/
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ocp {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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2015-03-20 18:08:29 +07:00
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l4_wkup: l4_wkup@44c00000 {
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compatible = "ti,am3-l4-wkup", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x44c00000 0x280000>;
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2013-07-18 22:15:35 +07:00
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2015-03-20 18:08:29 +07:00
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prcm: prcm@200000 {
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compatible = "ti,am3-prcm";
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reg = <0x200000 0x4000>;
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2013-07-18 22:15:35 +07:00
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2015-03-20 18:08:29 +07:00
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prcm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2013-07-18 22:15:35 +07:00
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2015-03-20 18:08:29 +07:00
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prcm_clockdomains: clockdomains {
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};
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2013-07-18 22:15:35 +07:00
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};
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2015-03-20 18:08:29 +07:00
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scm: scm@210000 {
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compatible = "ti,am3-scm", "simple-bus";
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reg = <0x210000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x210000 0x2000>;
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am33xx_pinmux: pinmux@800 {
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compatible = "pinctrl-single";
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reg = <0x800 0x238>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x7f>;
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};
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scm_conf: scm_conf@0 {
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compatible = "syscon";
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reg = <0x0 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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scm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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scm_clockdomains: clockdomains {
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};
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2013-07-18 22:15:35 +07:00
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};
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};
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2012-06-22 16:40:48 +07:00
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intc: interrupt-controller@48200000 {
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2014-09-09 07:54:48 +07:00
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compatible = "ti,am33xx-intc";
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2012-06-22 16:40:48 +07:00
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x48200000 0x1000>;
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};
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2013-09-11 02:24:37 +07:00
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edma: edma@49000000 {
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compatible = "ti,edma3";
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ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
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reg = <0x49000000 0x10000>,
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2014-04-14 01:44:46 +07:00
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<0x44e10f90 0x40>;
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2013-09-11 02:24:37 +07:00
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interrupts = <12 13 14>;
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#dma-cells = <1>;
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};
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2012-11-21 18:52:17 +07:00
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gpio0: gpio@44e07000 {
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2012-06-22 16:40:48 +07:00
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio1";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-08-07 18:06:32 +07:00
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#interrupt-cells = <2>;
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2012-08-27 18:51:01 +07:00
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reg = <0x44e07000 0x1000>;
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interrupts = <96>;
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2012-06-22 16:40:48 +07:00
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};
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2012-11-21 18:52:17 +07:00
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gpio1: gpio@4804c000 {
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2012-06-22 16:40:48 +07:00
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-08-07 18:06:32 +07:00
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#interrupt-cells = <2>;
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2012-08-27 18:51:01 +07:00
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reg = <0x4804c000 0x1000>;
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interrupts = <98>;
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2012-06-22 16:40:48 +07:00
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};
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2012-11-21 18:52:17 +07:00
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gpio2: gpio@481ac000 {
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2012-06-22 16:40:48 +07:00
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-08-07 18:06:32 +07:00
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#interrupt-cells = <2>;
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2012-08-27 18:51:01 +07:00
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reg = <0x481ac000 0x1000>;
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interrupts = <32>;
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2012-06-22 16:40:48 +07:00
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};
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2012-11-21 18:52:17 +07:00
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gpio3: gpio@481ae000 {
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2012-06-22 16:40:48 +07:00
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compatible = "ti,omap4-gpio";
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-08-07 18:06:32 +07:00
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#interrupt-cells = <2>;
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2012-08-27 18:51:01 +07:00
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reg = <0x481ae000 0x1000>;
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interrupts = <62>;
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2012-06-22 16:40:48 +07:00
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};
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2013-03-28 13:06:05 +07:00
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uart0: serial@44e09000 {
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2015-07-14 15:02:06 +07:00
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compatible = "ti,am3352-uart", "ti,omap3-uart";
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2012-06-22 16:40:48 +07:00
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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2012-08-27 18:51:01 +07:00
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reg = <0x44e09000 0x2000>;
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interrupts = <72>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2014-09-30 01:06:46 +07:00
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dmas = <&edma 26>, <&edma 27>;
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dma-names = "tx", "rx";
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2012-06-22 16:40:48 +07:00
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};
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2013-03-28 13:06:05 +07:00
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uart1: serial@48022000 {
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2015-07-14 15:02:06 +07:00
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compatible = "ti,am3352-uart", "ti,omap3-uart";
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2012-06-22 16:40:48 +07:00
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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2012-08-27 18:51:01 +07:00
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reg = <0x48022000 0x2000>;
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interrupts = <73>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2014-09-30 01:06:46 +07:00
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dmas = <&edma 28>, <&edma 29>;
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dma-names = "tx", "rx";
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2012-06-22 16:40:48 +07:00
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};
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2013-03-28 13:06:05 +07:00
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uart2: serial@48024000 {
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2015-07-14 15:02:06 +07:00
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compatible = "ti,am3352-uart", "ti,omap3-uart";
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2012-06-22 16:40:48 +07:00
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ti,hwmods = "uart3";
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clock-frequency = <48000000>;
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2012-08-27 18:51:01 +07:00
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reg = <0x48024000 0x2000>;
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interrupts = <74>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2014-09-30 01:06:46 +07:00
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dmas = <&edma 30>, <&edma 31>;
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dma-names = "tx", "rx";
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2012-06-22 16:40:48 +07:00
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};
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2013-03-28 13:06:05 +07:00
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uart3: serial@481a6000 {
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2015-07-14 15:02:06 +07:00
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compatible = "ti,am3352-uart", "ti,omap3-uart";
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2012-06-22 16:40:48 +07:00
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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2012-08-27 18:51:01 +07:00
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reg = <0x481a6000 0x2000>;
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interrupts = <44>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2012-06-22 16:40:48 +07:00
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};
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2013-03-28 13:06:05 +07:00
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uart4: serial@481a8000 {
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2015-07-14 15:02:06 +07:00
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compatible = "ti,am3352-uart", "ti,omap3-uart";
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2012-06-22 16:40:48 +07:00
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ti,hwmods = "uart5";
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clock-frequency = <48000000>;
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2012-08-27 18:51:01 +07:00
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reg = <0x481a8000 0x2000>;
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interrupts = <45>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2012-06-22 16:40:48 +07:00
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};
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2013-03-28 13:06:05 +07:00
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uart5: serial@481aa000 {
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2015-07-14 15:02:06 +07:00
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compatible = "ti,am3352-uart", "ti,omap3-uart";
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2012-06-22 16:40:48 +07:00
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ti,hwmods = "uart6";
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clock-frequency = <48000000>;
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2012-08-27 18:51:01 +07:00
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reg = <0x481aa000 0x2000>;
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interrupts = <46>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2012-06-22 16:40:48 +07:00
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};
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2012-11-21 18:52:17 +07:00
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i2c0: i2c@44e0b000 {
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2012-06-22 16:40:48 +07:00
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compatible = "ti,omap4-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c1";
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2012-08-27 18:51:01 +07:00
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reg = <0x44e0b000 0x1000>;
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interrupts = <70>;
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2012-08-15 18:23:25 +07:00
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status = "disabled";
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2012-06-22 16:40:48 +07:00
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};
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2012-11-21 18:52:17 +07:00
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i2c1: i2c@4802a000 {
|
2012-06-22 16:40:48 +07:00
|
|
|
compatible = "ti,omap4-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c2";
|
2012-08-27 18:51:01 +07:00
|
|
|
reg = <0x4802a000 0x1000>;
|
|
|
|
|
interrupts = <71>;
|
2012-08-15 18:23:25 +07:00
|
|
|
status = "disabled";
|
2012-06-22 16:40:48 +07:00
|
|
|
};
|
|
|
|
|
|
2012-11-21 18:52:17 +07:00
|
|
|
i2c2: i2c@4819c000 {
|
2012-06-22 16:40:48 +07:00
|
|
|
compatible = "ti,omap4-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c3";
|
2012-08-27 18:51:01 +07:00
|
|
|
reg = <0x4819c000 0x1000>;
|
|
|
|
|
interrupts = <30>;
|
2012-08-15 18:23:25 +07:00
|
|
|
status = "disabled";
|
2012-06-22 16:40:48 +07:00
|
|
|
};
|
2012-07-04 19:30:37 +07:00
|
|
|
|
2013-09-11 02:24:39 +07:00
|
|
|
mmc1: mmc@48060000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
|
|
|
|
ti,hwmods = "mmc1";
|
|
|
|
|
ti,dual-volt;
|
|
|
|
|
ti,needs-special-reset;
|
|
|
|
|
ti,needs-special-hs-handling;
|
|
|
|
|
dmas = <&edma 24
|
|
|
|
|
&edma 25>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
interrupts = <64>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
reg = <0x48060000 0x1000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2: mmc@481d8000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
|
|
|
|
ti,hwmods = "mmc2";
|
|
|
|
|
ti,needs-special-reset;
|
|
|
|
|
dmas = <&edma 2
|
|
|
|
|
&edma 3>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
interrupts = <28>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
reg = <0x481d8000 0x1000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc3: mmc@47810000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
|
|
|
|
ti,hwmods = "mmc3";
|
|
|
|
|
ti,needs-special-reset;
|
|
|
|
|
interrupts = <29>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
reg = <0x47810000 0x1000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-11 04:15:35 +07:00
|
|
|
hwspinlock: spinlock@480ca000 {
|
|
|
|
|
compatible = "ti,omap4-hwspinlock";
|
|
|
|
|
reg = <0x480ca000 0x1000>;
|
|
|
|
|
ti,hwmods = "spinlock";
|
2014-01-14 07:26:45 +07:00
|
|
|
#hwlock-cells = <1>;
|
2013-10-11 04:15:35 +07:00
|
|
|
};
|
|
|
|
|
|
2012-07-04 19:30:37 +07:00
|
|
|
wdt2: wdt@44e35000 {
|
|
|
|
|
compatible = "ti,omap3-wdt";
|
|
|
|
|
ti,hwmods = "wd_timer2";
|
2012-08-27 18:51:01 +07:00
|
|
|
reg = <0x44e35000 0x1000>;
|
|
|
|
|
interrupts = <91>;
|
2012-07-04 19:30:37 +07:00
|
|
|
};
|
2012-09-20 04:19:27 +07:00
|
|
|
|
2014-09-09 20:15:35 +07:00
|
|
|
dcan0: can@481cc000 {
|
|
|
|
|
compatible = "ti,am3352-d_can";
|
2012-09-20 04:19:27 +07:00
|
|
|
ti,hwmods = "d_can0";
|
2014-09-09 20:15:35 +07:00
|
|
|
reg = <0x481cc000 0x2000>;
|
|
|
|
|
clocks = <&dcan0_fck>;
|
|
|
|
|
clock-names = "fck";
|
2015-03-20 18:08:29 +07:00
|
|
|
syscon-raminit = <&scm_conf 0x644 0>;
|
2012-09-20 04:19:27 +07:00
|
|
|
interrupts = <52>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-09 20:15:35 +07:00
|
|
|
dcan1: can@481d0000 {
|
|
|
|
|
compatible = "ti,am3352-d_can";
|
2012-09-20 04:19:27 +07:00
|
|
|
ti,hwmods = "d_can1";
|
2014-09-09 20:15:35 +07:00
|
|
|
reg = <0x481d0000 0x2000>;
|
|
|
|
|
clocks = <&dcan1_fck>;
|
|
|
|
|
clock-names = "fck";
|
2015-03-20 18:08:29 +07:00
|
|
|
syscon-raminit = <&scm_conf 0x644 1>;
|
2012-09-20 04:19:27 +07:00
|
|
|
interrupts = <55>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-10-19 21:59:00 +07:00
|
|
|
|
2014-07-12 04:44:36 +07:00
|
|
|
mailbox: mailbox@480C8000 {
|
|
|
|
|
compatible = "ti,omap4-mailbox";
|
|
|
|
|
reg = <0x480C8000 0x200>;
|
|
|
|
|
interrupts = <77>;
|
|
|
|
|
ti,hwmods = "mailbox";
|
2014-11-04 06:07:35 +07:00
|
|
|
#mbox-cells = <1>;
|
2014-07-12 04:44:36 +07:00
|
|
|
ti,mbox-num-users = <4>;
|
|
|
|
|
ti,mbox-num-fifos = <8>;
|
2014-09-11 02:27:23 +07:00
|
|
|
mbox_wkupm3: wkup_m3 {
|
|
|
|
|
ti,mbox-tx = <0 0 0>;
|
|
|
|
|
ti,mbox-rx = <0 0 3>;
|
|
|
|
|
};
|
2014-07-12 04:44:36 +07:00
|
|
|
};
|
|
|
|
|
|
2012-10-19 21:59:00 +07:00
|
|
|
timer1: timer@44e31000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer-1ms";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x44e31000 0x400>;
|
|
|
|
|
interrupts = <67>;
|
|
|
|
|
ti,hwmods = "timer1";
|
|
|
|
|
ti,timer-alwon;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer2: timer@48040000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x48040000 0x400>;
|
|
|
|
|
interrupts = <68>;
|
|
|
|
|
ti,hwmods = "timer2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer3: timer@48042000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x48042000 0x400>;
|
|
|
|
|
interrupts = <69>;
|
|
|
|
|
ti,hwmods = "timer3";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer4: timer@48044000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x48044000 0x400>;
|
|
|
|
|
interrupts = <92>;
|
|
|
|
|
ti,hwmods = "timer4";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer5: timer@48046000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x48046000 0x400>;
|
|
|
|
|
interrupts = <93>;
|
|
|
|
|
ti,hwmods = "timer5";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer6: timer@48048000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x48048000 0x400>;
|
|
|
|
|
interrupts = <94>;
|
|
|
|
|
ti,hwmods = "timer6";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer7: timer@4804a000 {
|
2013-03-20 00:38:18 +07:00
|
|
|
compatible = "ti,am335x-timer";
|
2012-10-19 21:59:00 +07:00
|
|
|
reg = <0x4804a000 0x400>;
|
|
|
|
|
interrupts = <95>;
|
|
|
|
|
ti,hwmods = "timer7";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
2012-10-30 16:34:01 +07:00
|
|
|
|
2014-02-05 19:12:39 +07:00
|
|
|
rtc: rtc@44e3e000 {
|
2014-12-11 06:53:25 +07:00
|
|
|
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
2012-10-30 16:34:01 +07:00
|
|
|
reg = <0x44e3e000 0x1000>;
|
|
|
|
|
interrupts = <75
|
|
|
|
|
76>;
|
|
|
|
|
ti,hwmods = "rtc";
|
|
|
|
|
};
|
2012-10-31 17:51:09 +07:00
|
|
|
|
|
|
|
|
spi0: spi@48030000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x48030000 0x400>;
|
2013-02-01 12:37:27 +07:00
|
|
|
interrupts = <65>;
|
2012-10-31 17:51:09 +07:00
|
|
|
ti,spi-num-cs = <2>;
|
|
|
|
|
ti,hwmods = "spi0";
|
2013-09-11 02:24:38 +07:00
|
|
|
dmas = <&edma 16
|
|
|
|
|
&edma 17
|
|
|
|
|
&edma 18
|
|
|
|
|
&edma 19>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
2012-10-31 17:51:09 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1: spi@481a0000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x481a0000 0x400>;
|
2013-02-01 12:37:27 +07:00
|
|
|
interrupts = <125>;
|
2012-10-31 17:51:09 +07:00
|
|
|
ti,spi-num-cs = <2>;
|
|
|
|
|
ti,hwmods = "spi1";
|
2013-09-11 02:24:38 +07:00
|
|
|
dmas = <&edma 42
|
|
|
|
|
&edma 43
|
|
|
|
|
&edma 44
|
|
|
|
|
&edma 45>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
2012-10-31 17:51:09 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-11-06 21:29:38 +07:00
|
|
|
|
2013-07-05 19:51:33 +07:00
|
|
|
usb: usb@47400000 {
|
|
|
|
|
compatible = "ti,am33xx-usb";
|
|
|
|
|
reg = <0x47400000 0x1000>;
|
|
|
|
|
ranges;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2012-11-06 21:29:38 +07:00
|
|
|
ti,hwmods = "usb_otg_hs";
|
2013-07-05 19:51:33 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
|
2014-03-06 19:31:34 +07:00
|
|
|
usb_ctrl_mod: control@44e10620 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,am335x-usb-ctrl-module";
|
|
|
|
|
reg = <0x44e10620 0x10
|
|
|
|
|
0x44e10648 0x4>;
|
|
|
|
|
reg-names = "phy_ctrl", "wakeup";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-08-20 23:35:47 +07:00
|
|
|
usb0_phy: usb-phy@47401300 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,am335x-usb-phy";
|
|
|
|
|
reg = <0x47401300 0x100>;
|
|
|
|
|
reg-names = "phy";
|
|
|
|
|
status = "disabled";
|
2013-10-14 19:49:21 +07:00
|
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0: usb@47401000 {
|
|
|
|
|
compatible = "ti,musb-am33xx";
|
|
|
|
|
status = "disabled";
|
2013-08-20 23:35:47 +07:00
|
|
|
reg = <0x47401400 0x400
|
|
|
|
|
0x47401000 0x200>;
|
|
|
|
|
reg-names = "mc", "control";
|
|
|
|
|
|
|
|
|
|
interrupts = <18>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
mentor,multipoint = <1>;
|
|
|
|
|
mentor,num-eps = <16>;
|
|
|
|
|
mentor,ram-bits = <12>;
|
|
|
|
|
mentor,power = <500>;
|
|
|
|
|
phys = <&usb0_phy>;
|
2013-06-20 17:13:04 +07:00
|
|
|
|
|
|
|
|
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
|
|
|
|
&cppi41dma 2 0 &cppi41dma 3 0
|
|
|
|
|
&cppi41dma 4 0 &cppi41dma 5 0
|
|
|
|
|
&cppi41dma 6 0 &cppi41dma 7 0
|
|
|
|
|
&cppi41dma 8 0 &cppi41dma 9 0
|
|
|
|
|
&cppi41dma 10 0 &cppi41dma 11 0
|
|
|
|
|
&cppi41dma 12 0 &cppi41dma 13 0
|
|
|
|
|
&cppi41dma 14 0 &cppi41dma 0 1
|
|
|
|
|
&cppi41dma 1 1 &cppi41dma 2 1
|
|
|
|
|
&cppi41dma 3 1 &cppi41dma 4 1
|
|
|
|
|
&cppi41dma 5 1 &cppi41dma 6 1
|
|
|
|
|
&cppi41dma 7 1 &cppi41dma 8 1
|
|
|
|
|
&cppi41dma 9 1 &cppi41dma 10 1
|
|
|
|
|
&cppi41dma 11 1 &cppi41dma 12 1
|
|
|
|
|
&cppi41dma 13 1 &cppi41dma 14 1>;
|
|
|
|
|
dma-names =
|
|
|
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
|
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
|
|
|
"rx14", "rx15",
|
|
|
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
|
|
|
"tx14", "tx15";
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
|
|
|
|
|
2013-08-20 23:35:47 +07:00
|
|
|
usb1_phy: usb-phy@47401b00 {
|
2013-07-05 19:51:33 +07:00
|
|
|
compatible = "ti,am335x-usb-phy";
|
|
|
|
|
reg = <0x47401b00 0x100>;
|
|
|
|
|
reg-names = "phy";
|
|
|
|
|
status = "disabled";
|
2013-10-14 19:49:21 +07:00
|
|
|
ti,ctrl_mod = <&usb_ctrl_mod>;
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1: usb@47401800 {
|
|
|
|
|
compatible = "ti,musb-am33xx";
|
|
|
|
|
status = "disabled";
|
2013-08-20 23:35:47 +07:00
|
|
|
reg = <0x47401c00 0x400
|
|
|
|
|
0x47401800 0x200>;
|
|
|
|
|
reg-names = "mc", "control";
|
|
|
|
|
interrupts = <19>;
|
|
|
|
|
interrupt-names = "mc";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
mentor,multipoint = <1>;
|
|
|
|
|
mentor,num-eps = <16>;
|
|
|
|
|
mentor,ram-bits = <12>;
|
|
|
|
|
mentor,power = <500>;
|
|
|
|
|
phys = <&usb1_phy>;
|
2013-06-20 17:13:04 +07:00
|
|
|
|
|
|
|
|
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
|
|
|
|
&cppi41dma 17 0 &cppi41dma 18 0
|
|
|
|
|
&cppi41dma 19 0 &cppi41dma 20 0
|
|
|
|
|
&cppi41dma 21 0 &cppi41dma 22 0
|
|
|
|
|
&cppi41dma 23 0 &cppi41dma 24 0
|
|
|
|
|
&cppi41dma 25 0 &cppi41dma 26 0
|
|
|
|
|
&cppi41dma 27 0 &cppi41dma 28 0
|
|
|
|
|
&cppi41dma 29 0 &cppi41dma 15 1
|
|
|
|
|
&cppi41dma 16 1 &cppi41dma 17 1
|
|
|
|
|
&cppi41dma 18 1 &cppi41dma 19 1
|
|
|
|
|
&cppi41dma 20 1 &cppi41dma 21 1
|
|
|
|
|
&cppi41dma 22 1 &cppi41dma 23 1
|
|
|
|
|
&cppi41dma 24 1 &cppi41dma 25 1
|
|
|
|
|
&cppi41dma 26 1 &cppi41dma 27 1
|
|
|
|
|
&cppi41dma 28 1 &cppi41dma 29 1>;
|
|
|
|
|
dma-names =
|
|
|
|
|
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
|
|
|
|
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
|
|
|
|
"rx14", "rx15",
|
|
|
|
|
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
|
|
|
|
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
|
|
|
|
"tx14", "tx15";
|
2013-07-05 19:51:33 +07:00
|
|
|
};
|
2013-06-20 17:13:04 +07:00
|
|
|
|
2014-03-06 19:31:34 +07:00
|
|
|
cppi41dma: dma-controller@47402000 {
|
2013-06-20 17:13:04 +07:00
|
|
|
compatible = "ti,am3359-cppi41";
|
|
|
|
|
reg = <0x47400000 0x1000
|
|
|
|
|
0x47402000 0x1000
|
|
|
|
|
0x47403000 0x1000
|
|
|
|
|
0x47404000 0x4000>;
|
2013-08-20 23:35:45 +07:00
|
|
|
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
2013-06-20 17:13:04 +07:00
|
|
|
interrupts = <17>;
|
|
|
|
|
interrupt-names = "glue";
|
|
|
|
|
#dma-cells = <2>;
|
|
|
|
|
#dma-channels = <30>;
|
|
|
|
|
#dma-requests = <256>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-11-06 21:29:38 +07:00
|
|
|
};
|
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking changes from David Miller:
1) Allow to dump, monitor, and change the bridge multicast database
using netlink. From Cong Wang.
2) RFC 5961 TCP blind data injection attack mitigation, from Eric
Dumazet.
3) Networking user namespace support from Eric W. Biederman.
4) tuntap/virtio-net multiqueue support by Jason Wang.
5) Support for checksum offload of encapsulated packets (basically,
tunneled traffic can still be checksummed by HW). From Joseph
Gasparakis.
6) Allow BPF filter access to VLAN tags, from Eric Dumazet and
Daniel Borkmann.
7) Bridge port parameters over netlink and BPDU blocking support
from Stephen Hemminger.
8) Improve data access patterns during inet socket demux by rearranging
socket layout, from Eric Dumazet.
9) TIPC protocol updates and cleanups from Ying Xue, Paul Gortmaker, and
Jon Maloy.
10) Update TCP socket hash sizing to be more in line with current day
realities. The existing heurstics were choosen a decade ago.
From Eric Dumazet.
11) Fix races, queue bloat, and excessive wakeups in ATM and
associated drivers, from Krzysztof Mazur and David Woodhouse.
12) Support DOVE (Distributed Overlay Virtual Ethernet) extensions
in VXLAN driver, from David Stevens.
13) Add "oops_only" mode to netconsole, from Amerigo Wang.
14) Support set and query of VEB/VEPA bridge mode via PF_BRIDGE, also
allow DCB netlink to work on namespaces other than the initial
namespace. From John Fastabend.
15) Support PTP in the Tigon3 driver, from Matt Carlson.
16) tun/vhost zero copy fixes and improvements, plus turn it on
by default, from Michael S. Tsirkin.
17) Support per-association statistics in SCTP, from Michele
Baldessari.
And many, many, driver updates, cleanups, and improvements. Too
numerous to mention individually.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1722 commits)
net/mlx4_en: Add support for destination MAC in steering rules
net/mlx4_en: Use generic etherdevice.h functions.
net: ethtool: Add destination MAC address to flow steering API
bridge: add support of adding and deleting mdb entries
bridge: notify mdb changes via netlink
ndisc: Unexport ndisc_{build,send}_skb().
uapi: add missing netconf.h to export list
pkt_sched: avoid requeues if possible
solos-pci: fix double-free of TX skb in DMA mode
bnx2: Fix accidental reversions.
bna: Driver Version Updated to 3.1.2.1
bna: Firmware update
bna: Add RX State
bna: Rx Page Based Allocation
bna: TX Intr Coalescing Fix
bna: Tx and Rx Optimizations
bna: Code Cleanup and Enhancements
ath9k: check pdata variable before dereferencing it
ath5k: RX timestamp is reported at end of frame
ath9k_htc: RX timestamp is reported at end of frame
...
2012-12-13 09:07:07 +07:00
|
|
|
|
2013-06-06 20:52:37 +07:00
|
|
|
epwmss0: epwmss@48300000 {
|
|
|
|
|
compatible = "ti,am33xx-pwmss";
|
|
|
|
|
reg = <0x48300000 0x10>;
|
|
|
|
|
ti,hwmods = "epwmss0";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
|
|
|
|
|
0x48300180 0x48300180 0x80 /* EQEP */
|
|
|
|
|
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
|
|
|
|
|
|
|
|
|
ecap0: ecap@48300100 {
|
|
|
|
|
compatible = "ti,am33xx-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x48300100 0x80>;
|
2014-01-30 03:59:59 +07:00
|
|
|
interrupts = <31>;
|
|
|
|
|
interrupt-names = "ecap0";
|
2013-06-06 20:52:37 +07:00
|
|
|
ti,hwmods = "ecap0";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehrpwm0: ehrpwm@48300200 {
|
|
|
|
|
compatible = "ti,am33xx-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x48300200 0x80>;
|
|
|
|
|
ti,hwmods = "ehrpwm0";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwmss1: epwmss@48302000 {
|
|
|
|
|
compatible = "ti,am33xx-pwmss";
|
|
|
|
|
reg = <0x48302000 0x10>;
|
|
|
|
|
ti,hwmods = "epwmss1";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
|
|
|
|
|
0x48302180 0x48302180 0x80 /* EQEP */
|
|
|
|
|
0x48302200 0x48302200 0x80>; /* EHRPWM */
|
|
|
|
|
|
|
|
|
|
ecap1: ecap@48302100 {
|
|
|
|
|
compatible = "ti,am33xx-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x48302100 0x80>;
|
2014-01-30 03:59:59 +07:00
|
|
|
interrupts = <47>;
|
|
|
|
|
interrupt-names = "ecap1";
|
2013-06-06 20:52:37 +07:00
|
|
|
ti,hwmods = "ecap1";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehrpwm1: ehrpwm@48302200 {
|
|
|
|
|
compatible = "ti,am33xx-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x48302200 0x80>;
|
|
|
|
|
ti,hwmods = "ehrpwm1";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
epwmss2: epwmss@48304000 {
|
|
|
|
|
compatible = "ti,am33xx-pwmss";
|
|
|
|
|
reg = <0x48304000 0x10>;
|
|
|
|
|
ti,hwmods = "epwmss2";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
ranges = <0x48304100 0x48304100 0x80 /* ECAP */
|
|
|
|
|
0x48304180 0x48304180 0x80 /* EQEP */
|
|
|
|
|
0x48304200 0x48304200 0x80>; /* EHRPWM */
|
|
|
|
|
|
|
|
|
|
ecap2: ecap@48304100 {
|
|
|
|
|
compatible = "ti,am33xx-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x48304100 0x80>;
|
2014-01-30 03:59:59 +07:00
|
|
|
interrupts = <61>;
|
|
|
|
|
interrupt-names = "ecap2";
|
2013-06-06 20:52:37 +07:00
|
|
|
ti,hwmods = "ecap2";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ehrpwm2: ehrpwm@48304200 {
|
|
|
|
|
compatible = "ti,am33xx-ehrpwm";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x48304200 0x80>;
|
|
|
|
|
ti,hwmods = "ehrpwm2";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-14 16:08:00 +07:00
|
|
|
mac: ethernet@4a100000 {
|
|
|
|
|
compatible = "ti,cpsw";
|
|
|
|
|
ti,hwmods = "cpgmac0";
|
2014-05-02 13:31:59 +07:00
|
|
|
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
|
|
|
|
|
clock-names = "fck", "cpts";
|
2012-11-14 16:08:00 +07:00
|
|
|
cpdma_channels = <8>;
|
|
|
|
|
ale_entries = <1024>;
|
|
|
|
|
bd_ram_size = <0x2000>;
|
|
|
|
|
no_bd_ram = <0>;
|
|
|
|
|
rx_descs = <64>;
|
|
|
|
|
mac_control = <0x20>;
|
|
|
|
|
slaves = <2>;
|
2013-03-12 06:16:35 +07:00
|
|
|
active_slave = <0>;
|
2012-11-14 16:08:00 +07:00
|
|
|
cpts_clock_mult = <0x80000000>;
|
|
|
|
|
cpts_clock_shift = <29>;
|
|
|
|
|
reg = <0x4a100000 0x800
|
|
|
|
|
0x4a101200 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
/*
|
|
|
|
|
* c0_rx_thresh_pend
|
|
|
|
|
* c0_rx_pend
|
|
|
|
|
* c0_tx_pend
|
|
|
|
|
* c0_misc_pend
|
|
|
|
|
*/
|
|
|
|
|
interrupts = <40 41 42 43>;
|
|
|
|
|
ranges;
|
2015-03-20 18:08:29 +07:00
|
|
|
syscon = <&scm_conf>;
|
2014-05-08 15:57:36 +07:00
|
|
|
status = "disabled";
|
2012-11-14 16:08:00 +07:00
|
|
|
|
|
|
|
|
davinci_mdio: mdio@4a101000 {
|
|
|
|
|
compatible = "ti,davinci_mdio";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "davinci_mdio";
|
|
|
|
|
bus_freq = <1000000>;
|
|
|
|
|
reg = <0x4a101000 0x100>;
|
2014-05-08 15:57:36 +07:00
|
|
|
status = "disabled";
|
2012-11-14 16:08:00 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpsw_emac0: slave@4a100200 {
|
|
|
|
|
/* Filled in by U-Boot */
|
|
|
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpsw_emac1: slave@4a100300 {
|
|
|
|
|
/* Filled in by U-Boot */
|
|
|
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
|
|
|
};
|
2013-09-21 02:20:41 +07:00
|
|
|
|
|
|
|
|
phy_sel: cpsw-phy-sel@44e10650 {
|
|
|
|
|
compatible = "ti,am3352-cpsw-phy-sel";
|
|
|
|
|
reg= <0x44e10650 0x4>;
|
|
|
|
|
reg-names = "gmii-sel";
|
|
|
|
|
};
|
2012-11-14 16:08:00 +07:00
|
|
|
};
|
2013-01-29 18:15:07 +07:00
|
|
|
|
|
|
|
|
ocmcram: ocmcram@40300000 {
|
2014-09-10 23:04:03 +07:00
|
|
|
compatible = "mmio-sram";
|
|
|
|
|
reg = <0x40300000 0x10000>; /* 64k */
|
2013-01-29 18:15:07 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wkup_m3: wkup_m3@44d00000 {
|
|
|
|
|
compatible = "ti,am3353-wkup-m3";
|
|
|
|
|
reg = <0x44d00000 0x4000 /* M3 UMEM */
|
|
|
|
|
0x44d80000 0x2000>; /* M3 DMEM */
|
|
|
|
|
ti,hwmods = "wkup_m3";
|
2013-10-15 14:07:50 +07:00
|
|
|
ti,no-reset-on-init;
|
2013-01-29 18:15:07 +07:00
|
|
|
};
|
2013-05-02 16:44:03 +07:00
|
|
|
|
2013-05-31 14:49:03 +07:00
|
|
|
elm: elm@48080000 {
|
|
|
|
|
compatible = "ti,am3352-elm";
|
|
|
|
|
reg = <0x48080000 0x2000>;
|
|
|
|
|
interrupts = <4>;
|
|
|
|
|
ti,hwmods = "elm";
|
2013-08-09 06:28:14 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lcdc: lcdc@4830e000 {
|
|
|
|
|
compatible = "ti,am33xx-tilcdc";
|
|
|
|
|
reg = <0x4830e000 0x1000>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
interrupts = <36>;
|
|
|
|
|
ti,hwmods = "lcdc";
|
2013-05-31 14:49:03 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-24 10:45:12 +07:00
|
|
|
tscadc: tscadc@44e0d000 {
|
|
|
|
|
compatible = "ti,am3359-tscadc";
|
|
|
|
|
reg = <0x44e0d000 0x1000>;
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
|
interrupts = <16>;
|
|
|
|
|
ti,hwmods = "adc_tsc";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
tsc {
|
|
|
|
|
compatible = "ti,am3359-tsc";
|
|
|
|
|
};
|
|
|
|
|
am335x_adc: adc {
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
compatible = "ti,am3359-adc";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-05-02 16:44:03 +07:00
|
|
|
gpmc: gpmc@50000000 {
|
|
|
|
|
compatible = "ti,am3352-gpmc";
|
|
|
|
|
ti,hwmods = "gpmc";
|
2013-10-15 14:07:50 +07:00
|
|
|
ti,no-idle-on-init;
|
2013-05-02 16:44:03 +07:00
|
|
|
reg = <0x50000000 0x2000>;
|
|
|
|
|
interrupts = <100>;
|
2013-05-28 15:24:57 +07:00
|
|
|
gpmc,num-cs = <7>;
|
|
|
|
|
gpmc,num-waitpins = <2>;
|
2013-05-02 16:44:03 +07:00
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-08-24 04:12:35 +07:00
|
|
|
|
|
|
|
|
sham: sham@53100000 {
|
|
|
|
|
compatible = "ti,omap4-sham";
|
|
|
|
|
ti,hwmods = "sham";
|
|
|
|
|
reg = <0x53100000 0x200>;
|
|
|
|
|
interrupts = <109>;
|
|
|
|
|
dmas = <&edma 36>;
|
|
|
|
|
dma-names = "rx";
|
|
|
|
|
};
|
2013-08-24 04:12:36 +07:00
|
|
|
|
|
|
|
|
aes: aes@53500000 {
|
|
|
|
|
compatible = "ti,omap4-aes";
|
|
|
|
|
ti,hwmods = "aes";
|
|
|
|
|
reg = <0x53500000 0xa0>;
|
2013-07-18 07:07:52 +07:00
|
|
|
interrupts = <103>;
|
2013-08-24 04:12:36 +07:00
|
|
|
dmas = <&edma 6>,
|
|
|
|
|
<&edma 5>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
2013-10-21 00:04:08 +07:00
|
|
|
|
|
|
|
|
mcasp0: mcasp@48038000 {
|
|
|
|
|
compatible = "ti,am33xx-mcasp-audio";
|
|
|
|
|
ti,hwmods = "mcasp0";
|
2013-10-21 00:04:09 +07:00
|
|
|
reg = <0x48038000 0x2000>,
|
|
|
|
|
<0x46000000 0x400000>;
|
|
|
|
|
reg-names = "mpu", "dat";
|
2013-10-21 00:04:08 +07:00
|
|
|
interrupts = <80>, <81>;
|
2014-04-23 01:40:25 +07:00
|
|
|
interrupt-names = "tx", "rx";
|
2013-10-21 00:04:08 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
dmas = <&edma 8>,
|
|
|
|
|
<&edma 9>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcasp1: mcasp@4803C000 {
|
|
|
|
|
compatible = "ti,am33xx-mcasp-audio";
|
|
|
|
|
ti,hwmods = "mcasp1";
|
2013-10-21 00:04:09 +07:00
|
|
|
reg = <0x4803C000 0x2000>,
|
|
|
|
|
<0x46400000 0x400000>;
|
|
|
|
|
reg-names = "mpu", "dat";
|
2013-10-21 00:04:08 +07:00
|
|
|
interrupts = <82>, <83>;
|
2014-04-23 01:40:25 +07:00
|
|
|
interrupt-names = "tx", "rx";
|
2013-10-21 00:04:08 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
dmas = <&edma 10>,
|
|
|
|
|
<&edma 11>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
2013-08-29 19:52:09 +07:00
|
|
|
|
|
|
|
|
rng: rng@48310000 {
|
|
|
|
|
compatible = "ti,omap4-rng";
|
|
|
|
|
ti,hwmods = "rng";
|
|
|
|
|
reg = <0x48310000 0x2000>;
|
|
|
|
|
interrupts = <111>;
|
|
|
|
|
};
|
2012-06-22 16:40:48 +07:00
|
|
|
};
|
|
|
|
|
};
|
2013-07-18 22:15:35 +07:00
|
|
|
|
|
|
|
|
/include/ "am33xx-clocks.dtsi"
|