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linux_dsm_epyc7002/arch/arm/mach-vexpress/Makefile

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ARM: Add Versatile Express support Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-12 04:44:53 +07:00
#
# Makefile for the linux kernel.
#
ARM: vexpress: Remove non-DT code Now, with the CLCD DT support available, there is no more reason to keep the non-DT support for V2P-CA9. Removed, together with "some" supporting code. It was necessary to make PLAT_VERSATILE_SCHED_CLOCK optional and selected by the machines still interested in it. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-26 01:17:34 +07:00
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \
ARM: vexpress: convert to multi-platform Convert vexpress to multi-platform. This always enables vexpress DT and makes it the default v7 platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com>
2012-09-07 01:43:04 +07:00
-I$(srctree)/arch/arm/plat-versatile/include
ARM: Add Versatile Express support Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-12 04:44:53 +07:00
ARM: vexpress/mps2: introduce MPS2 platform The Cortex-M Prototyping System (or V2M-MPS2) is designed for prototyping and evaluation Cortex-M family of processors including the latest Cortex-M7 It comes with a range of useful peripherals including 8MB single cycle SRAM, 16MB PSRAM, Ethernet, QSVGA touch screen panel, 4bit RGB VGA connector, Audio, SPI and GPIO. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-04-25 15:49:13 +07:00
obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o
ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Add the required code to properly handle race free platform coherency exit to the DCSCB power down method. The power_up_setup callback is used to enable the CCI interface for the cluster being brought up. This must be done in assembly before the kernel environment is entered. Thanks to Achin Gupta and Nicolas Pitre for their help and contributions. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
2012-07-17 20:25:44 +07:00
obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
ARM: vexpress: allow dcscb and tc2_pm in a combined ARMv6+v7 build This fixes the following build error: /tmp/cce439dZ.s: Assembler messages: /tmp/cce439dZ.s:506: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:512: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:513: Error: selected processor does not support ARM mode `dsb ' /tmp/cce439dZ.s:583: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:589: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:590: Error: selected processor does not support ARM mode `dsb ' Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-09-09 23:31:04 +07:00
CFLAGS_dcscb.o += -march=armv7-a
ARM: 7962/2: Make all mcpm functions notrace The functions in mcpm_entry.c are mostly intended for use during scary cache and coherency disabling sequences, or do other things which confuse trace ... like powering a CPU down and not returning. Similarly for the backend code. For simplicity, this patch just makes whole files notrace. There should be more than enough traceable points on the paths to these functions, but we can be more fine-grained later if there is a need for it. Jon Medhurst: Also added spc.o to the list of files as it contains functions used by MCPM code which have comments comments like: "might be used in code paths where normal cacheable locks are not working" Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-02-14 18:46:02 +07:00
CFLAGS_REMOVE_dcscb.o = -pg
ARM: vexpress/TC2: add support for CPU DVFS SPC(Serial Power Controller) on TC2 also controls the CPU performance operating points which is essential to provide CPU DVFS. The M3 microcontroller provides two sets of eight performance values, one set for each cluster (CA15 or CA7). Each of this value contains the frequency(kHz) and voltage(mV) at that performance level. It expects these performance level to be passed through the SPC PERF_LVL registers. This patch adds support to populate these performance levels from M3, build the mapping to CPU OPPs at the boot and then use it to get and set the CPU performance level runtime. Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Pawel Moll <Pawel.Moll@arm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-29 19:18:37 +07:00
obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o
ARM: 7962/2: Make all mcpm functions notrace The functions in mcpm_entry.c are mostly intended for use during scary cache and coherency disabling sequences, or do other things which confuse trace ... like powering a CPU down and not returning. Similarly for the backend code. For simplicity, this patch just makes whole files notrace. There should be more than enough traceable points on the paths to these functions, but we can be more fine-grained later if there is a need for it. Jon Medhurst: Also added spc.o to the list of files as it contains functions used by MCPM code which have comments comments like: "might be used in code paths where normal cacheable locks are not working" Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-02-14 18:46:02 +07:00
CFLAGS_REMOVE_spc.o = -pg
ARM: vexpress/TC2: add support for CPU DVFS SPC(Serial Power Controller) on TC2 also controls the CPU performance operating points which is essential to provide CPU DVFS. The M3 microcontroller provides two sets of eight performance values, one set for each cluster (CA15 or CA7). Each of this value contains the frequency(kHz) and voltage(mV) at that performance level. It expects these performance level to be passed through the SPC PERF_LVL registers. This patch adds support to populate these performance levels from M3, build the mapping to CPU OPPs at the boot and then use it to get and set the CPU performance level runtime. Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Pawel Moll <Pawel.Moll@arm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-29 19:18:37 +07:00
obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o
ARM: vexpress: allow dcscb and tc2_pm in a combined ARMv6+v7 build This fixes the following build error: /tmp/cce439dZ.s: Assembler messages: /tmp/cce439dZ.s:506: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:512: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:513: Error: selected processor does not support ARM mode `dsb ' /tmp/cce439dZ.s:583: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:589: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:590: Error: selected processor does not support ARM mode `dsb ' Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-09-09 23:31:04 +07:00
CFLAGS_tc2_pm.o += -march=armv7-a
ARM: 7962/2: Make all mcpm functions notrace The functions in mcpm_entry.c are mostly intended for use during scary cache and coherency disabling sequences, or do other things which confuse trace ... like powering a CPU down and not returning. Similarly for the backend code. For simplicity, this patch just makes whole files notrace. There should be more than enough traceable points on the paths to these functions, but we can be more fine-grained later if there is a need for it. Jon Medhurst: Also added spc.o to the list of files as it contains functions used by MCPM code which have comments comments like: "might be used in code paths where normal cacheable locks are not working" Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-02-14 18:46:02 +07:00
CFLAGS_REMOVE_tc2_pm.o = -pg
ARM: realview/vexpress: consolidate SMP bringup code Realview and Versatile Express share the same SMP bringup code, so consolidate the two implementations. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-01-19 17:24:56 +07:00
obj-$(CONFIG_SMP) += platsmp.o
ARM: CPU hotplug: add Versatile Express hotplug CPU support Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-19 18:33:12 +07:00
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
ARM: vexpress/mps2: introduce MPS2 platform The Cortex-M Prototyping System (or V2M-MPS2) is designed for prototyping and evaluation Cortex-M family of processors including the latest Cortex-M7 It comes with a range of useful peripherals including 8MB single cycle SRAM, 16MB PSRAM, Ethernet, QSVGA touch screen panel, 4bit RGB VGA connector, Audio, SPI and GPIO. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-04-25 15:49:13 +07:00
obj-$(CONFIG_ARCH_MPS2) += v2m-mps2.o
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