2009-04-23 02:08:17 +07:00
|
|
|
/*
|
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __ASM_ARCH_BRIDGE_REGS_H
|
|
|
|
#define __ASM_ARCH_BRIDGE_REGS_H
|
|
|
|
|
2015-12-03 04:27:06 +07:00
|
|
|
#include "mv78xx0.h"
|
2009-04-23 02:08:17 +07:00
|
|
|
|
2012-09-11 19:27:16 +07:00
|
|
|
#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
|
2009-04-23 02:08:17 +07:00
|
|
|
#define L2_WRITETHROUGH 0x00020000
|
|
|
|
|
2012-09-11 19:27:16 +07:00
|
|
|
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
|
2014-02-11 06:00:25 +07:00
|
|
|
#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
|
2009-04-23 02:08:17 +07:00
|
|
|
#define SOFT_RESET_OUT_EN 0x00000004
|
|
|
|
|
2012-09-11 19:27:16 +07:00
|
|
|
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
|
2009-04-23 02:08:17 +07:00
|
|
|
#define SOFT_RESET 0x00000001
|
|
|
|
|
|
|
|
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
|
|
|
|
2012-09-11 19:27:16 +07:00
|
|
|
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
|
2009-04-23 02:08:17 +07:00
|
|
|
#define IRQ_CAUSE_ERR_OFF 0x0000
|
|
|
|
#define IRQ_CAUSE_LOW_OFF 0x0004
|
|
|
|
#define IRQ_CAUSE_HIGH_OFF 0x0008
|
|
|
|
#define IRQ_MASK_ERR_OFF 0x000c
|
|
|
|
#define IRQ_MASK_LOW_OFF 0x0010
|
|
|
|
#define IRQ_MASK_HIGH_OFF 0x0014
|
|
|
|
|
2012-09-11 19:27:16 +07:00
|
|
|
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
|
|
|
|
#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
|
2009-04-23 02:08:17 +07:00
|
|
|
|
|
|
|
#endif
|