2019-05-27 13:55:21 +07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-05-06 14:23:41 +07:00
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/*
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* Copyright (c) 2014-2015 MediaTek Inc.
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* Author: Tianping.Fang <tianping.fang@mediatek.com>
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*/
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2019-09-10 14:04:42 +07:00
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/mt6397/core.h>
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2015-05-06 14:23:41 +07:00
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#include <linux/module.h>
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2019-09-10 14:04:42 +07:00
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#include <linux/mutex.h>
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2020-04-21 10:00:11 +07:00
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#include <linux/of_device.h>
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2019-09-10 14:04:42 +07:00
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#include <linux/platform_device.h>
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2015-05-06 14:23:41 +07:00
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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2019-09-10 14:04:41 +07:00
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#include <linux/mfd/mt6397/rtc.h>
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2019-09-10 14:04:42 +07:00
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#include <linux/mod_devicetable.h>
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2015-05-06 14:23:41 +07:00
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static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
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{
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int ret;
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u32 data;
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2020-04-21 10:00:11 +07:00
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ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1);
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2015-05-06 14:23:41 +07:00
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if (ret < 0)
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return ret;
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2019-09-10 14:04:42 +07:00
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ret = regmap_read_poll_timeout(rtc->regmap,
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rtc->addr_base + RTC_BBPU, data,
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!(data & RTC_BBPU_CBUSY),
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MTK_RTC_POLL_DELAY_US,
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MTK_RTC_POLL_TIMEOUT);
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if (ret < 0)
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dev_err(rtc->dev, "failed to write WRTGE: %d\n", ret);
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2015-05-06 14:23:41 +07:00
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return ret;
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}
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static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
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{
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struct mt6397_rtc *rtc = data;
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u32 irqsta, irqen;
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int ret;
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ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
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if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
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rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
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irqen = irqsta & ~RTC_IRQ_EN_AL;
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mutex_lock(&rtc->lock);
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if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
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2019-12-11 16:43:54 +07:00
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irqen) == 0)
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2015-05-06 14:23:41 +07:00
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mtk_rtc_write_trigger(rtc);
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mutex_unlock(&rtc->lock);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
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struct rtc_time *tm, int *sec)
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{
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int ret;
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u16 data[RTC_OFFSET_COUNT];
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mutex_lock(&rtc->lock);
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ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
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data, RTC_OFFSET_COUNT);
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if (ret < 0)
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goto exit;
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tm->tm_sec = data[RTC_OFFSET_SEC];
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tm->tm_min = data[RTC_OFFSET_MIN];
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tm->tm_hour = data[RTC_OFFSET_HOUR];
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tm->tm_mday = data[RTC_OFFSET_DOM];
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tm->tm_mon = data[RTC_OFFSET_MTH];
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tm->tm_year = data[RTC_OFFSET_YEAR];
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ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
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exit:
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mutex_unlock(&rtc->lock);
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return ret;
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}
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static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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time64_t time;
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struct mt6397_rtc *rtc = dev_get_drvdata(dev);
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2015-05-15 03:39:06 +07:00
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int days, sec, ret;
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2015-05-06 14:23:41 +07:00
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do {
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ret = __mtk_rtc_read_time(rtc, tm, &sec);
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if (ret < 0)
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goto exit;
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} while (sec < tm->tm_sec);
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/* HW register use 7 bits to store year data, minus
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* RTC_MIN_YEAR_OFFSET before write year data to register, and plus
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* RTC_MIN_YEAR_OFFSET back after read year from register
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*/
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tm->tm_year += RTC_MIN_YEAR_OFFSET;
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/* HW register start mon from one, but tm_mon start from zero. */
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tm->tm_mon--;
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time = rtc_tm_to_time64(tm);
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/* rtc_tm_to_time64 covert Gregorian date to seconds since
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* 01-01-1970 00:00:00, and this date is Thursday.
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*/
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2015-05-15 03:39:06 +07:00
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days = div_s64(time, 86400);
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tm->tm_wday = (days + 4) % 7;
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2015-05-06 14:23:41 +07:00
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exit:
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return ret;
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}
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static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct mt6397_rtc *rtc = dev_get_drvdata(dev);
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int ret;
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u16 data[RTC_OFFSET_COUNT];
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tm->tm_year -= RTC_MIN_YEAR_OFFSET;
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tm->tm_mon++;
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data[RTC_OFFSET_SEC] = tm->tm_sec;
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data[RTC_OFFSET_MIN] = tm->tm_min;
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data[RTC_OFFSET_HOUR] = tm->tm_hour;
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data[RTC_OFFSET_DOM] = tm->tm_mday;
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data[RTC_OFFSET_MTH] = tm->tm_mon;
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data[RTC_OFFSET_YEAR] = tm->tm_year;
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mutex_lock(&rtc->lock);
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ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
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data, RTC_OFFSET_COUNT);
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if (ret < 0)
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goto exit;
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/* Time register write to hardware after call trigger function */
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ret = mtk_rtc_write_trigger(rtc);
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exit:
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mutex_unlock(&rtc->lock);
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return ret;
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}
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static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct rtc_time *tm = &alm->time;
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struct mt6397_rtc *rtc = dev_get_drvdata(dev);
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u32 irqen, pdn2;
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int ret;
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u16 data[RTC_OFFSET_COUNT];
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mutex_lock(&rtc->lock);
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ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
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if (ret < 0)
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goto err_exit;
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ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
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if (ret < 0)
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goto err_exit;
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ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
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data, RTC_OFFSET_COUNT);
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if (ret < 0)
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goto err_exit;
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alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
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alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
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mutex_unlock(&rtc->lock);
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2019-12-11 16:43:54 +07:00
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tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
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tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
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tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
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tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
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tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
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tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
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2015-05-06 14:23:41 +07:00
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tm->tm_year += RTC_MIN_YEAR_OFFSET;
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tm->tm_mon--;
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return 0;
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err_exit:
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mutex_unlock(&rtc->lock);
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return ret;
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}
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static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct rtc_time *tm = &alm->time;
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struct mt6397_rtc *rtc = dev_get_drvdata(dev);
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int ret;
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u16 data[RTC_OFFSET_COUNT];
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tm->tm_year -= RTC_MIN_YEAR_OFFSET;
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tm->tm_mon++;
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mutex_lock(&rtc->lock);
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2019-12-11 16:43:54 +07:00
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ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
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data, RTC_OFFSET_COUNT);
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if (ret < 0)
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goto exit;
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data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
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(tm->tm_sec & RTC_AL_SEC_MASK));
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data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
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(tm->tm_min & RTC_AL_MIN_MASK));
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data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
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(tm->tm_hour & RTC_AL_HOU_MASK));
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data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
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(tm->tm_mday & RTC_AL_DOM_MASK));
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data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
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(tm->tm_mon & RTC_AL_MTH_MASK));
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data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
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(tm->tm_year & RTC_AL_YEA_MASK));
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2015-05-06 14:23:41 +07:00
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if (alm->enabled) {
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ret = regmap_bulk_write(rtc->regmap,
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rtc->addr_base + RTC_AL_SEC,
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data, RTC_OFFSET_COUNT);
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if (ret < 0)
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goto exit;
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ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
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RTC_AL_MASK_DOW);
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if (ret < 0)
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goto exit;
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ret = regmap_update_bits(rtc->regmap,
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rtc->addr_base + RTC_IRQ_EN,
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RTC_IRQ_EN_ONESHOT_AL,
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RTC_IRQ_EN_ONESHOT_AL);
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if (ret < 0)
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goto exit;
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} else {
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ret = regmap_update_bits(rtc->regmap,
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rtc->addr_base + RTC_IRQ_EN,
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RTC_IRQ_EN_ONESHOT_AL, 0);
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if (ret < 0)
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goto exit;
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}
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/* All alarm time register write to hardware after calling
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* mtk_rtc_write_trigger. This can avoid race condition if alarm
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* occur happen during writing alarm time register.
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*/
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ret = mtk_rtc_write_trigger(rtc);
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exit:
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mutex_unlock(&rtc->lock);
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return ret;
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}
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rtc: constify rtc_class_ops structures
Check for rtc_class_ops structures that are only passed to
devm_rtc_device_register, rtc_device_register,
platform_device_register_data, all of which declare the corresponding
parameter as const. Declare rtc_class_ops structures that have these
properties as const.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct rtc_class_ops i@p = { ... };
@ok@
identifier r.i;
expression e1,e2,e3,e4;
position p;
@@
(
devm_rtc_device_register(e1,e2,&i@p,e3)
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rtc_device_register(e1,e2,&i@p,e3)
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platform_device_register_data(e1,e2,e3,&i@p,e4)
)
@bad@
position p != {r.p,ok.p};
identifier r.i;
@@
i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct rtc_class_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-08-31 15:05:25 +07:00
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static const struct rtc_class_ops mtk_rtc_ops = {
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2015-05-06 14:23:41 +07:00
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.read_time = mtk_rtc_read_time,
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.set_time = mtk_rtc_set_time,
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.read_alarm = mtk_rtc_read_alarm,
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.set_alarm = mtk_rtc_set_alarm,
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};
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static int mtk_rtc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
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struct mt6397_rtc *rtc;
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int ret;
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rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rtc->addr_base = res->start;
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2020-04-21 10:00:11 +07:00
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rtc->data = of_device_get_match_data(&pdev->dev);
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2017-10-25 20:15:59 +07:00
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rtc->irq = platform_get_irq(pdev, 0);
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if (rtc->irq < 0)
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return rtc->irq;
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2015-05-06 14:23:41 +07:00
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rtc->regmap = mt6397_chip->regmap;
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mutex_init(&rtc->lock);
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platform_set_drvdata(pdev, rtc);
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2019-09-10 14:04:42 +07:00
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rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
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2018-09-10 03:38:46 +07:00
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if (IS_ERR(rtc->rtc_dev))
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return PTR_ERR(rtc->rtc_dev);
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2019-09-10 14:04:42 +07:00
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ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
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mtk_rtc_irq_handler_thread,
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IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
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"mt6397-rtc", rtc);
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2015-05-06 14:23:41 +07:00
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if (ret) {
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dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
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rtc->irq, ret);
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2019-03-11 14:55:40 +07:00
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return ret;
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2015-05-06 14:23:41 +07:00
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}
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2015-07-02 15:36:56 +07:00
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device_init_wakeup(&pdev->dev, 1);
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2018-09-10 03:38:46 +07:00
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rtc->rtc_dev->ops = &mtk_rtc_ops;
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2019-11-13 09:17:20 +07:00
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return rtc_register_device(rtc->rtc_dev);
|
2015-05-06 14:23:41 +07:00
|
|
|
}
|
|
|
|
|
2015-07-30 21:53:14 +07:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int mt6397_rtc_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct mt6397_rtc *rtc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (device_may_wakeup(dev))
|
|
|
|
enable_irq_wake(rtc->irq);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mt6397_rtc_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct mt6397_rtc *rtc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (device_may_wakeup(dev))
|
|
|
|
disable_irq_wake(rtc->irq);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
|
|
|
|
mt6397_rtc_resume);
|
|
|
|
|
2020-04-21 10:00:11 +07:00
|
|
|
static const struct mtk_rtc_data mt6358_rtc_data = {
|
|
|
|
.wrtgr = RTC_WRTGR_MT6358,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct mtk_rtc_data mt6397_rtc_data = {
|
|
|
|
.wrtgr = RTC_WRTGR_MT6397,
|
|
|
|
};
|
|
|
|
|
2015-05-06 14:23:41 +07:00
|
|
|
static const struct of_device_id mt6397_rtc_of_match[] = {
|
2020-04-21 10:00:11 +07:00
|
|
|
{ .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data },
|
|
|
|
{ .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data },
|
|
|
|
{ .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data },
|
2015-05-06 14:23:41 +07:00
|
|
|
{ }
|
|
|
|
};
|
2015-08-27 18:52:02 +07:00
|
|
|
MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
|
2015-05-06 14:23:41 +07:00
|
|
|
|
|
|
|
static struct platform_driver mtk_rtc_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mt6397-rtc",
|
|
|
|
.of_match_table = mt6397_rtc_of_match,
|
2015-07-30 21:53:14 +07:00
|
|
|
.pm = &mt6397_pm_ops,
|
2015-05-06 14:23:41 +07:00
|
|
|
},
|
|
|
|
.probe = mtk_rtc_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(mtk_rtc_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
|
|
|
|
MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
|