2010-10-12 17:18:31 +07:00
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/*
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* Freescale SPI/eSPI controller driver library.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Copyright (C) 2006 Polycom, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __SPI_FSL_LIB_H__
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#define __SPI_FSL_LIB_H__
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2010-10-14 20:55:47 +07:00
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#include <asm/io.h>
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2010-10-12 17:18:31 +07:00
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/* SPI/eSPI Controller driver's private data. */
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struct mpc8xxx_spi {
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struct device *dev;
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void *reg_base;
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/* rx & tx bufs from the spi_transfer */
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const void *tx;
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void *rx;
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2015-01-06 20:07:34 +07:00
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#if IS_ENABLED(CONFIG_SPI_FSL_ESPI)
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spi/fsl_spi: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
4. The max transaction length limitation
The max transaction length one time is limitted by the SPCOM[TRANSLEN]
field which is 0xFFFF. When used mkfs.ext2 command to create ext2
filesystem on the flash, the read length will exceed the max value of
the SPCOM[TRANSLEN] field.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12 17:18:32 +07:00
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int len;
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#endif
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2010-10-12 17:18:31 +07:00
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int subblock;
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struct spi_pram __iomem *pram;
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2013-02-15 22:52:21 +07:00
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#ifdef CONFIG_FSL_SOC
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2010-10-12 17:18:31 +07:00
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struct cpm_buf_desc __iomem *tx_bd;
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struct cpm_buf_desc __iomem *rx_bd;
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2013-02-15 22:52:21 +07:00
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#endif
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2010-10-12 17:18:31 +07:00
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struct spi_transfer *xfer_in_progress;
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/* dma addresses for CPM transfers */
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dma_addr_t tx_dma;
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dma_addr_t rx_dma;
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bool map_tx_dma;
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bool map_rx_dma;
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dma_addr_t dma_dummy_tx;
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dma_addr_t dma_dummy_rx;
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32(*get_tx) (struct mpc8xxx_spi *);
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unsigned int count;
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unsigned int irq;
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unsigned nsecs; /* (clock cycle time)/2 */
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u32 spibrg; /* SPIBRG input clock */
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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unsigned int flags;
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2015-01-06 20:07:34 +07:00
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#if IS_ENABLED(CONFIG_SPI_FSL_SPI)
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2013-02-15 22:52:24 +07:00
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int type;
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2013-02-15 22:52:27 +07:00
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int native_chipselects;
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2013-02-15 22:52:25 +07:00
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u8 max_bits_per_word;
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2013-02-15 22:52:24 +07:00
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2013-02-15 22:52:23 +07:00
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void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first);
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#endif
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2010-10-12 17:18:31 +07:00
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struct completion done;
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};
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struct spi_mpc8xxx_cs {
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32 (*get_tx) (struct mpc8xxx_spi *);
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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u32 hw_mode; /* Holds HW mode register settings */
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};
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static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
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{
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2013-02-15 22:52:21 +07:00
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iowrite32be(val, reg);
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2010-10-12 17:18:31 +07:00
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}
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static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
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{
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2013-02-15 22:52:21 +07:00
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return ioread32be(reg);
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2010-10-12 17:18:31 +07:00
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}
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struct mpc8xxx_spi_probe_info {
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struct fsl_spi_platform_data pdata;
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int *gpios;
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bool *alow_flags;
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};
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extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
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extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
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extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
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extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
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extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
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extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
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extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
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struct fsl_spi_platform_data *pdata);
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extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, unsigned int len);
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extern const char *mpc8xxx_spi_strmode(unsigned int flags);
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2014-12-03 13:56:17 +07:00
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extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
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2010-10-12 17:18:31 +07:00
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unsigned int irq);
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extern int mpc8xxx_spi_remove(struct device *dev);
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2011-02-23 11:02:43 +07:00
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extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
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2010-10-12 17:18:31 +07:00
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#endif /* __SPI_FSL_LIB_H__ */
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