2012-09-21 15:07:49 +07:00
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/*
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* Copyright 2005-2009 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU Lesser General
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* Public License. You may obtain a copy of the GNU Lesser General
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* Public License Version 2.1 or later at the following locations:
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*
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* http://www.opensource.org/licenses/lgpl-license.html
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* http://www.gnu.org/copyleft/lgpl.html
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*/
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#ifndef __DRM_IPU_H__
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#define __DRM_IPU_H__
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <linux/bitmap.h>
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#include <linux/fb.h>
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2016-05-12 20:00:44 +07:00
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#include <linux/of.h>
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2014-08-20 00:52:40 +07:00
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#include <media/v4l2-mediabus.h>
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2014-12-19 09:00:20 +07:00
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#include <video/videomode.h>
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2012-09-21 15:07:49 +07:00
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struct ipu_soc;
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enum ipuv3_type {
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IPUV3EX,
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IPUV3M,
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IPUV3H,
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};
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2014-02-25 18:43:41 +07:00
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#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
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2012-09-21 15:07:49 +07:00
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/*
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* Bitfield of Display Interface signal polarities.
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*/
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struct ipu_di_signal_cfg {
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unsigned data_pol:1; /* true = inverted */
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unsigned clk_pol:1; /* true = rising edge */
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unsigned enable_pol:1;
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2014-12-19 09:00:25 +07:00
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struct videomode mode;
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2015-02-02 23:25:59 +07:00
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u32 bus_format;
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2012-09-21 15:07:49 +07:00
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u32 v_to_h_sync;
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2014-12-19 09:00:25 +07:00
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2012-09-21 15:07:49 +07:00
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#define IPU_DI_CLKMODE_SYNC (1 << 0)
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#define IPU_DI_CLKMODE_EXT (1 << 1)
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unsigned long clkflags;
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2013-04-08 23:04:35 +07:00
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u8 hsync_pin;
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u8 vsync_pin;
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2012-09-21 15:07:49 +07:00
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};
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2014-08-20 00:52:40 +07:00
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/*
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* Enumeration of CSI destinations
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*/
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enum ipu_csi_dest {
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IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
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IPU_CSI_DEST_IC, /* to Image Converter */
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IPU_CSI_DEST_VDIC, /* to VDIC */
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};
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2014-08-11 18:04:50 +07:00
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/*
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* Enumeration of IPU rotation modes
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*/
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2016-09-18 02:33:57 +07:00
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#define IPU_ROT_BIT_VFLIP (1 << 0)
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#define IPU_ROT_BIT_HFLIP (1 << 1)
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#define IPU_ROT_BIT_90 (1 << 2)
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2014-08-11 18:04:50 +07:00
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enum ipu_rotate_mode {
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IPU_ROTATE_NONE = 0,
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2016-09-18 02:33:57 +07:00
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IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
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IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
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IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
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IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
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IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
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IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
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IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
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IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
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2014-08-11 18:04:50 +07:00
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};
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2016-09-18 02:33:57 +07:00
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/* 90-degree rotations require the IRT unit */
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#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
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2012-09-21 15:07:49 +07:00
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enum ipu_color_space {
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IPUV3_COLORSPACE_RGB,
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IPUV3_COLORSPACE_YUV,
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IPUV3_COLORSPACE_UNKNOWN,
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};
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2016-08-18 07:50:16 +07:00
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/*
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* Enumeration of VDI MOTION select
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*/
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enum ipu_motion_sel {
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MOTION_NONE = 0,
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LOW_MOTION,
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MED_MOTION,
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HIGH_MOTION,
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};
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2012-09-21 15:07:49 +07:00
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struct ipuv3_channel;
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enum ipu_channel_irq {
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IPU_IRQ_EOF = 0,
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IPU_IRQ_NFACK = 64,
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IPU_IRQ_NFB4EOF = 128,
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IPU_IRQ_EOS = 192,
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};
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2014-06-26 08:05:39 +07:00
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/*
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* Enumeration of IDMAC channels
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*/
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#define IPUV3_CHANNEL_CSI0 0
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#define IPUV3_CHANNEL_CSI1 1
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#define IPUV3_CHANNEL_CSI2 2
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#define IPUV3_CHANNEL_CSI3 3
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#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
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2016-08-18 07:50:17 +07:00
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/*
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* NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
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* but the direct CSI->VDI linking is handled the same way as IDMAC
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* channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
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* these channel names are used to support the direct CSI->VDI link.
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*/
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#define IPUV3_CHANNEL_CSI_DIRECT 6
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#define IPUV3_CHANNEL_CSI_VDI_PREV 7
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2016-07-20 08:11:05 +07:00
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#define IPUV3_CHANNEL_MEM_VDI_PREV 8
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#define IPUV3_CHANNEL_MEM_VDI_CUR 9
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#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
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2014-06-26 08:05:39 +07:00
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#define IPUV3_CHANNEL_MEM_IC_PP 11
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#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
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2014-07-30 19:10:51 +07:00
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#define IPUV3_CHANNEL_VDI_MEM_RECENT 13
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2014-06-26 08:05:39 +07:00
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#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
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#define IPUV3_CHANNEL_G_MEM_IC_PP 15
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2014-07-30 19:10:51 +07:00
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#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
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#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
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#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
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2014-06-26 08:05:39 +07:00
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#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
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#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
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#define IPUV3_CHANNEL_IC_PP_MEM 22
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#define IPUV3_CHANNEL_MEM_BG_SYNC 23
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#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
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2014-07-30 19:10:51 +07:00
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#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
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#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
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2014-06-26 08:05:39 +07:00
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#define IPUV3_CHANNEL_MEM_FG_SYNC 27
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#define IPUV3_CHANNEL_MEM_DC_SYNC 28
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#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
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#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
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2014-07-30 19:10:51 +07:00
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#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
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#define IPUV3_CHANNEL_DC_MEM_READ 40
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2014-06-26 08:05:39 +07:00
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#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
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2014-07-30 19:10:51 +07:00
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#define IPUV3_CHANNEL_MEM_DC_COMMAND 42
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#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
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#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
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2014-06-26 08:05:39 +07:00
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#define IPUV3_CHANNEL_MEM_ROT_ENC 45
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#define IPUV3_CHANNEL_MEM_ROT_VF 46
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#define IPUV3_CHANNEL_MEM_ROT_PP 47
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#define IPUV3_CHANNEL_ROT_ENC_MEM 48
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#define IPUV3_CHANNEL_ROT_VF_MEM 49
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#define IPUV3_CHANNEL_ROT_PP_MEM 50
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#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
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2014-07-30 19:10:51 +07:00
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#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
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2016-08-18 07:50:17 +07:00
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#define IPUV3_NUM_CHANNELS 64
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2014-06-26 08:05:39 +07:00
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2015-01-09 17:03:13 +07:00
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static inline int ipu_channel_alpha_channel(int ch_num)
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{
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switch (ch_num) {
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case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
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return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
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case IPUV3_CHANNEL_G_MEM_IC_PP:
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return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
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case IPUV3_CHANNEL_MEM_FG_SYNC:
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return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
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case IPUV3_CHANNEL_MEM_FG_ASYNC:
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return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
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case IPUV3_CHANNEL_MEM_BG_SYNC:
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return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
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case IPUV3_CHANNEL_MEM_BG_ASYNC:
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return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
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case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
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return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
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default:
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return -EINVAL;
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}
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}
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2014-04-15 04:53:16 +07:00
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int ipu_map_irq(struct ipu_soc *ipu, int irq);
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2012-09-21 15:07:49 +07:00
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int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
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enum ipu_channel_irq irq);
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#define IPU_IRQ_DP_SF_START (448 + 2)
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#define IPU_IRQ_DP_SF_END (448 + 3)
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#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
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#define IPU_IRQ_DC_FC_0 (448 + 8)
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#define IPU_IRQ_DC_FC_1 (448 + 9)
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#define IPU_IRQ_DC_FC_2 (448 + 10)
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#define IPU_IRQ_DC_FC_3 (448 + 11)
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#define IPU_IRQ_DC_FC_4 (448 + 12)
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#define IPU_IRQ_DC_FC_6 (448 + 13)
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#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
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#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
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2014-06-26 08:05:30 +07:00
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/*
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* IPU Common functions
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*/
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2016-07-20 08:11:02 +07:00
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int ipu_get_num(struct ipu_soc *ipu);
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2014-06-26 08:05:30 +07:00
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void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
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void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
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2014-06-26 08:05:55 +07:00
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void ipu_dump(struct ipu_soc *ipu);
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2014-06-26 08:05:30 +07:00
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2012-09-21 15:07:49 +07:00
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/*
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* IPU Image DMA Controller (idmac) functions
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*/
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struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
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void ipu_idmac_put(struct ipuv3_channel *);
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int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
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2014-06-26 08:05:44 +07:00
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void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
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2014-06-26 08:05:45 +07:00
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int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
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2013-10-10 21:18:41 +07:00
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
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2012-09-21 15:07:49 +07:00
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void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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bool doublebuffer);
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2012-05-16 22:28:29 +07:00
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int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
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2014-06-26 08:05:40 +07:00
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bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
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2012-09-21 15:07:49 +07:00
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void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
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2014-06-26 08:05:41 +07:00
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void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
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2016-08-18 07:50:17 +07:00
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int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
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int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
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int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
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int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
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2012-09-21 15:07:49 +07:00
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2014-06-26 08:05:47 +07:00
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/*
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* IPU Channel Parameter Memory (cpmem) functions
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*/
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struct ipu_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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int bits_per_pixel;
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};
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struct ipu_image {
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struct v4l2_pix_format pix;
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struct v4l2_rect rect;
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2014-06-26 08:05:52 +07:00
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dma_addr_t phys0;
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dma_addr_t phys1;
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2018-10-07 04:45:48 +07:00
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/* chroma plane offset overrides */
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u32 u_offset;
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u32 v_offset;
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2014-06-26 08:05:47 +07:00
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};
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void ipu_cpmem_zero(struct ipuv3_channel *ch);
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void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
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2014-09-17 20:44:54 +07:00
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void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
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2014-06-26 08:05:47 +07:00
|
|
|
void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
|
|
|
|
|
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
|
|
|
|
|
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
|
2016-07-20 08:11:00 +07:00
|
|
|
void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
|
2019-01-10 01:30:06 +07:00
|
|
|
void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
|
|
|
|
|
u32 pixelformat);
|
2014-06-26 08:05:50 +07:00
|
|
|
void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
|
2016-07-20 08:11:01 +07:00
|
|
|
int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
|
2014-06-26 08:05:47 +07:00
|
|
|
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
|
2014-06-26 08:05:49 +07:00
|
|
|
void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
|
2014-06-26 08:05:51 +07:00
|
|
|
void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
|
|
|
|
|
enum ipu_rotate_mode rot);
|
2014-06-26 08:05:47 +07:00
|
|
|
int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
|
|
|
|
|
const struct ipu_rgb *rgb);
|
|
|
|
|
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
|
|
|
|
|
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
|
|
|
|
|
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
|
2016-02-23 16:22:50 +07:00
|
|
|
unsigned int uv_stride,
|
|
|
|
|
unsigned int u_offset,
|
|
|
|
|
unsigned int v_offset);
|
2014-06-26 08:05:47 +07:00
|
|
|
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
|
|
|
|
|
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
|
2014-06-26 08:05:54 +07:00
|
|
|
void ipu_cpmem_dump(struct ipuv3_channel *ch);
|
2014-06-26 08:05:47 +07:00
|
|
|
|
2012-09-21 15:07:49 +07:00
|
|
|
/*
|
|
|
|
|
* IPU Display Controller (dc) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_dc;
|
|
|
|
|
struct ipu_di;
|
|
|
|
|
struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
|
|
|
|
|
void ipu_dc_put(struct ipu_dc *dc);
|
|
|
|
|
int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
|
|
|
|
|
u32 pixel_fmt, u32 width);
|
2014-04-15 04:53:23 +07:00
|
|
|
void ipu_dc_enable(struct ipu_soc *ipu);
|
2012-09-21 15:07:49 +07:00
|
|
|
void ipu_dc_enable_channel(struct ipu_dc *dc);
|
|
|
|
|
void ipu_dc_disable_channel(struct ipu_dc *dc);
|
2014-04-15 04:53:23 +07:00
|
|
|
void ipu_dc_disable(struct ipu_soc *ipu);
|
2012-09-21 15:07:49 +07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IPU Display Interface (di) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
|
|
|
|
|
void ipu_di_put(struct ipu_di *);
|
|
|
|
|
int ipu_di_disable(struct ipu_di *);
|
|
|
|
|
int ipu_di_enable(struct ipu_di *);
|
|
|
|
|
int ipu_di_get_num(struct ipu_di *);
|
2014-12-19 09:00:20 +07:00
|
|
|
int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
|
2012-09-21 15:07:49 +07:00
|
|
|
int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IPU Display Multi FIFO Controller (dmfc) functions
|
|
|
|
|
*/
|
|
|
|
|
struct dmfc_channel;
|
|
|
|
|
int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
|
|
|
|
|
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
|
2016-03-14 15:10:10 +07:00
|
|
|
void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
|
2012-09-21 15:07:49 +07:00
|
|
|
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
|
|
|
|
|
void ipu_dmfc_put(struct dmfc_channel *dmfc);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IPU Display Processor (dp) functions
|
|
|
|
|
*/
|
|
|
|
|
#define IPU_DP_FLOW_SYNC_BG 0
|
|
|
|
|
#define IPU_DP_FLOW_SYNC_FG 1
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC0_BG 2
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC0_FG 3
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC1_BG 4
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC1_FG 5
|
|
|
|
|
|
|
|
|
|
struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
|
|
|
|
|
void ipu_dp_put(struct ipu_dp *);
|
2014-04-15 04:53:20 +07:00
|
|
|
int ipu_dp_enable(struct ipu_soc *ipu);
|
2012-09-21 15:07:49 +07:00
|
|
|
int ipu_dp_enable_channel(struct ipu_dp *dp);
|
2017-02-25 00:23:55 +07:00
|
|
|
void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
|
2014-04-15 04:53:20 +07:00
|
|
|
void ipu_dp_disable(struct ipu_soc *ipu);
|
2012-09-21 15:07:49 +07:00
|
|
|
int ipu_dp_setup_channel(struct ipu_dp *dp,
|
|
|
|
|
enum ipu_color_space in, enum ipu_color_space out);
|
|
|
|
|
int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
|
|
|
|
|
int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
|
|
|
|
|
bool bg_chan);
|
|
|
|
|
|
2017-03-08 18:13:16 +07:00
|
|
|
/*
|
|
|
|
|
* IPU Prefetch Resolve Gasket (prg) functions
|
|
|
|
|
*/
|
|
|
|
|
int ipu_prg_max_active_channels(void);
|
|
|
|
|
bool ipu_prg_present(struct ipu_soc *ipu);
|
|
|
|
|
bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
|
|
|
|
|
uint64_t modifier);
|
|
|
|
|
int ipu_prg_enable(struct ipu_soc *ipu);
|
|
|
|
|
void ipu_prg_disable(struct ipu_soc *ipu);
|
|
|
|
|
void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
|
|
|
|
|
int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
|
|
|
|
|
unsigned int axi_id, unsigned int width,
|
|
|
|
|
unsigned int height, unsigned int stride,
|
2017-11-10 23:09:59 +07:00
|
|
|
u32 format, uint64_t modifier, unsigned long *eba);
|
2018-09-11 20:26:54 +07:00
|
|
|
bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan);
|
2017-03-08 18:13:16 +07:00
|
|
|
|
2012-05-22 22:08:48 +07:00
|
|
|
/*
|
|
|
|
|
* IPU CMOS Sensor Interface (csi) functions
|
|
|
|
|
*/
|
2014-08-20 00:52:40 +07:00
|
|
|
struct ipu_csi;
|
|
|
|
|
int ipu_csi_init_interface(struct ipu_csi *csi,
|
2019-01-10 01:30:05 +07:00
|
|
|
const struct v4l2_mbus_config *mbus_cfg,
|
|
|
|
|
const struct v4l2_mbus_framefmt *infmt,
|
|
|
|
|
const struct v4l2_mbus_framefmt *outfmt);
|
2014-08-20 00:52:40 +07:00
|
|
|
bool ipu_csi_is_interlaced(struct ipu_csi *csi);
|
|
|
|
|
void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
|
|
|
|
|
void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
|
2016-10-05 22:33:45 +07:00
|
|
|
void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
|
2014-08-20 00:52:40 +07:00
|
|
|
void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
|
|
|
|
|
u32 r_value, u32 g_value, u32 b_value,
|
|
|
|
|
u32 pix_clk);
|
|
|
|
|
int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
|
|
|
|
|
struct v4l2_mbus_framefmt *mbus_fmt);
|
|
|
|
|
int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
|
|
|
|
|
u32 max_ratio, u32 id);
|
|
|
|
|
int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
|
|
|
|
|
int ipu_csi_enable(struct ipu_csi *csi);
|
|
|
|
|
int ipu_csi_disable(struct ipu_csi *csi);
|
|
|
|
|
struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
|
|
|
|
|
void ipu_csi_put(struct ipu_csi *csi);
|
|
|
|
|
void ipu_csi_dump(struct ipu_csi *csi);
|
2012-05-22 22:08:48 +07:00
|
|
|
|
2014-08-11 18:04:50 +07:00
|
|
|
/*
|
|
|
|
|
* IPU Image Converter (ic) functions
|
|
|
|
|
*/
|
|
|
|
|
enum ipu_ic_task {
|
|
|
|
|
IC_TASK_ENCODER,
|
|
|
|
|
IC_TASK_VIEWFINDER,
|
|
|
|
|
IC_TASK_POST_PROCESSOR,
|
|
|
|
|
IC_NUM_TASKS,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct ipu_ic;
|
|
|
|
|
int ipu_ic_task_init(struct ipu_ic *ic,
|
|
|
|
|
int in_width, int in_height,
|
|
|
|
|
int out_width, int out_height,
|
|
|
|
|
enum ipu_color_space in_cs,
|
|
|
|
|
enum ipu_color_space out_cs);
|
2018-09-18 16:34:08 +07:00
|
|
|
int ipu_ic_task_init_rsc(struct ipu_ic *ic,
|
|
|
|
|
int in_width, int in_height,
|
|
|
|
|
int out_width, int out_height,
|
|
|
|
|
enum ipu_color_space in_cs,
|
|
|
|
|
enum ipu_color_space out_cs,
|
|
|
|
|
u32 rsc);
|
2014-08-11 18:04:50 +07:00
|
|
|
int ipu_ic_task_graphics_init(struct ipu_ic *ic,
|
|
|
|
|
enum ipu_color_space in_g_cs,
|
|
|
|
|
bool galpha_en, u32 galpha,
|
|
|
|
|
bool colorkey_en, u32 colorkey);
|
|
|
|
|
void ipu_ic_task_enable(struct ipu_ic *ic);
|
|
|
|
|
void ipu_ic_task_disable(struct ipu_ic *ic);
|
|
|
|
|
int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
|
|
|
|
|
u32 width, u32 height, int burst_size,
|
|
|
|
|
enum ipu_rotate_mode rot);
|
|
|
|
|
int ipu_ic_enable(struct ipu_ic *ic);
|
|
|
|
|
int ipu_ic_disable(struct ipu_ic *ic);
|
|
|
|
|
struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
|
|
|
|
|
void ipu_ic_put(struct ipu_ic *ic);
|
|
|
|
|
void ipu_ic_dump(struct ipu_ic *ic);
|
|
|
|
|
|
2016-08-18 07:50:16 +07:00
|
|
|
/*
|
|
|
|
|
* IPU Video De-Interlacer (vdi) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_vdi;
|
|
|
|
|
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
|
|
|
|
|
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
|
|
|
|
|
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
|
|
|
|
|
void ipu_vdi_unsetup(struct ipu_vdi *vdi);
|
|
|
|
|
int ipu_vdi_enable(struct ipu_vdi *vdi);
|
|
|
|
|
int ipu_vdi_disable(struct ipu_vdi *vdi);
|
|
|
|
|
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
|
|
|
|
|
void ipu_vdi_put(struct ipu_vdi *vdi);
|
|
|
|
|
|
2012-05-09 21:59:01 +07:00
|
|
|
/*
|
|
|
|
|
* IPU Sensor Multiple FIFO Controller (SMFC) functions
|
|
|
|
|
*/
|
2014-06-26 08:05:34 +07:00
|
|
|
struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
|
|
|
|
|
void ipu_smfc_put(struct ipu_smfc *smfc);
|
|
|
|
|
int ipu_smfc_enable(struct ipu_smfc *smfc);
|
|
|
|
|
int ipu_smfc_disable(struct ipu_smfc *smfc);
|
|
|
|
|
int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
|
|
|
|
|
int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
|
2014-06-26 08:05:35 +07:00
|
|
|
int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
|
2012-05-09 21:59:01 +07:00
|
|
|
|
2013-10-10 21:18:38 +07:00
|
|
|
enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
|
2012-09-21 15:07:49 +07:00
|
|
|
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
|
2014-06-26 08:05:36 +07:00
|
|
|
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
|
2014-06-26 08:05:43 +07:00
|
|
|
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
|
2014-06-26 08:05:38 +07:00
|
|
|
bool ipu_pixelformat_is_planar(u32 pixelformat);
|
2014-06-26 08:05:37 +07:00
|
|
|
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
|
|
|
|
|
bool hflip, bool vflip);
|
|
|
|
|
int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
|
|
|
|
|
bool hflip, bool vflip);
|
2012-09-21 15:07:49 +07:00
|
|
|
|
|
|
|
|
struct ipu_client_platformdata {
|
2012-05-23 22:08:19 +07:00
|
|
|
int csi;
|
2012-09-21 15:07:49 +07:00
|
|
|
int di;
|
|
|
|
|
int dc;
|
|
|
|
|
int dp;
|
|
|
|
|
int dma[2];
|
2016-05-12 20:00:44 +07:00
|
|
|
struct device_node *of_node;
|
2012-09-21 15:07:49 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif /* __DRM_IPU_H__ */
|
