2005-04-17 05:20:36 +07:00
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/*
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* File: msi.c
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* Purpose: PCI Message Signaled Interrupt (MSI)
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*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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2016-07-12 16:20:17 +07:00
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* Copyright (C) 2016 Christoph Hellwig.
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2005-04-17 05:20:36 +07:00
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*/
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2006-10-04 16:16:41 +07:00
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#include <linux/err.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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2011-05-27 20:37:25 +07:00
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#include <linux/export.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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2006-10-04 16:16:59 +07:00
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#include <linux/msi.h>
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2007-04-27 08:21:38 +07:00
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#include <linux/smp.h>
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2009-08-10 08:14:15 +07:00
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#include <linux/errno.h>
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#include <linux/io.h>
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2016-09-13 01:32:22 +07:00
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#include <linux/acpi_iort.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/slab.h>
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2014-11-11 20:02:18 +07:00
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#include <linux/irqdomain.h>
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2015-10-09 05:10:49 +07:00
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#include <linux/of_irq.h>
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2005-04-17 05:20:36 +07:00
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#include "pci.h"
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static int pci_msi_enable = 1;
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2014-10-27 09:44:36 +07:00
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int pci_msi_ignore_mask;
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2005-04-17 05:20:36 +07:00
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2013-04-18 06:44:48 +07:00
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#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
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2014-11-15 21:24:07 +07:00
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#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
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static struct irq_domain *pci_msi_default_domain;
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static DEFINE_MUTEX(pci_msi_domain_lock);
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struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
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{
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return pci_msi_default_domain;
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}
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2014-11-15 17:49:12 +07:00
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static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
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{
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2015-07-28 20:46:14 +07:00
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struct irq_domain *domain;
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2014-11-15 17:49:12 +07:00
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2015-07-28 20:46:14 +07:00
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domain = dev_get_msi_domain(&dev->dev);
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if (domain)
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return domain;
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2014-11-15 17:49:12 +07:00
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2015-07-28 20:46:14 +07:00
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return arch_get_pci_msi_domain(dev);
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2014-11-15 17:49:12 +07:00
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}
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2014-11-15 21:24:07 +07:00
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static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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struct irq_domain *domain;
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2014-11-15 17:49:12 +07:00
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domain = pci_msi_get_domain(dev);
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2015-12-04 23:28:14 +07:00
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if (domain && irq_domain_is_hierarchy(domain))
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2014-11-15 21:24:07 +07:00
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return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
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return arch_setup_msi_irqs(dev, nvec, type);
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}
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static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
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{
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struct irq_domain *domain;
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2014-11-15 17:49:12 +07:00
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domain = pci_msi_get_domain(dev);
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2015-12-04 23:28:14 +07:00
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if (domain && irq_domain_is_hierarchy(domain))
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2014-11-15 21:24:07 +07:00
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pci_msi_domain_free_irqs(domain, dev);
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else
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arch_teardown_msi_irqs(dev);
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}
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#else
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#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
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#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
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#endif
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2013-04-18 06:44:48 +07:00
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2007-12-12 05:19:41 +07:00
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/* Arch hooks */
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2013-08-10 03:27:06 +07:00
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int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
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{
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2015-08-04 10:04:06 +07:00
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struct msi_controller *chip = dev->bus->msi;
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2013-08-10 03:27:08 +07:00
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int err;
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if (!chip || !chip->setup_irq)
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return -EINVAL;
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err = chip->setup_irq(chip, dev, desc);
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if (err < 0)
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return err;
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irq_set_chip_data(desc->irq, chip);
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return 0;
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2013-08-10 03:27:06 +07:00
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}
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void __weak arch_teardown_msi_irq(unsigned int irq)
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2007-12-12 05:19:41 +07:00
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{
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2014-11-12 07:45:45 +07:00
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struct msi_controller *chip = irq_get_chip_data(irq);
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2013-08-10 03:27:08 +07:00
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if (!chip || !chip->teardown_irq)
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return;
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chip->teardown_irq(chip, irq);
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2007-12-12 05:19:41 +07:00
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}
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2013-08-10 03:27:06 +07:00
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int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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2007-12-12 05:19:41 +07:00
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{
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2015-09-19 01:58:34 +07:00
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struct msi_controller *chip = dev->bus->msi;
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2007-12-12 05:19:41 +07:00
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struct msi_desc *entry;
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int ret;
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2015-09-19 01:58:34 +07:00
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if (chip && chip->setup_irqs)
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return chip->setup_irqs(chip, dev, nvec, type);
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2009-03-17 19:54:10 +07:00
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/*
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* If an architecture wants to support multiple MSI, it needs to
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* override arch_setup_msi_irqs()
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*/
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if (type == PCI_CAP_ID_MSI && nvec > 1)
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return 1;
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2015-07-09 15:00:41 +07:00
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for_each_pci_msi_entry(entry, dev) {
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2007-12-12 05:19:41 +07:00
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ret = arch_setup_msi_irq(dev, entry);
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2009-02-11 18:27:02 +07:00
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if (ret < 0)
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2007-12-12 05:19:41 +07:00
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return ret;
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2009-02-11 18:27:02 +07:00
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if (ret > 0)
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return -ENOSPC;
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2007-12-12 05:19:41 +07:00
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}
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return 0;
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}
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2010-10-07 03:05:35 +07:00
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2013-08-10 03:27:06 +07:00
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/*
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* We have a default implementation available as a separate non-weak
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* function, as it is used by the Xen x86 PCI code
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*/
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2010-10-07 03:05:35 +07:00
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void default_teardown_msi_irqs(struct pci_dev *dev)
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2007-12-12 05:19:41 +07:00
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{
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2014-11-06 21:20:32 +07:00
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int i;
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2007-12-12 05:19:41 +07:00
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struct msi_desc *entry;
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2015-07-09 15:00:41 +07:00
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for_each_pci_msi_entry(entry, dev)
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2014-11-06 21:20:32 +07:00
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if (entry->irq)
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for (i = 0; i < entry->nvec_used; i++)
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arch_teardown_msi_irq(entry->irq + i);
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2007-12-12 05:19:41 +07:00
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}
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2013-08-10 03:27:06 +07:00
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void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
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{
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return default_teardown_msi_irqs(dev);
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}
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2011-12-17 05:38:18 +07:00
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2013-12-04 12:09:16 +07:00
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static void default_restore_msi_irq(struct pci_dev *dev, int irq)
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2011-12-17 05:38:18 +07:00
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{
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struct msi_desc *entry;
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entry = NULL;
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if (dev->msix_enabled) {
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2015-07-09 15:00:41 +07:00
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for_each_pci_msi_entry(entry, dev) {
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2011-12-17 05:38:18 +07:00
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if (irq == entry->irq)
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break;
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}
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} else if (dev->msi_enabled) {
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entry = irq_get_msi_desc(irq);
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}
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if (entry)
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2014-11-09 22:10:34 +07:00
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__pci_write_msi_msg(entry, &entry->msg);
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2011-12-17 05:38:18 +07:00
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}
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2013-08-10 03:27:06 +07:00
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2013-12-04 12:09:16 +07:00
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void __weak arch_restore_msi_irqs(struct pci_dev *dev)
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2013-08-10 03:27:06 +07:00
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{
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2013-12-04 12:09:16 +07:00
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return default_restore_msi_irqs(dev);
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2013-08-10 03:27:06 +07:00
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}
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2011-12-17 05:38:18 +07:00
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2009-01-22 07:19:19 +07:00
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static inline __attribute_const__ u32 msi_mask(unsigned x)
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{
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2009-02-09 10:27:47 +07:00
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/* Don't shift by >= width of type */
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if (x >= 5)
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return 0xffffffff;
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return (1 << (1 << x)) - 1;
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2009-01-22 07:19:19 +07:00
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}
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2008-07-26 04:42:58 +07:00
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/*
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* PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
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* mask all MSI interrupts by clearing the MSI enable bit does not work
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* reliably as devices without an INTx disable bit will then generate a
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* level IRQ which will never be cleared.
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*/
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2014-11-23 17:55:58 +07:00
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u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
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2005-04-17 05:20:36 +07:00
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{
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2009-03-17 19:54:09 +07:00
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u32 mask_bits = desc->masked;
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2005-04-17 05:20:36 +07:00
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2014-10-27 09:44:36 +07:00
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if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
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PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
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return 0;
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2009-03-17 19:54:09 +07:00
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mask_bits &= ~mask;
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mask_bits |= flag;
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2015-07-09 15:00:43 +07:00
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pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
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mask_bits);
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
|
|
|
|
return mask_bits;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
|
|
|
|
{
|
2014-11-23 17:55:58 +07:00
|
|
|
desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
|
2009-03-17 19:54:09 +07:00
|
|
|
}
|
|
|
|
|
2016-07-12 16:20:14 +07:00
|
|
|
static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
return desc->mask_base +
|
|
|
|
desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
|
|
|
|
}
|
|
|
|
|
2009-03-17 19:54:09 +07:00
|
|
|
/*
|
|
|
|
* This internal function does not flush PCI writes to the device.
|
|
|
|
* All users must ensure that they read from the device before either
|
|
|
|
* assuming that the device state is up to date, or returning out of this
|
|
|
|
* file. This saves a few milliseconds when initialising devices with lots
|
|
|
|
* of MSI-X interrupts.
|
|
|
|
*/
|
2014-11-23 17:55:58 +07:00
|
|
|
u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
|
2009-03-17 19:54:09 +07:00
|
|
|
{
|
|
|
|
u32 mask_bits = desc->masked;
|
2014-10-27 09:44:36 +07:00
|
|
|
|
|
|
|
if (pci_msi_ignore_mask)
|
|
|
|
return 0;
|
|
|
|
|
2010-11-11 14:46:55 +07:00
|
|
|
mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
|
|
|
|
if (flag)
|
|
|
|
mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
|
2016-07-12 16:20:14 +07:00
|
|
|
writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
|
|
|
|
return mask_bits;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void msix_mask_irq(struct msi_desc *desc, u32 flag)
|
|
|
|
{
|
2014-11-23 17:55:58 +07:00
|
|
|
desc->masked = __pci_msix_desc_mask_irq(desc, flag);
|
2009-03-17 19:54:09 +07:00
|
|
|
}
|
2009-03-17 19:54:06 +07:00
|
|
|
|
2010-09-28 21:46:51 +07:00
|
|
|
static void msi_set_mask_bit(struct irq_data *data, u32 flag)
|
2009-03-17 19:54:09 +07:00
|
|
|
{
|
2015-06-01 15:05:41 +07:00
|
|
|
struct msi_desc *desc = irq_data_get_msi_desc(data);
|
2009-03-17 19:54:06 +07:00
|
|
|
|
2009-03-17 19:54:09 +07:00
|
|
|
if (desc->msi_attrib.is_msix) {
|
|
|
|
msix_mask_irq(desc, flag);
|
|
|
|
readl(desc->mask_base); /* Flush write to device */
|
|
|
|
} else {
|
2014-07-08 09:08:55 +07:00
|
|
|
unsigned offset = data->irq - desc->irq;
|
2009-03-17 19:54:10 +07:00
|
|
|
msi_mask_irq(desc, 1 << offset, flag << offset);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2009-03-17 19:54:09 +07:00
|
|
|
}
|
|
|
|
|
2014-11-23 17:55:58 +07:00
|
|
|
/**
|
|
|
|
* pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
|
|
|
|
* @data: pointer to irqdata associated to that interrupt
|
|
|
|
*/
|
|
|
|
void pci_msi_mask_irq(struct irq_data *data)
|
2009-03-17 19:54:09 +07:00
|
|
|
{
|
2010-09-28 21:46:51 +07:00
|
|
|
msi_set_mask_bit(data, 1);
|
2009-03-17 19:54:09 +07:00
|
|
|
}
|
2015-12-11 00:52:59 +07:00
|
|
|
EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
|
2009-03-17 19:54:09 +07:00
|
|
|
|
2014-11-23 17:55:58 +07:00
|
|
|
/**
|
|
|
|
* pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
|
|
|
|
* @data: pointer to irqdata associated to that interrupt
|
|
|
|
*/
|
|
|
|
void pci_msi_unmask_irq(struct irq_data *data)
|
2009-03-17 19:54:09 +07:00
|
|
|
{
|
2010-09-28 21:46:51 +07:00
|
|
|
msi_set_mask_bit(data, 0);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2015-12-11 00:52:59 +07:00
|
|
|
EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2013-12-04 12:09:16 +07:00
|
|
|
void default_restore_msi_irqs(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev)
|
2013-12-04 12:09:16 +07:00
|
|
|
default_restore_msi_irq(dev, entry->irq);
|
|
|
|
}
|
|
|
|
|
2014-11-09 22:10:33 +07:00
|
|
|
void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2015-07-09 15:00:43 +07:00
|
|
|
struct pci_dev *dev = msi_desc_to_pci_dev(entry);
|
|
|
|
|
|
|
|
BUG_ON(dev->current_state != PCI_D0);
|
2010-07-23 20:56:28 +07:00
|
|
|
|
|
|
|
if (entry->msi_attrib.is_msix) {
|
2016-07-12 16:20:14 +07:00
|
|
|
void __iomem *base = pci_msix_desc_addr(entry);
|
2010-07-23 20:56:28 +07:00
|
|
|
|
|
|
|
msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
|
|
|
|
msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
|
|
|
|
msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
|
|
|
|
} else {
|
2013-04-18 06:34:36 +07:00
|
|
|
int pos = dev->msi_cap;
|
2010-07-23 20:56:28 +07:00
|
|
|
u16 data;
|
|
|
|
|
2013-04-18 06:39:57 +07:00
|
|
|
pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
|
|
|
|
&msg->address_lo);
|
2010-07-23 20:56:28 +07:00
|
|
|
if (entry->msi_attrib.is_64) {
|
2013-04-18 06:39:57 +07:00
|
|
|
pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
|
|
|
|
&msg->address_hi);
|
2013-04-18 06:41:13 +07:00
|
|
|
pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
|
2010-07-23 20:56:28 +07:00
|
|
|
} else {
|
|
|
|
msg->address_hi = 0;
|
2013-04-18 06:41:13 +07:00
|
|
|
pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
|
2010-07-23 20:56:28 +07:00
|
|
|
}
|
|
|
|
msg->data = data;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-09 22:10:34 +07:00
|
|
|
void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
|
2008-12-06 09:58:34 +07:00
|
|
|
{
|
2015-07-09 15:00:43 +07:00
|
|
|
struct pci_dev *dev = msi_desc_to_pci_dev(entry);
|
|
|
|
|
|
|
|
if (dev->current_state != PCI_D0) {
|
2010-06-18 02:16:36 +07:00
|
|
|
/* Don't touch the hardware now */
|
|
|
|
} else if (entry->msi_attrib.is_msix) {
|
2016-07-12 16:20:14 +07:00
|
|
|
void __iomem *base = pci_msix_desc_addr(entry);
|
2009-03-17 19:54:06 +07:00
|
|
|
|
2009-06-23 15:40:04 +07:00
|
|
|
writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
|
|
|
|
writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
|
|
|
|
writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
|
2009-03-17 19:54:06 +07:00
|
|
|
} else {
|
2013-04-18 06:34:36 +07:00
|
|
|
int pos = dev->msi_cap;
|
2009-03-17 19:54:10 +07:00
|
|
|
u16 msgctl;
|
|
|
|
|
2013-04-18 06:38:32 +07:00
|
|
|
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
|
2009-03-17 19:54:10 +07:00
|
|
|
msgctl &= ~PCI_MSI_FLAGS_QSIZE;
|
|
|
|
msgctl |= entry->msi_attrib.multiple << 4;
|
2013-04-18 06:38:32 +07:00
|
|
|
pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
|
2006-10-04 16:16:33 +07:00
|
|
|
|
2013-04-18 06:39:57 +07:00
|
|
|
pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
|
|
|
|
msg->address_lo);
|
2006-10-04 16:16:33 +07:00
|
|
|
if (entry->msi_attrib.is_64) {
|
2013-04-18 06:39:57 +07:00
|
|
|
pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
|
|
|
|
msg->address_hi);
|
2013-04-18 06:41:13 +07:00
|
|
|
pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
|
|
|
|
msg->data);
|
2006-10-04 16:16:33 +07:00
|
|
|
} else {
|
2013-04-18 06:41:13 +07:00
|
|
|
pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
|
|
|
|
msg->data);
|
2006-10-04 16:16:33 +07:00
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2007-03-09 03:04:57 +07:00
|
|
|
entry->msg = *msg;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2006-10-04 16:16:33 +07:00
|
|
|
|
2014-11-09 22:10:34 +07:00
|
|
|
void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
|
2008-12-06 09:58:34 +07:00
|
|
|
{
|
2011-03-28 22:49:12 +07:00
|
|
|
struct msi_desc *entry = irq_get_msi_desc(irq);
|
2008-12-06 09:58:34 +07:00
|
|
|
|
2014-11-09 22:10:34 +07:00
|
|
|
__pci_write_msi_msg(entry, msg);
|
2008-12-06 09:58:34 +07:00
|
|
|
}
|
2014-11-09 22:10:34 +07:00
|
|
|
EXPORT_SYMBOL_GPL(pci_write_msi_msg);
|
2008-12-06 09:58:34 +07:00
|
|
|
|
2009-08-06 09:32:51 +07:00
|
|
|
static void free_msi_irqs(struct pci_dev *dev)
|
|
|
|
{
|
2015-07-09 15:00:41 +07:00
|
|
|
struct list_head *msi_list = dev_to_msi_list(&dev->dev);
|
2009-08-06 09:32:51 +07:00
|
|
|
struct msi_desc *entry, *tmp;
|
2013-12-20 03:30:17 +07:00
|
|
|
struct attribute **msi_attrs;
|
|
|
|
struct device_attribute *dev_attr;
|
2014-11-06 21:20:32 +07:00
|
|
|
int i, count = 0;
|
2009-08-06 09:32:51 +07:00
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev)
|
2014-11-06 21:20:32 +07:00
|
|
|
if (entry->irq)
|
|
|
|
for (i = 0; i < entry->nvec_used; i++)
|
|
|
|
BUG_ON(irq_has_action(entry->irq + i));
|
2009-08-06 09:32:51 +07:00
|
|
|
|
2014-11-15 21:24:07 +07:00
|
|
|
pci_msi_teardown_msi_irqs(dev);
|
2009-08-06 09:32:51 +07:00
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
list_for_each_entry_safe(entry, tmp, msi_list, list) {
|
2009-08-06 09:32:51 +07:00
|
|
|
if (entry->msi_attrib.is_msix) {
|
2015-07-09 15:00:41 +07:00
|
|
|
if (list_is_last(&entry->list, msi_list))
|
2009-08-06 09:32:51 +07:00
|
|
|
iounmap(entry->mask_base);
|
|
|
|
}
|
2012-01-03 22:29:54 +07:00
|
|
|
|
2009-08-06 09:32:51 +07:00
|
|
|
list_del(&entry->list);
|
|
|
|
kfree(entry);
|
|
|
|
}
|
2013-12-20 03:30:17 +07:00
|
|
|
|
|
|
|
if (dev->msi_irq_groups) {
|
|
|
|
sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
|
|
|
|
msi_attrs = dev->msi_irq_groups[0]->attrs;
|
2014-06-05 05:49:50 +07:00
|
|
|
while (msi_attrs[count]) {
|
2013-12-20 03:30:17 +07:00
|
|
|
dev_attr = container_of(msi_attrs[count],
|
|
|
|
struct device_attribute, attr);
|
|
|
|
kfree(dev_attr->attr.name);
|
|
|
|
kfree(dev_attr);
|
|
|
|
++count;
|
|
|
|
}
|
|
|
|
kfree(msi_attrs);
|
|
|
|
kfree(dev->msi_irq_groups[0]);
|
|
|
|
kfree(dev->msi_irq_groups);
|
|
|
|
dev->msi_irq_groups = NULL;
|
|
|
|
}
|
2009-08-06 09:32:51 +07:00
|
|
|
}
|
2007-01-18 11:50:05 +07:00
|
|
|
|
2007-10-25 15:16:30 +07:00
|
|
|
static void pci_intx_for_msi(struct pci_dev *dev, int enable)
|
|
|
|
{
|
|
|
|
if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
|
|
|
|
pci_intx(dev, enable);
|
|
|
|
}
|
|
|
|
|
2007-01-25 15:34:08 +07:00
|
|
|
static void __pci_restore_msi_state(struct pci_dev *dev)
|
2006-02-08 16:11:38 +07:00
|
|
|
{
|
|
|
|
u16 control;
|
2007-03-09 03:04:57 +07:00
|
|
|
struct msi_desc *entry;
|
2006-02-08 16:11:38 +07:00
|
|
|
|
2007-03-05 15:30:10 +07:00
|
|
|
if (!dev->msi_enabled)
|
|
|
|
return;
|
|
|
|
|
2011-03-28 22:49:12 +07:00
|
|
|
entry = irq_get_msi_desc(dev->irq);
|
2006-02-08 16:11:38 +07:00
|
|
|
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_intx_for_msi(dev, 0);
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msi_set_enable(dev, 0);
|
2013-12-04 12:09:16 +07:00
|
|
|
arch_restore_msi_irqs(dev);
|
2007-03-09 03:04:57 +07:00
|
|
|
|
2013-04-18 06:34:36 +07:00
|
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
2014-06-19 15:30:30 +07:00
|
|
|
msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
|
|
|
|
entry->masked);
|
2008-08-07 22:52:37 +07:00
|
|
|
control &= ~PCI_MSI_FLAGS_QSIZE;
|
2009-03-17 19:54:10 +07:00
|
|
|
control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
|
2013-04-18 06:34:36 +07:00
|
|
|
pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
|
2007-01-25 15:34:08 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __pci_restore_msix_state(struct pci_dev *dev)
|
2006-02-08 16:11:38 +07:00
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
|
|
|
|
2007-01-29 02:42:52 +07:00
|
|
|
if (!dev->msix_enabled)
|
|
|
|
return;
|
2015-07-09 15:00:41 +07:00
|
|
|
BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
|
2007-01-29 02:42:52 +07:00
|
|
|
|
2006-02-08 16:11:38 +07:00
|
|
|
/* route the table */
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_intx_for_msi(dev, 0);
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msix_clear_and_set_ctrl(dev, 0,
|
2014-06-19 15:29:53 +07:00
|
|
|
PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
|
2006-02-08 16:11:38 +07:00
|
|
|
|
2013-12-04 12:09:16 +07:00
|
|
|
arch_restore_msi_irqs(dev);
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev)
|
2009-03-17 19:54:09 +07:00
|
|
|
msix_mask_irq(entry, entry->masked);
|
2006-02-08 16:11:38 +07:00
|
|
|
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
2006-02-08 16:11:38 +07:00
|
|
|
}
|
2007-01-25 15:34:08 +07:00
|
|
|
|
|
|
|
void pci_restore_msi_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
__pci_restore_msi_state(dev);
|
|
|
|
__pci_restore_msix_state(dev);
|
|
|
|
}
|
2007-11-08 04:43:59 +07:00
|
|
|
EXPORT_SYMBOL_GPL(pci_restore_msi_state);
|
2006-02-08 16:11:38 +07:00
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
|
2011-10-07 01:08:18 +07:00
|
|
|
char *buf)
|
|
|
|
{
|
2013-12-20 03:30:17 +07:00
|
|
|
struct msi_desc *entry;
|
|
|
|
unsigned long irq;
|
|
|
|
int retval;
|
2011-10-07 01:08:18 +07:00
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
retval = kstrtoul(attr->attr.name, 10, &irq);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
2011-10-07 01:08:18 +07:00
|
|
|
|
2014-07-08 09:09:19 +07:00
|
|
|
entry = irq_get_msi_desc(irq);
|
|
|
|
if (entry)
|
|
|
|
return sprintf(buf, "%s\n",
|
|
|
|
entry->msi_attrib.is_msix ? "msix" : "msi");
|
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
return -ENODEV;
|
2011-10-07 01:08:18 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int populate_msi_sysfs(struct pci_dev *pdev)
|
|
|
|
{
|
2013-12-20 03:30:17 +07:00
|
|
|
struct attribute **msi_attrs;
|
|
|
|
struct attribute *msi_attr;
|
|
|
|
struct device_attribute *msi_dev_attr;
|
|
|
|
struct attribute_group *msi_irq_group;
|
|
|
|
const struct attribute_group **msi_irq_groups;
|
2011-10-07 01:08:18 +07:00
|
|
|
struct msi_desc *entry;
|
2013-12-20 03:30:17 +07:00
|
|
|
int ret = -ENOMEM;
|
|
|
|
int num_msi = 0;
|
2011-10-07 01:08:18 +07:00
|
|
|
int count = 0;
|
2015-09-24 06:31:16 +07:00
|
|
|
int i;
|
2011-10-07 01:08:18 +07:00
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
/* Determine how many msi entries we have */
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, pdev)
|
2015-09-24 06:31:16 +07:00
|
|
|
num_msi += entry->nvec_used;
|
2013-12-20 03:30:17 +07:00
|
|
|
if (!num_msi)
|
|
|
|
return 0;
|
2011-10-07 01:08:18 +07:00
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
/* Dynamically create the MSI attributes for the PCI device */
|
|
|
|
msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
|
|
|
|
if (!msi_attrs)
|
|
|
|
return -ENOMEM;
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, pdev) {
|
2015-09-24 06:31:16 +07:00
|
|
|
for (i = 0; i < entry->nvec_used; i++) {
|
|
|
|
msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
|
|
|
|
if (!msi_dev_attr)
|
|
|
|
goto error_attrs;
|
|
|
|
msi_attrs[count] = &msi_dev_attr->attr;
|
|
|
|
|
|
|
|
sysfs_attr_init(&msi_dev_attr->attr);
|
|
|
|
msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
|
|
|
|
entry->irq + i);
|
|
|
|
if (!msi_dev_attr->attr.name)
|
|
|
|
goto error_attrs;
|
|
|
|
msi_dev_attr->attr.mode = S_IRUGO;
|
|
|
|
msi_dev_attr->show = msi_mode_show;
|
|
|
|
++count;
|
|
|
|
}
|
2011-10-07 01:08:18 +07:00
|
|
|
}
|
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
|
|
|
|
if (!msi_irq_group)
|
|
|
|
goto error_attrs;
|
|
|
|
msi_irq_group->name = "msi_irqs";
|
|
|
|
msi_irq_group->attrs = msi_attrs;
|
|
|
|
|
|
|
|
msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
|
|
|
|
if (!msi_irq_groups)
|
|
|
|
goto error_irq_group;
|
|
|
|
msi_irq_groups[0] = msi_irq_group;
|
|
|
|
|
|
|
|
ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
|
|
|
|
if (ret)
|
|
|
|
goto error_irq_groups;
|
|
|
|
pdev->msi_irq_groups = msi_irq_groups;
|
|
|
|
|
2011-10-07 01:08:18 +07:00
|
|
|
return 0;
|
|
|
|
|
2013-12-20 03:30:17 +07:00
|
|
|
error_irq_groups:
|
|
|
|
kfree(msi_irq_groups);
|
|
|
|
error_irq_group:
|
|
|
|
kfree(msi_irq_group);
|
|
|
|
error_attrs:
|
|
|
|
count = 0;
|
|
|
|
msi_attr = msi_attrs[count];
|
|
|
|
while (msi_attr) {
|
|
|
|
msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
|
|
|
|
kfree(msi_attr->name);
|
|
|
|
kfree(msi_dev_attr);
|
|
|
|
++count;
|
|
|
|
msi_attr = msi_attrs[count];
|
2011-10-07 01:08:18 +07:00
|
|
|
}
|
2014-02-14 00:47:35 +07:00
|
|
|
kfree(msi_attrs);
|
2011-10-07 01:08:18 +07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
static struct msi_desc *
|
|
|
|
msi_setup_entry(struct pci_dev *dev, int nvec, bool affinity)
|
2014-07-08 09:07:23 +07:00
|
|
|
{
|
2016-09-14 21:18:49 +07:00
|
|
|
struct cpumask *masks = NULL;
|
2014-07-08 09:07:23 +07:00
|
|
|
struct msi_desc *entry;
|
2016-09-14 21:18:49 +07:00
|
|
|
u16 control;
|
|
|
|
|
|
|
|
if (affinity) {
|
|
|
|
masks = irq_create_affinity_masks(dev->irq_affinity, nvec);
|
|
|
|
if (!masks)
|
|
|
|
pr_err("Unable to allocate affinity masks, ignoring\n");
|
|
|
|
}
|
2014-07-08 09:07:23 +07:00
|
|
|
|
|
|
|
/* MSI Entry Initialization */
|
2016-09-14 21:18:49 +07:00
|
|
|
entry = alloc_msi_entry(&dev->dev, nvec, masks);
|
2014-07-08 09:07:23 +07:00
|
|
|
if (!entry)
|
2016-09-14 21:18:49 +07:00
|
|
|
goto out;
|
2014-07-08 09:07:23 +07:00
|
|
|
|
|
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
|
|
|
|
|
|
|
|
entry->msi_attrib.is_msix = 0;
|
|
|
|
entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
|
|
|
|
entry->msi_attrib.entry_nr = 0;
|
|
|
|
entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
|
|
|
|
entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
|
|
|
|
entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
|
2014-11-06 21:20:32 +07:00
|
|
|
entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
|
2014-07-08 09:07:23 +07:00
|
|
|
|
|
|
|
if (control & PCI_MSI_FLAGS_64BIT)
|
|
|
|
entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
|
|
|
|
else
|
|
|
|
entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
|
|
|
|
|
|
|
|
/* Save the initial mask status */
|
|
|
|
if (entry->msi_attrib.maskbit)
|
|
|
|
pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
|
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
out:
|
|
|
|
kfree(masks);
|
2014-07-08 09:07:23 +07:00
|
|
|
return entry;
|
|
|
|
}
|
|
|
|
|
2014-10-03 12:13:24 +07:00
|
|
|
static int msi_verify_entries(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev) {
|
2014-10-03 12:13:24 +07:00
|
|
|
if (!dev->no_64bit_msi || !entry->msg.address_hi)
|
|
|
|
continue;
|
|
|
|
dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
|
|
|
|
" tried to assign one above 4G\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/**
|
|
|
|
* msi_capability_init - configure device's MSI capability structure
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
2009-03-17 19:54:10 +07:00
|
|
|
* @nvec: number of interrupts to allocate
|
2016-10-23 23:32:34 +07:00
|
|
|
* @affinity: flag to indicate cpu irq affinity mask should be set
|
2005-04-17 05:20:36 +07:00
|
|
|
*
|
2009-03-17 19:54:10 +07:00
|
|
|
* Setup the MSI capability structure of the device with the requested
|
|
|
|
* number of interrupts. A return value of zero indicates the successful
|
|
|
|
* setup of an entry with the new MSI irq. A negative return value indicates
|
|
|
|
* an error, and a positive return value indicates the number of interrupts
|
|
|
|
* which could have been allocated.
|
|
|
|
*/
|
2016-09-14 21:18:49 +07:00
|
|
|
static int msi_capability_init(struct pci_dev *dev, int nvec, bool affinity)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
2013-04-04 23:54:32 +07:00
|
|
|
int ret;
|
2009-03-17 19:54:09 +07:00
|
|
|
unsigned mask;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
|
2009-06-16 19:31:45 +07:00
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
entry = msi_setup_entry(dev, nvec, affinity);
|
2007-01-29 02:56:37 +07:00
|
|
|
if (!entry)
|
|
|
|
return -ENOMEM;
|
2006-10-04 16:16:41 +07:00
|
|
|
|
2009-03-17 19:54:09 +07:00
|
|
|
/* All MSIs are unmasked by default, Mask them all */
|
2014-06-19 15:30:30 +07:00
|
|
|
mask = msi_mask(entry->msi_attrib.multi_cap);
|
2009-03-17 19:54:09 +07:00
|
|
|
msi_mask_irq(entry, mask, mask);
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 16:39:21 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Configure MSI capability structure */
|
2014-11-15 21:24:07 +07:00
|
|
|
ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
|
2007-04-18 16:39:21 +07:00
|
|
|
if (ret) {
|
2009-06-23 15:39:27 +07:00
|
|
|
msi_mask_irq(entry, mask, ~mask);
|
2009-08-06 09:32:51 +07:00
|
|
|
free_msi_irqs(dev);
|
2007-04-18 16:39:21 +07:00
|
|
|
return ret;
|
2006-04-11 09:17:48 +07:00
|
|
|
}
|
2007-01-29 02:56:37 +07:00
|
|
|
|
2014-10-03 12:13:24 +07:00
|
|
|
ret = msi_verify_entries(dev);
|
|
|
|
if (ret) {
|
|
|
|
msi_mask_irq(entry, mask, ~mask);
|
|
|
|
free_msi_irqs(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-10-07 01:08:18 +07:00
|
|
|
ret = populate_msi_sysfs(dev);
|
|
|
|
if (ret) {
|
|
|
|
msi_mask_irq(entry, mask, ~mask);
|
|
|
|
free_msi_irqs(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Set MSI enabled bits */
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_intx_for_msi(dev, 0);
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msi_set_enable(dev, 1);
|
2007-03-05 15:30:10 +07:00
|
|
|
dev->msi_enabled = 1;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2015-07-31 02:00:08 +07:00
|
|
|
pcibios_free_irq(dev);
|
2007-04-18 16:39:21 +07:00
|
|
|
dev->irq = entry->irq;
|
2005-04-17 05:20:36 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-04 23:54:33 +07:00
|
|
|
static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
|
2009-08-06 09:34:34 +07:00
|
|
|
{
|
2010-06-17 08:42:44 +07:00
|
|
|
resource_size_t phys_addr;
|
2009-08-06 09:34:34 +07:00
|
|
|
u32 table_offset;
|
PCI: Fail MSI-X mappings if there's no space assigned to MSI-X BAR
Unlike MSI, which is configured via registers in the MSI capability in
Configuration Space, MSI-X is configured via tables in Memory Space.
These MSI-X tables are mapped by a device BAR, and if no Memory Space
has been assigned to the BAR, MSI-X cannot be used.
Fail MSI-X setup if no space has been assigned for the BAR.
Previously, we ioremapped the MSI-X table even if the resource hadn't been
assigned. In this case, the resource address is undefined (and is often
zero), which may lead to warnings or oopses in this path:
pci_enable_msix
msix_capability_init
msix_map_region
ioremap_nocache
The PCI core sets resource flags to zero when it can't assign space for the
resource (see reset_resource()). There are also some cases where it sets
the IORESOURCE_UNSET flag, e.g., pci_reassigndev_resource_alignment(),
pci_assign_resource(), etc. So we must check for both cases.
[bhelgaas: changelog]
Reported-by: Zhang Jukuo <zhangjukuo@huawei.com>
Tested-by: Zhang Jukuo <zhangjukuo@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-01-28 08:52:17 +07:00
|
|
|
unsigned long flags;
|
2009-08-06 09:34:34 +07:00
|
|
|
u8 bir;
|
|
|
|
|
2013-04-18 06:43:40 +07:00
|
|
|
pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
|
|
|
|
&table_offset);
|
2013-04-18 07:10:07 +07:00
|
|
|
bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
|
PCI: Fail MSI-X mappings if there's no space assigned to MSI-X BAR
Unlike MSI, which is configured via registers in the MSI capability in
Configuration Space, MSI-X is configured via tables in Memory Space.
These MSI-X tables are mapped by a device BAR, and if no Memory Space
has been assigned to the BAR, MSI-X cannot be used.
Fail MSI-X setup if no space has been assigned for the BAR.
Previously, we ioremapped the MSI-X table even if the resource hadn't been
assigned. In this case, the resource address is undefined (and is often
zero), which may lead to warnings or oopses in this path:
pci_enable_msix
msix_capability_init
msix_map_region
ioremap_nocache
The PCI core sets resource flags to zero when it can't assign space for the
resource (see reset_resource()). There are also some cases where it sets
the IORESOURCE_UNSET flag, e.g., pci_reassigndev_resource_alignment(),
pci_assign_resource(), etc. So we must check for both cases.
[bhelgaas: changelog]
Reported-by: Zhang Jukuo <zhangjukuo@huawei.com>
Tested-by: Zhang Jukuo <zhangjukuo@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2015-01-28 08:52:17 +07:00
|
|
|
flags = pci_resource_flags(dev, bir);
|
|
|
|
if (!flags || (flags & IORESOURCE_UNSET))
|
|
|
|
return NULL;
|
|
|
|
|
2013-04-18 07:10:07 +07:00
|
|
|
table_offset &= PCI_MSIX_TABLE_OFFSET;
|
2009-08-06 09:34:34 +07:00
|
|
|
phys_addr = pci_resource_start(dev, bir) + table_offset;
|
|
|
|
|
|
|
|
return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
|
|
|
|
}
|
|
|
|
|
2013-04-04 23:54:33 +07:00
|
|
|
static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
|
2016-09-14 21:18:49 +07:00
|
|
|
struct msix_entry *entries, int nvec,
|
|
|
|
bool affinity)
|
2009-08-06 09:35:48 +07:00
|
|
|
{
|
2016-09-14 21:18:49 +07:00
|
|
|
struct cpumask *curmsk, *masks = NULL;
|
2009-08-06 09:35:48 +07:00
|
|
|
struct msi_desc *entry;
|
2016-09-14 21:18:49 +07:00
|
|
|
int ret, i;
|
2016-07-12 16:20:18 +07:00
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
if (affinity) {
|
|
|
|
masks = irq_create_affinity_masks(dev->irq_affinity, nvec);
|
|
|
|
if (!masks)
|
|
|
|
pr_err("Unable to allocate affinity masks, ignoring\n");
|
|
|
|
}
|
2016-07-12 16:20:18 +07:00
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
for (i = 0, curmsk = masks; i < nvec; i++) {
|
|
|
|
entry = alloc_msi_entry(&dev->dev, 1, curmsk);
|
2009-08-06 09:35:48 +07:00
|
|
|
if (!entry) {
|
|
|
|
if (!i)
|
|
|
|
iounmap(base);
|
|
|
|
else
|
|
|
|
free_msi_irqs(dev);
|
|
|
|
/* No enough memory. Don't try again */
|
2016-09-14 21:18:49 +07:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out;
|
2009-08-06 09:35:48 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
entry->msi_attrib.is_msix = 1;
|
|
|
|
entry->msi_attrib.is_64 = 1;
|
2016-07-12 16:20:16 +07:00
|
|
|
if (entries)
|
|
|
|
entry->msi_attrib.entry_nr = entries[i].entry;
|
|
|
|
else
|
|
|
|
entry->msi_attrib.entry_nr = i;
|
2009-08-06 09:35:48 +07:00
|
|
|
entry->msi_attrib.default_irq = dev->irq;
|
|
|
|
entry->mask_base = base;
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
|
2016-09-14 21:18:49 +07:00
|
|
|
if (masks)
|
|
|
|
curmsk++;
|
2009-08-06 09:35:48 +07:00
|
|
|
}
|
2016-09-14 21:18:49 +07:00
|
|
|
ret = 0;
|
|
|
|
out:
|
|
|
|
kfree(masks);
|
2009-08-06 09:35:48 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-06 09:35:10 +07:00
|
|
|
static void msix_program_entries(struct pci_dev *dev,
|
2013-04-04 23:54:33 +07:00
|
|
|
struct msix_entry *entries)
|
2009-08-06 09:35:10 +07:00
|
|
|
{
|
|
|
|
struct msi_desc *entry;
|
|
|
|
int i = 0;
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev) {
|
2016-07-12 16:20:16 +07:00
|
|
|
if (entries)
|
|
|
|
entries[i++].vector = entry->irq;
|
2016-07-12 16:20:15 +07:00
|
|
|
entry->masked = readl(pci_msix_desc_addr(entry) +
|
|
|
|
PCI_MSIX_ENTRY_VECTOR_CTRL);
|
2009-08-06 09:35:10 +07:00
|
|
|
msix_mask_irq(entry, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
/**
|
|
|
|
* msix_capability_init - configure device's MSI-X capability
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
2005-10-24 01:57:38 +07:00
|
|
|
* @entries: pointer to an array of struct msix_entry entries
|
|
|
|
* @nvec: number of @entries
|
2016-10-23 23:32:34 +07:00
|
|
|
* @affinity: flag to indicate cpu irq affinity mask should be set
|
2005-04-17 05:20:36 +07:00
|
|
|
*
|
2005-05-04 07:38:30 +07:00
|
|
|
* Setup the MSI-X capability structure of device function with a
|
2006-10-04 16:16:41 +07:00
|
|
|
* single MSI-X irq. A return of zero indicates the successful setup of
|
|
|
|
* requested MSI-X entries with allocated irqs or non-zero for otherwise.
|
2005-04-17 05:20:36 +07:00
|
|
|
**/
|
2016-09-14 21:18:49 +07:00
|
|
|
static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
|
|
|
|
int nvec, bool affinity)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2013-04-04 23:54:33 +07:00
|
|
|
int ret;
|
2009-08-06 09:34:34 +07:00
|
|
|
u16 control;
|
2005-04-17 05:20:36 +07:00
|
|
|
void __iomem *base;
|
|
|
|
|
2009-06-19 09:15:59 +07:00
|
|
|
/* Ensure MSI-X is disabled while it is set up */
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
2009-06-19 09:15:59 +07:00
|
|
|
|
2014-06-19 15:29:53 +07:00
|
|
|
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
2005-04-17 05:20:36 +07:00
|
|
|
/* Request & Map MSI-X table region */
|
2013-04-18 06:44:48 +07:00
|
|
|
base = msix_map_region(dev, msix_table_size(control));
|
2009-08-06 09:34:34 +07:00
|
|
|
if (!base)
|
2005-04-17 05:20:36 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
ret = msix_setup_entries(dev, base, entries, nvec, affinity);
|
2009-08-06 09:35:48 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 16:39:21 +07:00
|
|
|
|
2014-11-15 21:24:07 +07:00
|
|
|
ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
|
2009-08-06 09:33:39 +07:00
|
|
|
if (ret)
|
2013-12-16 15:34:56 +07:00
|
|
|
goto out_avail;
|
MSI: Give archs the option to allocate all MSI/Xs at once.
This patch introduces an optional function, arch_setup_msi_irqs(),
(note the plural) which gives an arch the opportunity to do per-device
setup for MSI/X and then allocate all the requested MSI/Xs at once.
If that's not required by the arch, the default version simply calls
arch_setup_msi_irq() for each MSI irq required.
arch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list
of msi_descs with irq == 0, it is up to the arch to connect these up to
an irq (via set_irq_msi()) or return an error. For convenience the number
of vectors and the type are passed also.
All msi_descs with irq != 0 are considered allocated, and the arch
teardown routine will be called on them when necessary.
The existing semantics of pci_enable_msix() are that if the requested
number of irqs can not be allocated, the maximum number that _could_ be
allocated is returned. To support that, we define that in case of an
error from arch_setup_msi_irqs(), the number of msi_descs with irq != 0
are considered allocated, and are counted toward the "max that could be
allocated".
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2007-04-18 16:39:21 +07:00
|
|
|
|
2014-10-03 12:13:24 +07:00
|
|
|
/* Check if all MSI entries honor device restrictions */
|
|
|
|
ret = msi_verify_entries(dev);
|
|
|
|
if (ret)
|
|
|
|
goto out_free;
|
|
|
|
|
2009-06-19 09:15:59 +07:00
|
|
|
/*
|
|
|
|
* Some devices require MSI-X to be enabled before we can touch the
|
|
|
|
* MSI-X registers. We need to mask all the vectors to prevent
|
|
|
|
* interrupts coming in before they're fully set up.
|
|
|
|
*/
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msix_clear_and_set_ctrl(dev, 0,
|
2014-06-19 15:29:53 +07:00
|
|
|
PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
|
2009-06-19 09:15:59 +07:00
|
|
|
|
2009-08-06 09:35:10 +07:00
|
|
|
msix_program_entries(dev, entries);
|
2009-06-19 09:15:59 +07:00
|
|
|
|
2011-10-07 01:08:18 +07:00
|
|
|
ret = populate_msi_sysfs(dev);
|
2013-12-16 15:34:56 +07:00
|
|
|
if (ret)
|
|
|
|
goto out_free;
|
2011-10-07 01:08:18 +07:00
|
|
|
|
2009-06-19 09:15:59 +07:00
|
|
|
/* Set MSI-X enabled bits and unmask the function */
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_intx_for_msi(dev, 0);
|
2007-03-05 15:30:10 +07:00
|
|
|
dev->msix_enabled = 1;
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
|
2009-05-08 20:13:33 +07:00
|
|
|
|
2015-07-31 02:00:08 +07:00
|
|
|
pcibios_free_irq(dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
return 0;
|
2009-08-06 09:33:39 +07:00
|
|
|
|
2013-12-16 15:34:56 +07:00
|
|
|
out_avail:
|
2009-08-06 09:33:39 +07:00
|
|
|
if (ret < 0) {
|
|
|
|
/*
|
|
|
|
* If we had some success, report the number of irqs
|
|
|
|
* we succeeded in setting up.
|
|
|
|
*/
|
2009-08-06 09:35:48 +07:00
|
|
|
struct msi_desc *entry;
|
2009-08-06 09:33:39 +07:00
|
|
|
int avail = 0;
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev) {
|
2009-08-06 09:33:39 +07:00
|
|
|
if (entry->irq != 0)
|
|
|
|
avail++;
|
|
|
|
}
|
|
|
|
if (avail != 0)
|
|
|
|
ret = avail;
|
|
|
|
}
|
|
|
|
|
2013-12-16 15:34:56 +07:00
|
|
|
out_free:
|
2009-08-06 09:33:39 +07:00
|
|
|
free_msi_irqs(dev);
|
|
|
|
|
|
|
|
return ret;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
2006-08-31 12:55:07 +07:00
|
|
|
/**
|
2014-09-24 01:45:58 +07:00
|
|
|
* pci_msi_supported - check whether MSI may be enabled on a device
|
2006-08-31 12:55:07 +07:00
|
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
2007-04-05 14:19:08 +07:00
|
|
|
* @nvec: how many MSIs have been requested ?
|
2006-08-31 12:55:07 +07:00
|
|
|
*
|
2013-11-15 01:28:18 +07:00
|
|
|
* Look at global flags, the device itself, and its parent buses
|
2007-04-05 14:19:07 +07:00
|
|
|
* to determine if MSI/-X are supported for the device. If MSI/-X is
|
2014-09-24 01:45:58 +07:00
|
|
|
* supported return 1, else return 0.
|
2006-08-31 12:55:07 +07:00
|
|
|
**/
|
2014-09-24 01:45:58 +07:00
|
|
|
static int pci_msi_supported(struct pci_dev *dev, int nvec)
|
2006-08-31 12:55:07 +07:00
|
|
|
{
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
2006-10-05 15:24:31 +07:00
|
|
|
/* MSI must be globally enabled and supported by the device */
|
2014-09-24 03:25:11 +07:00
|
|
|
if (!pci_msi_enable)
|
2014-09-24 01:45:58 +07:00
|
|
|
return 0;
|
2014-09-24 03:25:11 +07:00
|
|
|
|
|
|
|
if (!dev || dev->no_msi || dev->current_state != PCI_D0)
|
2014-09-24 01:45:58 +07:00
|
|
|
return 0;
|
2006-08-31 12:55:07 +07:00
|
|
|
|
2007-04-05 14:19:12 +07:00
|
|
|
/*
|
|
|
|
* You can't ask to have 0 or less MSIs configured.
|
|
|
|
* a) it's stupid ..
|
|
|
|
* b) the list manipulation code assumes nvec >= 1.
|
|
|
|
*/
|
|
|
|
if (nvec < 1)
|
2014-09-24 01:45:58 +07:00
|
|
|
return 0;
|
2007-04-05 14:19:12 +07:00
|
|
|
|
2009-08-10 08:14:15 +07:00
|
|
|
/*
|
|
|
|
* Any bridge which does NOT route MSI transactions from its
|
|
|
|
* secondary bus to its primary bus must set NO_MSI flag on
|
2006-10-05 15:24:31 +07:00
|
|
|
* the secondary pci_bus.
|
|
|
|
* We expect only arch-specific PCI host bus controller driver
|
|
|
|
* or quirks for specific PCI bridges to be setting NO_MSI.
|
|
|
|
*/
|
2006-08-31 12:55:07 +07:00
|
|
|
for (bus = dev->bus; bus; bus = bus->parent)
|
|
|
|
if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
|
2014-09-24 01:45:58 +07:00
|
|
|
return 0;
|
2006-08-31 12:55:07 +07:00
|
|
|
|
2014-09-24 01:45:58 +07:00
|
|
|
return 1;
|
2006-08-31 12:55:07 +07:00
|
|
|
}
|
|
|
|
|
2013-12-30 14:28:13 +07:00
|
|
|
/**
|
|
|
|
* pci_msi_vec_count - Return the number of MSI vectors a device can send
|
|
|
|
* @dev: device to report about
|
|
|
|
*
|
|
|
|
* This function returns the number of MSI vectors a device requested via
|
|
|
|
* Multiple Message Capable register. It returns a negative errno if the
|
|
|
|
* device is not capable sending MSI interrupts. Otherwise, the call succeeds
|
|
|
|
* and returns a power of two, up to a maximum of 2^5 (32), according to the
|
|
|
|
* MSI specification.
|
|
|
|
**/
|
|
|
|
int pci_msi_vec_count(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
u16 msgctl;
|
|
|
|
|
|
|
|
if (!dev->msi_cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
|
|
|
|
ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_msi_vec_count);
|
|
|
|
|
2009-03-17 19:54:09 +07:00
|
|
|
void pci_msi_shutdown(struct pci_dev *dev)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2009-03-17 19:54:09 +07:00
|
|
|
struct msi_desc *desc;
|
|
|
|
u32 mask;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2007-03-22 17:51:39 +07:00
|
|
|
if (!pci_msi_enable || !dev || !dev->msi_enabled)
|
2007-01-29 02:42:52 +07:00
|
|
|
return;
|
|
|
|
|
2015-07-09 15:00:41 +07:00
|
|
|
BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
|
2015-07-09 15:00:44 +07:00
|
|
|
desc = first_pci_msi_entry(dev);
|
2009-06-16 19:31:45 +07:00
|
|
|
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msi_set_enable(dev, 0);
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_intx_for_msi(dev, 1);
|
2007-03-05 15:30:10 +07:00
|
|
|
dev->msi_enabled = 0;
|
2006-10-04 16:16:31 +07:00
|
|
|
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
/* Return the device with MSI unmasked as initial states */
|
2014-06-19 15:30:30 +07:00
|
|
|
mask = msi_mask(desc->msi_attrib.multi_cap);
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
/* Keep cached state to be restored */
|
2014-11-23 17:55:58 +07:00
|
|
|
__pci_msi_desc_mask_irq(desc, mask, ~mask);
|
2007-03-22 17:51:27 +07:00
|
|
|
|
|
|
|
/* Restore dev->irq to its default pin-assertion irq */
|
2009-03-17 19:54:09 +07:00
|
|
|
dev->irq = desc->msi_attrib.default_irq;
|
2015-07-31 02:00:08 +07:00
|
|
|
pcibios_alloc_irq(dev);
|
2008-04-24 04:58:09 +07:00
|
|
|
}
|
2009-03-17 19:54:06 +07:00
|
|
|
|
2009-08-10 08:14:15 +07:00
|
|
|
void pci_disable_msi(struct pci_dev *dev)
|
2008-04-24 04:58:09 +07:00
|
|
|
{
|
|
|
|
if (!pci_msi_enable || !dev || !dev->msi_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_msi_shutdown(dev);
|
2009-08-06 09:32:51 +07:00
|
|
|
free_msi_irqs(dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2007-03-22 17:51:34 +07:00
|
|
|
EXPORT_SYMBOL(pci_disable_msi);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2009-01-24 06:21:14 +07:00
|
|
|
/**
|
2013-12-30 14:28:15 +07:00
|
|
|
* pci_msix_vec_count - return the number of device's MSI-X table entries
|
2009-01-24 06:21:14 +07:00
|
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
2013-12-30 14:28:15 +07:00
|
|
|
* This function returns the number of device's MSI-X table entries and
|
|
|
|
* therefore the number of MSI-X vectors device is capable of sending.
|
|
|
|
* It returns a negative errno if the device is not capable of sending MSI-X
|
|
|
|
* interrupts.
|
|
|
|
**/
|
|
|
|
int pci_msix_vec_count(struct pci_dev *dev)
|
2009-01-24 06:21:14 +07:00
|
|
|
{
|
|
|
|
u16 control;
|
|
|
|
|
2013-04-04 23:54:33 +07:00
|
|
|
if (!dev->msix_cap)
|
2013-12-30 14:28:15 +07:00
|
|
|
return -EINVAL;
|
2009-01-24 06:21:14 +07:00
|
|
|
|
2013-04-18 06:38:32 +07:00
|
|
|
pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
|
2013-04-18 06:44:48 +07:00
|
|
|
return msix_table_size(control);
|
2009-01-24 06:21:14 +07:00
|
|
|
}
|
2013-12-30 14:28:15 +07:00
|
|
|
EXPORT_SYMBOL(pci_msix_vec_count);
|
2009-01-24 06:21:14 +07:00
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
|
|
|
|
int nvec, bool affinity)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2014-09-24 03:38:28 +07:00
|
|
|
int nr_entries;
|
2007-01-29 02:42:52 +07:00
|
|
|
int i, j;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2014-09-24 01:45:58 +07:00
|
|
|
if (!pci_msi_supported(dev, nvec))
|
|
|
|
return -EINVAL;
|
2007-04-05 14:19:08 +07:00
|
|
|
|
2013-12-30 14:28:15 +07:00
|
|
|
nr_entries = pci_msix_vec_count(dev);
|
|
|
|
if (nr_entries < 0)
|
|
|
|
return nr_entries;
|
2005-04-17 05:20:36 +07:00
|
|
|
if (nvec > nr_entries)
|
2009-05-07 15:28:41 +07:00
|
|
|
return nr_entries;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2016-07-12 16:20:16 +07:00
|
|
|
if (entries) {
|
|
|
|
/* Check for any invalid entries */
|
|
|
|
for (i = 0; i < nvec; i++) {
|
|
|
|
if (entries[i].entry >= nr_entries)
|
|
|
|
return -EINVAL; /* invalid entry */
|
|
|
|
for (j = i + 1; j < nvec; j++) {
|
|
|
|
if (entries[i].entry == entries[j].entry)
|
|
|
|
return -EINVAL; /* duplicate entry */
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
}
|
2007-01-29 02:42:52 +07:00
|
|
|
WARN_ON(!!dev->msix_enabled);
|
2006-10-04 16:16:31 +07:00
|
|
|
|
2006-10-04 16:16:41 +07:00
|
|
|
/* Check whether driver already requested for MSI irq */
|
2009-08-10 08:14:15 +07:00
|
|
|
if (dev->msi_enabled) {
|
2014-04-19 07:13:50 +07:00
|
|
|
dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
|
2005-04-17 05:20:36 +07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2016-09-14 21:18:49 +07:00
|
|
|
return msix_capability_init(dev, entries, nvec, affinity);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_msix - configure device's MSI-X capability structure
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
|
|
* @entries: pointer to an array of MSI-X entries (optional)
|
|
|
|
* @nvec: number of MSI-X irqs requested for allocation by device driver
|
|
|
|
*
|
|
|
|
* Setup the MSI-X capability structure of device function with the number
|
|
|
|
* of requested irqs upon its software driver call to request for
|
|
|
|
* MSI-X mode enabled on its hardware device function. A return of zero
|
|
|
|
* indicates the successful configuration of MSI-X capability structure
|
|
|
|
* with new allocated MSI-X irqs. A return of < 0 indicates a failure.
|
|
|
|
* Or a return of > 0 indicates that driver request is exceeding the number
|
|
|
|
* of irqs or MSI-X vectors available. Driver should use the returned value to
|
|
|
|
* re-send its request.
|
|
|
|
**/
|
|
|
|
int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
|
|
|
|
{
|
|
|
|
return __pci_enable_msix(dev, entries, nvec, false);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2007-03-22 17:51:34 +07:00
|
|
|
EXPORT_SYMBOL(pci_enable_msix);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2009-08-10 08:14:15 +07:00
|
|
|
void pci_msix_shutdown(struct pci_dev *dev)
|
2007-03-22 17:51:33 +07:00
|
|
|
{
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
struct msi_desc *entry;
|
|
|
|
|
2007-03-22 17:51:39 +07:00
|
|
|
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
2007-01-29 02:42:52 +07:00
|
|
|
return;
|
|
|
|
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
/* Return the device with MSI-X masked as initial states */
|
2015-07-09 15:00:41 +07:00
|
|
|
for_each_pci_msi_entry(entry, dev) {
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
/* Keep cached states to be restored */
|
2014-11-23 17:55:58 +07:00
|
|
|
__pci_msix_desc_mask_irq(entry, 1);
|
PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume
There are 2 problems on mask states in suspend/resume.
[1]:
It is better to restore the mask states of MSI/MSI-X to initial states
(MSI is unmasked, MSI-X is masked) when we release the device.
The pci_msi_shutdown() does the restoration of mask states for MSI,
while the msi_free_irqs() does it for MSI-X. In other words, in the
"disable" path both of MSI and MSI-X are handled, but in the "shutdown"
path only MSI is handled.
MSI:
pci_disable_msi()
=> pci_msi_shutdown()
[ mask states for MSI restored ]
=> msi_set_enable(dev, pos, 0);
=> msi_free_irqs()
MSI-X:
pci_disable_msix()
=> pci_msix_shutdown()
=> msix_set_enable(dev, 0);
=> msix_free_all_irqs
=> msi_free_irqs()
[ mask states for MSI-X restored ]
This patch moves the masking for MSI-X from msi_free_irqs() to
pci_msix_shutdown().
This change has some positive side effects:
- It prevents OS from touching mask states before reading preserved
bits in the register, which can be happen if msi_free_irqs() is
called from error path in msix_capability_init().
- It also prevents touching the register after turning off MSI-X in
"disable" path, which can be a problem on some devices.
[2]:
We have cache of the mask state in msi_desc, which is automatically
updated when msi/msix_mask_irq() is called. This cached states are
used for the resume.
But since what need to be restored in the resume is the states before
the shutdown on the suspend, calling msi/msix_mask_irq() from
pci_msi/msix_shutdown() is not appropriate.
This patch introduces __msi/msix_mask_irq() that do mask as same
as msi/msix_mask_irq() but does not update cached state, for use
in pci_msi/msix_shutdown().
[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-24 10:08:09 +07:00
|
|
|
}
|
|
|
|
|
2015-05-07 21:52:21 +07:00
|
|
|
pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
|
2007-10-25 15:16:30 +07:00
|
|
|
pci_intx_for_msi(dev, 1);
|
2007-03-05 15:30:10 +07:00
|
|
|
dev->msix_enabled = 0;
|
2015-07-31 02:00:08 +07:00
|
|
|
pcibios_alloc_irq(dev);
|
2008-04-24 04:58:09 +07:00
|
|
|
}
|
2009-08-06 09:31:27 +07:00
|
|
|
|
2009-08-10 08:14:15 +07:00
|
|
|
void pci_disable_msix(struct pci_dev *dev)
|
2008-04-24 04:58:09 +07:00
|
|
|
{
|
|
|
|
if (!pci_msi_enable || !dev || !dev->msix_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pci_msix_shutdown(dev);
|
2009-08-06 09:32:51 +07:00
|
|
|
free_msi_irqs(dev);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
2007-03-22 17:51:34 +07:00
|
|
|
EXPORT_SYMBOL(pci_disable_msix);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2006-03-06 12:33:34 +07:00
|
|
|
void pci_no_msi(void)
|
|
|
|
{
|
|
|
|
pci_msi_enable = 0;
|
|
|
|
}
|
2007-04-05 14:19:08 +07:00
|
|
|
|
2008-11-11 05:31:05 +07:00
|
|
|
/**
|
|
|
|
* pci_msi_enabled - is MSI enabled?
|
|
|
|
*
|
|
|
|
* Returns true if MSI has not been disabled by the command-line option
|
|
|
|
* pci=nomsi.
|
|
|
|
**/
|
|
|
|
int pci_msi_enabled(void)
|
2008-10-17 11:52:51 +07:00
|
|
|
{
|
2008-11-11 05:31:05 +07:00
|
|
|
return pci_msi_enable;
|
2008-10-17 11:52:51 +07:00
|
|
|
}
|
2008-11-11 05:31:05 +07:00
|
|
|
EXPORT_SYMBOL(pci_msi_enabled);
|
2008-10-17 11:52:51 +07:00
|
|
|
|
2016-07-12 16:20:18 +07:00
|
|
|
static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
|
|
|
|
unsigned int flags)
|
2013-12-30 14:28:16 +07:00
|
|
|
{
|
2016-09-14 21:18:49 +07:00
|
|
|
bool affinity = flags & PCI_IRQ_AFFINITY;
|
2014-04-14 20:28:35 +07:00
|
|
|
int nvec;
|
2013-12-30 14:28:16 +07:00
|
|
|
int rc;
|
|
|
|
|
2014-09-24 01:45:58 +07:00
|
|
|
if (!pci_msi_supported(dev, minvec))
|
|
|
|
return -EINVAL;
|
2014-04-14 20:28:35 +07:00
|
|
|
|
|
|
|
WARN_ON(!!dev->msi_enabled);
|
|
|
|
|
|
|
|
/* Check whether driver already requested MSI-X irqs */
|
|
|
|
if (dev->msix_enabled) {
|
|
|
|
dev_info(&dev->dev,
|
|
|
|
"can't enable MSI (MSI-X already enabled)\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-12-30 14:28:16 +07:00
|
|
|
if (maxvec < minvec)
|
|
|
|
return -ERANGE;
|
|
|
|
|
2014-04-14 20:28:35 +07:00
|
|
|
nvec = pci_msi_vec_count(dev);
|
|
|
|
if (nvec < 0)
|
|
|
|
return nvec;
|
2016-07-12 16:20:18 +07:00
|
|
|
if (nvec < minvec)
|
2014-04-14 20:28:35 +07:00
|
|
|
return -EINVAL;
|
2016-07-12 16:20:18 +07:00
|
|
|
|
|
|
|
if (nvec > maxvec)
|
2014-04-14 20:28:35 +07:00
|
|
|
nvec = maxvec;
|
|
|
|
|
2016-07-12 16:20:18 +07:00
|
|
|
for (;;) {
|
2016-09-14 21:18:49 +07:00
|
|
|
if (affinity) {
|
|
|
|
nvec = irq_calc_affinity_vectors(dev->irq_affinity,
|
|
|
|
nvec);
|
2016-07-12 16:20:18 +07:00
|
|
|
if (nvec < minvec)
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
rc = msi_capability_init(dev, nvec, affinity);
|
2016-07-12 16:20:18 +07:00
|
|
|
if (rc == 0)
|
|
|
|
return nvec;
|
|
|
|
|
|
|
|
if (rc < 0)
|
2013-12-30 14:28:16 +07:00
|
|
|
return rc;
|
2016-07-12 16:20:18 +07:00
|
|
|
if (rc < minvec)
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
nvec = rc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_msi_range - configure device's MSI capability structure
|
|
|
|
* @dev: device to configure
|
|
|
|
* @minvec: minimal number of interrupts to configure
|
|
|
|
* @maxvec: maximum number of interrupts to configure
|
|
|
|
*
|
|
|
|
* This function tries to allocate a maximum possible number of interrupts in a
|
|
|
|
* range between @minvec and @maxvec. It returns a negative errno if an error
|
|
|
|
* occurs. If it succeeds, it returns the actual number of interrupts allocated
|
|
|
|
* and updates the @dev's irq member to the lowest new interrupt number;
|
|
|
|
* the other interrupt numbers allocated to this device are consecutive.
|
|
|
|
**/
|
|
|
|
int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
|
|
|
|
{
|
2016-08-11 21:11:04 +07:00
|
|
|
return __pci_enable_msi_range(dev, minvec, maxvec, 0);
|
2016-07-12 16:20:18 +07:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_enable_msi_range);
|
|
|
|
|
|
|
|
static int __pci_enable_msix_range(struct pci_dev *dev,
|
|
|
|
struct msix_entry *entries, int minvec, int maxvec,
|
|
|
|
unsigned int flags)
|
|
|
|
{
|
2016-09-14 21:18:49 +07:00
|
|
|
bool affinity = flags & PCI_IRQ_AFFINITY;
|
|
|
|
int rc, nvec = maxvec;
|
2016-07-12 16:20:18 +07:00
|
|
|
|
|
|
|
if (maxvec < minvec)
|
|
|
|
return -ERANGE;
|
|
|
|
|
|
|
|
for (;;) {
|
2016-09-14 21:18:49 +07:00
|
|
|
if (affinity) {
|
|
|
|
nvec = irq_calc_affinity_vectors(dev->irq_affinity,
|
|
|
|
nvec);
|
2016-07-12 16:20:18 +07:00
|
|
|
if (nvec < minvec)
|
2013-12-30 14:28:16 +07:00
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
|
2016-09-14 21:18:49 +07:00
|
|
|
rc = __pci_enable_msix(dev, entries, nvec, affinity);
|
2016-07-12 16:20:18 +07:00
|
|
|
if (rc == 0)
|
|
|
|
return nvec;
|
|
|
|
|
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
|
|
|
if (rc < minvec)
|
|
|
|
return -ENOSPC;
|
|
|
|
|
|
|
|
nvec = rc;
|
|
|
|
}
|
2013-12-30 14:28:16 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_msix_range - configure device's MSI-X capability structure
|
|
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
|
|
* @entries: pointer to an array of MSI-X entries
|
|
|
|
* @minvec: minimum number of MSI-X irqs requested
|
|
|
|
* @maxvec: maximum number of MSI-X irqs requested
|
|
|
|
*
|
|
|
|
* Setup the MSI-X capability structure of device function with a maximum
|
|
|
|
* possible number of interrupts in the range between @minvec and @maxvec
|
|
|
|
* upon its software driver call to request for MSI-X mode enabled on its
|
|
|
|
* hardware device function. It returns a negative errno if an error occurs.
|
|
|
|
* If it succeeds, it returns the actual number of interrupts allocated and
|
|
|
|
* indicates the successful configuration of MSI-X capability structure
|
|
|
|
* with new allocated MSI-X interrupts.
|
|
|
|
**/
|
|
|
|
int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
|
2016-07-12 16:20:18 +07:00
|
|
|
int minvec, int maxvec)
|
2013-12-30 14:28:16 +07:00
|
|
|
{
|
2016-08-11 21:11:04 +07:00
|
|
|
return __pci_enable_msix_range(dev, entries, minvec, maxvec, 0);
|
2013-12-30 14:28:16 +07:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_enable_msix_range);
|
2014-11-11 20:02:18 +07:00
|
|
|
|
2016-07-12 16:20:17 +07:00
|
|
|
/**
|
|
|
|
* pci_alloc_irq_vectors - allocate multiple IRQs for a device
|
|
|
|
* @dev: PCI device to operate on
|
|
|
|
* @min_vecs: minimum number of vectors required (must be >= 1)
|
|
|
|
* @max_vecs: maximum (desired) number of vectors
|
|
|
|
* @flags: flags or quirks for the allocation
|
|
|
|
*
|
|
|
|
* Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
|
|
|
|
* vectors if available, and fall back to a single legacy vector
|
|
|
|
* if neither is available. Return the number of vectors allocated,
|
|
|
|
* (which might be smaller than @max_vecs) if successful, or a negative
|
|
|
|
* error code on error. If less than @min_vecs interrupt vectors are
|
|
|
|
* available for @dev the function will fail with -ENOSPC.
|
|
|
|
*
|
|
|
|
* To get the Linux IRQ number used for a vector that can be passed to
|
|
|
|
* request_irq() use the pci_irq_vector() helper.
|
|
|
|
*/
|
|
|
|
int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
|
|
|
|
unsigned int max_vecs, unsigned int flags)
|
|
|
|
{
|
|
|
|
int vecs = -ENOSPC;
|
|
|
|
|
2016-08-11 21:11:04 +07:00
|
|
|
if (flags & PCI_IRQ_MSIX) {
|
2016-07-12 16:20:18 +07:00
|
|
|
vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
|
|
|
|
flags);
|
2016-07-12 16:20:17 +07:00
|
|
|
if (vecs > 0)
|
|
|
|
return vecs;
|
|
|
|
}
|
|
|
|
|
2016-08-11 21:11:04 +07:00
|
|
|
if (flags & PCI_IRQ_MSI) {
|
2016-07-12 16:20:18 +07:00
|
|
|
vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, flags);
|
2016-07-12 16:20:17 +07:00
|
|
|
if (vecs > 0)
|
|
|
|
return vecs;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* use legacy irq if allowed */
|
2016-08-11 21:11:05 +07:00
|
|
|
if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1) {
|
|
|
|
pci_intx(dev, 1);
|
2016-07-12 16:20:17 +07:00
|
|
|
return 1;
|
2016-08-11 21:11:05 +07:00
|
|
|
}
|
|
|
|
|
2016-07-12 16:20:17 +07:00
|
|
|
return vecs;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_alloc_irq_vectors);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_free_irq_vectors - free previously allocated IRQs for a device
|
|
|
|
* @dev: PCI device to operate on
|
|
|
|
*
|
|
|
|
* Undoes the allocations and enabling in pci_alloc_irq_vectors().
|
|
|
|
*/
|
|
|
|
void pci_free_irq_vectors(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
pci_disable_msix(dev);
|
|
|
|
pci_disable_msi(dev);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_free_irq_vectors);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_irq_vector - return Linux IRQ number of a device vector
|
|
|
|
* @dev: PCI device to operate on
|
|
|
|
* @nr: device-relative interrupt vector index (0-based).
|
|
|
|
*/
|
|
|
|
int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
|
|
|
|
{
|
|
|
|
if (dev->msix_enabled) {
|
|
|
|
struct msi_desc *entry;
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
for_each_pci_msi_entry(entry, dev) {
|
|
|
|
if (i == nr)
|
|
|
|
return entry->irq;
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->msi_enabled) {
|
|
|
|
struct msi_desc *entry = first_pci_msi_entry(dev);
|
|
|
|
|
|
|
|
if (WARN_ON_ONCE(nr >= entry->nvec_used))
|
|
|
|
return -EINVAL;
|
|
|
|
} else {
|
|
|
|
if (WARN_ON_ONCE(nr > 0))
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dev->irq + nr;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_irq_vector);
|
|
|
|
|
2016-09-14 21:18:51 +07:00
|
|
|
/**
|
|
|
|
* pci_irq_get_affinity - return the affinity of a particular msi vector
|
|
|
|
* @dev: PCI device to operate on
|
|
|
|
* @nr: device-relative interrupt vector index (0-based).
|
|
|
|
*/
|
|
|
|
const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
|
|
|
|
{
|
|
|
|
if (dev->msix_enabled) {
|
|
|
|
struct msi_desc *entry;
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
for_each_pci_msi_entry(entry, dev) {
|
|
|
|
if (i == nr)
|
|
|
|
return entry->affinity;
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
return NULL;
|
|
|
|
} else if (dev->msi_enabled) {
|
|
|
|
struct msi_desc *entry = first_pci_msi_entry(dev);
|
|
|
|
|
|
|
|
if (WARN_ON_ONCE(!entry || nr >= entry->nvec_used))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return &entry->affinity[nr];
|
|
|
|
} else {
|
|
|
|
return cpu_possible_mask;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_irq_get_affinity);
|
|
|
|
|
2015-07-09 15:00:45 +07:00
|
|
|
struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
return to_pci_dev(desc->dev);
|
|
|
|
}
|
2015-12-11 00:52:59 +07:00
|
|
|
EXPORT_SYMBOL(msi_desc_to_pci_dev);
|
2015-07-09 15:00:45 +07:00
|
|
|
|
2015-07-09 15:00:36 +07:00
|
|
|
void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev = msi_desc_to_pci_dev(desc);
|
|
|
|
|
|
|
|
return dev->bus->sysdata;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
|
|
|
|
|
2014-11-11 20:02:18 +07:00
|
|
|
#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
|
|
|
|
/**
|
|
|
|
* pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
|
|
|
|
* @irq_data: Pointer to interrupt data of the MSI interrupt
|
|
|
|
* @msg: Pointer to the message
|
|
|
|
*/
|
|
|
|
void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
|
|
|
|
{
|
2015-06-01 15:05:42 +07:00
|
|
|
struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
|
2014-11-11 20:02:18 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For MSI-X desc->irq is always equal to irq_data->irq. For
|
|
|
|
* MSI only the first interrupt of MULTI MSI passes the test.
|
|
|
|
*/
|
|
|
|
if (desc->irq == irq_data->irq)
|
|
|
|
__pci_write_msi_msg(desc, msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
|
|
|
|
* @dev: Pointer to the PCI device
|
|
|
|
* @desc: Pointer to the msi descriptor
|
|
|
|
*
|
|
|
|
* The ID number is only used within the irqdomain.
|
|
|
|
*/
|
|
|
|
irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
|
|
|
|
struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
return (irq_hw_number_t)desc->msi_attrib.entry_nr |
|
|
|
|
PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
|
|
|
|
(pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
|
|
|
|
* @domain: The interrupt domain to check
|
|
|
|
* @info: The domain info for verification
|
|
|
|
* @dev: The device to check
|
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* 0 if the functionality is supported
|
|
|
|
* 1 if Multi MSI is requested, but the domain does not support it
|
|
|
|
* -ENOTSUPP otherwise
|
|
|
|
*/
|
|
|
|
int pci_msi_domain_check_cap(struct irq_domain *domain,
|
|
|
|
struct msi_domain_info *info, struct device *dev)
|
|
|
|
{
|
|
|
|
struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
|
|
|
|
|
|
|
|
/* Special handling to support pci_enable_msi_range() */
|
|
|
|
if (pci_msi_desc_is_multi_msi(desc) &&
|
|
|
|
!(info->flags & MSI_FLAG_MULTI_PCI_MSI))
|
|
|
|
return 1;
|
|
|
|
else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_msi_domain_handle_error(struct irq_domain *domain,
|
|
|
|
struct msi_desc *desc, int error)
|
|
|
|
{
|
|
|
|
/* Special handling to support pci_enable_msi_range() */
|
|
|
|
if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef GENERIC_MSI_DOMAIN_OPS
|
|
|
|
static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
|
|
|
|
struct msi_desc *desc)
|
|
|
|
{
|
|
|
|
arg->desc = desc;
|
|
|
|
arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
|
|
|
|
desc);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define pci_msi_domain_set_desc NULL
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct msi_domain_ops pci_msi_domain_ops_default = {
|
|
|
|
.set_desc = pci_msi_domain_set_desc,
|
|
|
|
.msi_check = pci_msi_domain_check_cap,
|
|
|
|
.handle_error = pci_msi_domain_handle_error,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
|
|
|
|
{
|
|
|
|
struct msi_domain_ops *ops = info->ops;
|
|
|
|
|
|
|
|
if (ops == NULL) {
|
|
|
|
info->ops = &pci_msi_domain_ops_default;
|
|
|
|
} else {
|
|
|
|
if (ops->set_desc == NULL)
|
|
|
|
ops->set_desc = pci_msi_domain_set_desc;
|
|
|
|
if (ops->msi_check == NULL)
|
|
|
|
ops->msi_check = pci_msi_domain_check_cap;
|
|
|
|
if (ops->handle_error == NULL)
|
|
|
|
ops->handle_error = pci_msi_domain_handle_error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
|
|
|
|
{
|
|
|
|
struct irq_chip *chip = info->chip;
|
|
|
|
|
|
|
|
BUG_ON(!chip);
|
|
|
|
if (!chip->irq_write_msi_msg)
|
|
|
|
chip->irq_write_msi_msg = pci_msi_domain_write_msg;
|
2015-10-14 01:14:45 +07:00
|
|
|
if (!chip->irq_mask)
|
|
|
|
chip->irq_mask = pci_msi_mask_irq;
|
|
|
|
if (!chip->irq_unmask)
|
|
|
|
chip->irq_unmask = pci_msi_unmask_irq;
|
2014-11-11 20:02:18 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-10-13 18:51:44 +07:00
|
|
|
* pci_msi_create_irq_domain - Create a MSI interrupt domain
|
|
|
|
* @fwnode: Optional fwnode of the interrupt controller
|
2014-11-11 20:02:18 +07:00
|
|
|
* @info: MSI domain info
|
|
|
|
* @parent: Parent irq domain
|
|
|
|
*
|
|
|
|
* Updates the domain and chip ops and creates a MSI interrupt domain.
|
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* A domain pointer or NULL in case of failure.
|
|
|
|
*/
|
2015-10-13 18:51:44 +07:00
|
|
|
struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
|
2014-11-11 20:02:18 +07:00
|
|
|
struct msi_domain_info *info,
|
|
|
|
struct irq_domain *parent)
|
|
|
|
{
|
2015-07-28 20:46:09 +07:00
|
|
|
struct irq_domain *domain;
|
|
|
|
|
2014-11-11 20:02:18 +07:00
|
|
|
if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
|
|
|
|
pci_msi_domain_update_dom_ops(info);
|
|
|
|
if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
|
|
|
|
pci_msi_domain_update_chip_ops(info);
|
|
|
|
|
2016-07-13 23:18:33 +07:00
|
|
|
info->flags |= MSI_FLAG_ACTIVATE_EARLY;
|
|
|
|
|
2015-10-13 18:51:44 +07:00
|
|
|
domain = msi_create_irq_domain(fwnode, info, parent);
|
2015-07-28 20:46:09 +07:00
|
|
|
if (!domain)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
domain->bus_token = DOMAIN_BUS_PCI_MSI;
|
|
|
|
return domain;
|
2014-11-11 20:02:18 +07:00
|
|
|
}
|
2015-12-11 00:52:59 +07:00
|
|
|
EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
|
2014-11-11 20:02:18 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
|
|
|
|
* @domain: The interrupt domain to allocate from
|
|
|
|
* @dev: The device for which to allocate
|
|
|
|
* @nvec: The number of interrupts to allocate
|
|
|
|
* @type: Unused to allow simpler migration from the arch_XXX interfaces
|
|
|
|
*
|
|
|
|
* Returns:
|
|
|
|
* A virtual interrupt number or an error code in case of failure
|
|
|
|
*/
|
|
|
|
int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
|
|
|
|
int nvec, int type)
|
|
|
|
{
|
|
|
|
return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
|
|
|
|
* @domain: The interrupt domain
|
|
|
|
* @dev: The device for which to free interrupts
|
|
|
|
*/
|
|
|
|
void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
msi_domain_free_irqs(domain, &dev->dev);
|
|
|
|
}
|
2014-11-15 21:24:07 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
|
2015-10-13 18:51:44 +07:00
|
|
|
* @fwnode: Optional fwnode of the interrupt controller
|
2014-11-15 21:24:07 +07:00
|
|
|
* @info: MSI domain info
|
|
|
|
* @parent: Parent irq domain
|
|
|
|
*
|
|
|
|
* Returns: A domain pointer or NULL in case of failure. If successful
|
|
|
|
* the default PCI/MSI irqdomain pointer is updated.
|
|
|
|
*/
|
2015-10-13 18:51:44 +07:00
|
|
|
struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
|
2014-11-15 21:24:07 +07:00
|
|
|
struct msi_domain_info *info, struct irq_domain *parent)
|
|
|
|
{
|
|
|
|
struct irq_domain *domain;
|
|
|
|
|
|
|
|
mutex_lock(&pci_msi_domain_lock);
|
|
|
|
if (pci_msi_default_domain) {
|
|
|
|
pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
|
|
|
|
domain = NULL;
|
|
|
|
} else {
|
2015-10-13 18:51:44 +07:00
|
|
|
domain = pci_msi_create_irq_domain(fwnode, info, parent);
|
2014-11-15 21:24:07 +07:00
|
|
|
pci_msi_default_domain = domain;
|
|
|
|
}
|
|
|
|
mutex_unlock(&pci_msi_domain_lock);
|
|
|
|
|
|
|
|
return domain;
|
|
|
|
}
|
2015-10-09 05:10:49 +07:00
|
|
|
|
|
|
|
static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
|
|
|
|
{
|
|
|
|
u32 *pa = data;
|
|
|
|
|
|
|
|
*pa = alias;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
/**
|
|
|
|
* pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
|
|
|
|
* @domain: The interrupt domain
|
|
|
|
* @pdev: The PCI device.
|
|
|
|
*
|
|
|
|
* The RID for a device is formed from the alias, with a firmware
|
|
|
|
* supplied mapping applied
|
|
|
|
*
|
|
|
|
* Returns: The RID.
|
|
|
|
*/
|
|
|
|
u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *of_node;
|
|
|
|
u32 rid = 0;
|
|
|
|
|
|
|
|
pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
|
|
|
|
|
|
|
|
of_node = irq_domain_get_of_node(domain);
|
2016-09-13 01:32:22 +07:00
|
|
|
rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
|
|
|
|
iort_msi_map_rid(&pdev->dev, rid);
|
2015-10-09 05:10:49 +07:00
|
|
|
|
|
|
|
return rid;
|
|
|
|
}
|
2015-10-02 20:43:06 +07:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_msi_get_device_domain - Get the MSI domain for a given PCI device
|
|
|
|
* @pdev: The PCI device
|
|
|
|
*
|
|
|
|
* Use the firmware data to find a device-specific MSI domain
|
|
|
|
* (i.e. not one that is ste as a default).
|
|
|
|
*
|
|
|
|
* Returns: The coresponding MSI domain or NULL if none has been found.
|
|
|
|
*/
|
|
|
|
struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
|
|
|
|
{
|
2016-09-13 01:32:22 +07:00
|
|
|
struct irq_domain *dom;
|
2015-10-02 20:43:06 +07:00
|
|
|
u32 rid = 0;
|
|
|
|
|
|
|
|
pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
|
2016-09-13 01:32:22 +07:00
|
|
|
dom = of_msi_map_get_device_domain(&pdev->dev, rid);
|
|
|
|
if (!dom)
|
|
|
|
dom = iort_get_device_domain(&pdev->dev, rid);
|
|
|
|
return dom;
|
2015-10-02 20:43:06 +07:00
|
|
|
}
|
2014-11-11 20:02:18 +07:00
|
|
|
#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
|