linux_dsm_epyc7002/include/dt-bindings/interrupt-controller/mips-gic.h

#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H

#include <dt-bindings/interrupt-controller/irq.h>

#define GIC_SHARED 0
#define GIC_LOCAL 1

#endif
of: Add binding document for MIPS GIC The Global Interrupt Controller (GIC) present on certain MIPS systems can be used to route external interrupts to individual VPEs and CPU interrupt vectors. It also supports a timer and software-generated interrupts. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8420/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2014-11-13 02:43:37 +07:00			`#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H`
			`#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H`

			`#include <dt-bindings/interrupt-controller/irq.h>`

			`#define GIC_SHARED 0`
			`#define GIC_LOCAL 1`

			`#endif`