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linux_dsm_epyc7002/arch/arm/boot/dts/imx6dl.dtsi

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ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
ARM: dts: add dtsi for imx6q and imx6dl Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-04 22:09:16 +07:00
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
ARM: imx: use #include for all device trees Replace /include/ (dtc) with #include (C pre-processor) for all imx DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as pinctrl settings. Use of those features will increase the readability of the device tree files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-07 09:49:34 +07:00
#include "imx6qdl.dtsi"
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
#include "imx6dl-pinfunc.h"
ARM: dts: add dtsi for imx6q and imx6dl Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-04 22:09:16 +07:00
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
ARM: dts: imx: cpus/cpu nodes dts updates This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-19 00:34:06 +07:00
device_type = "cpu";
ARM: dts: add dtsi for imx6q and imx6dl Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-04 22:09:16 +07:00
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
ARM: dts: imx: cpus/cpu nodes dts updates This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-19 00:34:06 +07:00
device_type = "cpu";
ARM: dts: add dtsi for imx6q and imx6dl Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-04 22:09:16 +07:00
reg = <1>;
next-level-cache = <&L2>;
};
};
soc {
aips1: aips-bus@02000000 {
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
reg = <0x020e0000 0x4000>;
ARM: dtsi: imx6dl: Add a pinctrl for AUDMUX Add a pinctrl for AUDMUX used on imx6dl-sabresd. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-13 18:50:59 +07:00
audmux {
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
};
ARM: dts: imx6dl: add a pinctrl for eCSPI1 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-09 10:29:00 +07:00
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
ARM: dts: imx6dl: add a new pinctrl for ecspi1 This new pinctrl is used in the imx6dl-sabresd board. Signed-off-by: Huang Shijie <b32955@freescale.com>
2013-06-21 09:19:09 +07:00
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
>;
};
ARM: dts: imx6dl: add a pinctrl for eCSPI1 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-09 10:29:00 +07:00
};
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
ARM: dts: imx: add initial imx6dl-sabreauto support Add initial imx6dl-sabreauto support based on the common stuff already in imx6qdl-sabreauto.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:38:11 +07:00
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
};
ARM: dts: imx6dl: add pinctrl for gpmi-nand add the pinctrl item for gpmi-nand. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-07 14:39:19 +07:00
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1 Add a pinctrl for I2C1 used on imx6q/dl-sabresd. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-13 18:50:58 +07:00
i2c1 {
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
ARM: dts: imx: add initial imx6dl-sabreauto support Add initial imx6dl-sabreauto support based on the common stuff already in imx6qdl-sabreauto.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:38:11 +07:00
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
usbotg {
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
ARM: dts: Add initial support for Wandboard Dual-Lite Wandboard is a development board that has two variants: one version based on mx6 dual lite and another one based on mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-03 19:29:16 +07:00
pinctrl_usdhc3_2: usdhc3grp_2 {
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
};
ARM: dts: imx6dl: add pinctrls for WEIM NOR Add two pinctrls for WEIM: one for the weim nor, another for the chipselect. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-05-28 13:20:11 +07:00
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
/* data */
MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
/* address */
MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
ARM: dts: imx: add initial imx6dl-sabresd support Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-04-02 13:04:45 +07:00
};
ARM: dts: add dtsi for imx6q and imx6dl Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-02-04 22:09:16 +07:00
pxp: pxp@020f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
};
epdc: epdc@020f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
};
};
aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
status = "disabled";
};
};
};
};
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