2005-04-17 05:20:36 +07:00
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AMD64 specific boot options
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There are many others (usually documented in driver documentation), but
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only the AMD64 specific ones are listed here.
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Machine check
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2009-05-28 02:56:56 +07:00
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Please see Documentation/x86/x86_64/machinecheck for sysfs runtime tunables.
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2009-06-11 14:06:07 +07:00
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mce=off
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Disable machine check
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mce=no_cmci
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Disable CMCI(Corrected Machine Check Interrupt) that
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Intel processor supports. Usually this disablement is
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not recommended, but it might be handy if your hardware
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is misbehaving.
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Note that you'll get more problems without CMCI than with
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due to the shared banks, i.e. you might get duplicated
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error logs.
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mce=dont_log_ce
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Don't make logs for corrected errors. All events reported
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as corrected are silently cleared by OS.
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This option will be useful if you have no interest in any
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of corrected errors.
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mce=ignore_ce
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Disable features for corrected errors, e.g. polling timer
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and CMCI. All events reported as corrected are not cleared
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by OS and remained in its error banks.
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Usually this disablement is not recommended, however if
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there is an agent checking/clearing corrected errors
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(e.g. BIOS or hardware monitoring applications), conflicting
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with OS's error handling, and you cannot deactivate the agent,
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then this option will be a help.
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2015-06-04 23:55:23 +07:00
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mce=no_lmce
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Do not opt-in to Local MCE delivery. Use legacy method
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to broadcast MCEs.
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2009-06-11 14:06:07 +07:00
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mce=bootlog
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Enable logging of machine checks left over from booting.
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Disabled by default on AMD because some BIOS leave bogus ones.
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If your BIOS doesn't do that it's a good idea to enable though
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to make sure you log even machine check events that result
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in a reboot. On Intel systems it is enabled by default.
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2005-11-05 23:25:54 +07:00
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mce=nobootlog
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Disable boot machine check logging.
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2009-05-28 02:56:55 +07:00
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mce=tolerancelevel[,monarchtimeout] (number,number)
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tolerance levels:
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x86_64: mcelog tolerant level cleanup
Background:
The MCE handler has several paths that it can take, depending on various
conditions of the MCE status and the value of the 'tolerant' knob. The
exact semantics are not well defined and the code is a bit twisty.
Description:
This patch makes the MCE handler's behavior more clear by documenting the
behavior for various 'tolerant' levels. It also fixes or enhances
several small things in the handler. Specifically:
* If RIPV is set it is not safe to restart, so set the 'no way out'
flag rather than the 'kill it' flag.
* Don't panic() on correctable MCEs.
* If the _OVER bit is set *and* the _UC bit is set (meaning possibly
dropped uncorrected errors), set the 'no way out' flag.
* Use EIPV for testing whether an app can be killed (SIGBUS) rather
than RIPV. According to docs, EIPV indicates that the error is
related to the IP, while RIPV simply means the IP is valid to
restart from.
* Don't clear the MCi_STATUS registers until after the panic() path.
This leaves the status bits set after the panic() so clever BIOSes
can find them (and dumb BIOSes can do nothing).
This patch also calls nonseekable_open() in mce_open (as suggested by akpm).
Result:
Tolerant levels behave almost identically to how they always have, but
not it's well defined. There's a slightly higher chance of panic()ing
when multiple errors happen (a good thing, IMHO). If you take an MBE and
panic(), the error status bits are not cleared.
Alternatives:
None.
Testing:
I used software to inject correctable and uncorrectable errors. With
tolerant = 3, the system usually survives. With tolerant = 2, the system
usually panic()s (PCC) but not always. With tolerant = 1, the system
always panic()s. When the system panic()s, the BIOS is able to detect
that the cause of death was an MC4. I was not able to reproduce the
case of a non-PCC error in userspace, with EIPV, with (tolerant < 3).
That will be rare at best.
Signed-off-by: Tim Hockin <thockin@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-21 22:10:37 +07:00
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0: always panic on uncorrected errors, log corrected errors
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1: panic or SIGBUS on uncorrected errors, log corrected errors
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2: SIGBUS or log uncorrected errors, log corrected errors
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3: never panic or SIGBUS, log all errors (for testing only)
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Default is 1
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2005-09-12 23:49:24 +07:00
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Can be also set using sysfs which is preferable.
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2009-05-28 02:56:55 +07:00
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monarchtimeout:
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Sets the time in us to wait for other CPUs on machine checks. 0
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to disable.
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2012-09-28 00:08:00 +07:00
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mce=bios_cmci_threshold
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Don't overwrite the bios-set CMCI threshold. This boot option
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prevents Linux from overwriting the CMCI threshold set by the
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bios. Without this option, Linux always sets the CMCI
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threshold to 1. Enabling this may make memory predictive failure
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analysis less effective if the bios sets thresholds for memory
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errors since we will not see details for all errors.
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2016-02-18 01:20:13 +07:00
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mce=recovery
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Force-enable recoverable machine check code paths
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2005-04-17 05:20:36 +07:00
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nomce (for compatibility with i386): same as mce=off
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Everything else is in sysfs now.
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APICs
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apic Use IO-APIC. Default
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noapic Don't use the IO-APIC.
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disableapic Don't use the local APIC
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nolapic Don't use the local APIC (alias for i386 compatibility)
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2008-10-20 23:32:21 +07:00
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pirq=... See Documentation/x86/i386/IO-APIC.txt
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2005-04-17 05:20:36 +07:00
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noapictimer Don't set up the APIC timer
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2005-05-21 04:27:59 +07:00
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no_timer_check Don't check the IO-APIC timer. This can work around
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problems with incorrect timer initialization on some boards.
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2006-02-04 03:51:41 +07:00
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apicpmtimer
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Do APIC timer calibration using the pmtimer. Implies
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apicmaintimer. Useful when your PIT timer is totally
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broken.
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2005-04-17 05:20:36 +07:00
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Timing
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notsc
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Don't use the CPU time stamp counter to read the wall time.
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This can be used to work around timing problems on multiprocessor systems
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2005-07-29 11:15:34 +07:00
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with not properly synchronized CPUs.
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2005-04-17 05:20:36 +07:00
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nohpet
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Don't use the HPET timer.
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Idle loop
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idle=poll
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Don't do power saving in the idle loop using HLT, but poll for rescheduling
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event. This will make the CPUs eat a lot more power, but may be useful
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to get slightly better performance in multiprocessor benchmarks. It also
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makes some profiling using performance counters more accurate.
|
2005-07-29 11:15:34 +07:00
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|
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Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
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CPUs) this option has no performance advantage over the normal idle loop.
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It may also interact badly with hyperthreading.
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2005-04-17 05:20:36 +07:00
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Rebooting
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2008-01-30 19:31:19 +07:00
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reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] [, [w]arm | [c]old]
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2006-10-04 03:54:15 +07:00
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bios Use the CPU reboot vector for warm reset
|
2005-04-17 05:20:36 +07:00
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warm Don't set the cold reboot flag
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cold Set the cold reboot flag
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triple Force a triple fault (init)
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kbd Use the keyboard controller. cold reset (default)
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2008-01-30 19:31:17 +07:00
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acpi Use the ACPI RESET_REG in the FADT. If ACPI is not configured or the
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ACPI reset does not work, the reboot path attempts the reset using
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the keyboard controller.
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2008-01-30 19:31:19 +07:00
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efi Use efi reset_system runtime service. If EFI is not configured or the
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EFI reset does not work, the reboot path attempts the reset using
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the keyboard controller.
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2005-04-17 05:20:36 +07:00
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Using warm reset will be much faster especially on big memory
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systems because the BIOS will not go through the memory check.
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Disadvantage is that not all hardware will be completely reinitialized
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on reboot so there may be boot problems on some systems.
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reboot=force
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Don't stop other CPUs on reboot. This can make reboot more reliable
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in some cases.
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Non Executable Mappings
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noexec=on|off
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on Enable(default)
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off Disable
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NUMA
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numa=off Only set up a single NUMA node spanning all memory.
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numa=noacpi Don't parse the SRAT table for NUMA setup
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|
2010-02-16 04:43:30 +07:00
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|
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numa=fake=<size>[MG]
|
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If given as a memory unit, fills all system RAM with nodes of
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size interleaved over physical nodes.
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|
2010-02-16 04:43:33 +07:00
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numa=fake=<N>
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If given as an integer, fills all system RAM with N fake nodes
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interleaved over physical nodes.
|
2005-04-17 05:20:36 +07:00
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ACPI
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acpi=off Don't enable ACPI
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acpi=ht Use ACPI boot table parsing, but don't enable ACPI
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interpreter
|
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acpi=force Force ACPI on (currently not needed)
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acpi=strict Disable out of spec ACPI workarounds.
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acpi_sci={edge,level,high,low} Set up ACPI SCI interrupt.
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acpi=noirq Don't route interrupts
|
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|
2013-07-01 22:38:54 +07:00
|
|
|
acpi=nocmcff Disable firmware first mode for corrected errors. This
|
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|
|
disables parsing the HEST CMC error source to check if
|
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|
|
firmware has set the FF flag. This may result in
|
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|
|
duplicate corrected error reports.
|
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|
2005-04-17 05:20:36 +07:00
|
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PCI
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|
2011-03-18 02:24:15 +07:00
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pci=off Don't use PCI
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pci=conf1 Use conf1 access.
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pci=conf2 Use conf2 access.
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pci=rom Assign ROMs.
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pci=assign-busses Assign busses
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pci=irqmask=MASK Set PCI interrupt mask to MASK
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pci=lastbus=NUMBER Scan up to NUMBER busses, no matter what the mptable says.
|
2005-04-17 05:20:36 +07:00
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pci=noacpi Don't use ACPI to set up PCI interrupt routing.
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|
2007-02-13 19:26:21 +07:00
|
|
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IOMMU (input/output memory management unit)
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Currently four x86-64 PCI-DMA mapping implementations exist:
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1. <arch/x86_64/kernel/pci-nommu.c>: use no hardware/software IOMMU at all
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(e.g. because you have < 3 GB memory).
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Kernel boot message: "PCI-DMA: Disabling IOMMU"
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|
2011-05-10 22:22:06 +07:00
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2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
|
2007-02-13 19:26:21 +07:00
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Kernel boot message: "PCI-DMA: using GART IOMMU"
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3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
|
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e.g. if there is no hardware IOMMU in the system and it is need because
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you have >3GB memory or told the kernel to us it (iommu=soft))
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Kernel boot message: "PCI-DMA: Using software bounce buffering
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for IO (SWIOTLB)"
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4. <arch/x86_64/pci-calgary.c> : IBM Calgary hardware IOMMU. Used in IBM
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pSeries and xSeries servers. This hardware IOMMU supports DMA address
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mapping with memory protection, etc.
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Kernel boot message: "PCI-DMA: Using Calgary IOMMU"
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iommu=[<size>][,noagp][,off][,force][,noforce][,leak[=<nr_of_leak_pages>]
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[,memaper[=<order>]][,merge][,forcesac][,fullflush][,nomerge]
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[,noaperture][,calgary]
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General iommu options:
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off Don't initialize and use any kind of IOMMU.
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noforce Don't force hardware IOMMU usage when it is not needed.
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(default).
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force Force the use of the hardware IOMMU even when it is
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not actually needed (e.g. because < 3 GB memory).
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soft Use software bounce buffering (SWIOTLB) (default for
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Intel machines). This can be used to prevent the usage
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of an available hardware IOMMU.
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iommu options only relevant to the AMD GART hardware IOMMU:
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<size> Set the size of the remapping area in bytes.
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allowed Overwrite iommu off workarounds for specific chipsets.
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fullflush Flush IOMMU on each allocation (default).
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nofullflush Don't use IOMMU fullflush.
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leak Turn on simple iommu leak tracing (only when
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|
CONFIG_IOMMU_LEAK is on). Default number of leak pages
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is 20.
|
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memaper[=<order>] Allocate an own aperture over RAM with size 32MB<<order.
|
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|
|
(default: order=1, i.e. 64MB)
|
2007-02-13 19:26:23 +07:00
|
|
|
merge Do scatter-gather (SG) merging. Implies "force"
|
2007-02-13 19:26:21 +07:00
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|
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(experimental).
|
2007-02-13 19:26:23 +07:00
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nomerge Don't do scatter-gather (SG) merging.
|
2007-02-13 19:26:21 +07:00
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noaperture Ask the IOMMU not to touch the aperture for AGP.
|
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forcesac Force single-address cycle (SAC) mode for masks <40bits
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(experimental).
|
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noagp Don't initialize the AGP driver and use full aperture.
|
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|
allowdac Allow double-address cycle (DAC) mode, i.e. DMA >4GB.
|
|
|
|
DAC is used with 32-bit PCI to push a 64-bit address in
|
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|
two cycles. When off all DMA over >4GB is forced through
|
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|
|
an IOMMU or software bounce buffering.
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nodac Forbid DAC mode, i.e. DMA >4GB.
|
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panic Always panic when IOMMU overflows.
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|
calgary Use the Calgary IOMMU if it is available
|
|
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|
|
iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
|
|
|
|
implementation:
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swiotlb=<pages>[,force]
|
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|
<pages> Prereserve that many 128K pages for the software IO
|
|
|
|
bounce buffering.
|
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force Force all IO through the software TLB.
|
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|
|
Settings for the IBM Calgary hardware IOMMU currently found in IBM
|
|
|
|
pSeries and xSeries machines:
|
|
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|
|
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|
|
calgary=[64k,128k,256k,512k,1M,2M,4M,8M]
|
|
|
|
calgary=[translate_empty_slots]
|
|
|
|
calgary=[disable=<PCI bus number>]
|
|
|
|
panic Always panic when IOMMU overflows
|
2006-06-26 18:58:14 +07:00
|
|
|
|
|
|
|
64k,...,8M - Set the size of each PCI slot's translation table
|
|
|
|
when using the Calgary IOMMU. This is the size of the translation
|
|
|
|
table itself in main memory. The smallest table, 64k, covers an IO
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|
|
space of 32MB; the largest, 8MB table, can cover an IO space of
|
|
|
|
4GB. Normally the kernel will make the right choice by itself.
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|
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|
|
translate_empty_slots - Enable translation even on slots that have
|
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|
|
no devices attached to them, in case a device will be hotplugged
|
|
|
|
in the future.
|
|
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|
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|
|
disable=<PCI bus number> - Disable translation on a given PHB. For
|
|
|
|
example, the built-in graphics adapter resides on the first bridge
|
|
|
|
(PCI bus number 0); if translation (isolation) is enabled on this
|
|
|
|
bridge, X servers that access the hardware directly from user
|
|
|
|
space might stop working. Use this option if you have devices that
|
|
|
|
are accessed from userspace directly on some PCI host bridge.
|
|
|
|
|
2007-02-13 19:26:23 +07:00
|
|
|
Miscellaneous
|
2008-04-17 22:40:45 +07:00
|
|
|
|
|
|
|
nogbpages
|
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|
|
Do not use GB pages for kernel direct mappings.
|
|
|
|
gbpages
|
|
|
|
Use GB pages for kernel direct mappings.
|