2005-09-26 13:04:21 +07:00
|
|
|
/*
|
|
|
|
* MMU context allocation for 64-bit kernels.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2004 Anton Blanchard, IBM Corp. <anton@samba.org>
|
|
|
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*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License
|
|
|
|
* as published by the Free Software Foundation; either version
|
|
|
|
* 2 of the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/sched.h>
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/errno.h>
|
|
|
|
#include <linux/string.h>
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include <linux/mm.h>
|
2018-01-19 08:50:25 +07:00
|
|
|
#include <linux/pkeys.h>
|
2005-09-26 13:04:21 +07:00
|
|
|
#include <linux/spinlock.h>
|
|
|
|
#include <linux/idr.h>
|
2011-07-23 05:24:23 +07:00
|
|
|
#include <linux/export.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
|
|
|
#include <linux/gfp.h>
|
2011-05-03 03:43:04 +07:00
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|
|
#include <linux/slab.h>
|
2005-09-26 13:04:21 +07:00
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|
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#include <asm/mmu_context.h>
|
2013-04-28 16:37:33 +07:00
|
|
|
#include <asm/pgalloc.h>
|
2005-09-26 13:04:21 +07:00
|
|
|
|
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|
|
static DEFINE_SPINLOCK(mmu_context_lock);
|
2010-02-07 19:30:12 +07:00
|
|
|
static DEFINE_IDA(mmu_context_ida);
|
2005-09-26 13:04:21 +07:00
|
|
|
|
2017-03-29 18:10:45 +07:00
|
|
|
static int alloc_context_id(int min_id, int max_id)
|
2005-09-26 13:04:21 +07:00
|
|
|
{
|
2017-03-29 18:10:45 +07:00
|
|
|
int index, err;
|
2005-09-26 13:04:21 +07:00
|
|
|
|
|
|
|
again:
|
2010-02-07 19:30:12 +07:00
|
|
|
if (!ida_pre_get(&mmu_context_ida, GFP_KERNEL))
|
2005-09-26 13:04:21 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
spin_lock(&mmu_context_lock);
|
2017-03-29 18:10:45 +07:00
|
|
|
err = ida_get_new_above(&mmu_context_ida, min_id, &index);
|
2005-09-26 13:04:21 +07:00
|
|
|
spin_unlock(&mmu_context_lock);
|
|
|
|
|
|
|
|
if (err == -EAGAIN)
|
|
|
|
goto again;
|
|
|
|
else if (err)
|
|
|
|
return err;
|
|
|
|
|
2017-03-29 18:10:45 +07:00
|
|
|
if (index > max_id) {
|
2006-06-27 19:46:09 +07:00
|
|
|
spin_lock(&mmu_context_lock);
|
2010-02-07 19:30:12 +07:00
|
|
|
ida_remove(&mmu_context_ida, index);
|
2006-06-27 19:46:09 +07:00
|
|
|
spin_unlock(&mmu_context_lock);
|
2005-09-26 13:04:21 +07:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2009-11-02 19:02:30 +07:00
|
|
|
return index;
|
|
|
|
}
|
2017-03-29 18:00:46 +07:00
|
|
|
|
2017-03-22 10:37:00 +07:00
|
|
|
void hash__reserve_context_id(int id)
|
|
|
|
{
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|
|
|
int rc, result = 0;
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (!ida_pre_get(&mmu_context_ida, GFP_KERNEL))
|
|
|
|
break;
|
|
|
|
|
|
|
|
spin_lock(&mmu_context_lock);
|
|
|
|
rc = ida_get_new_above(&mmu_context_ida, id, &result);
|
|
|
|
spin_unlock(&mmu_context_lock);
|
|
|
|
} while (rc == -EAGAIN);
|
|
|
|
|
|
|
|
WARN(result != id, "mmu: Failed to reserve context id %d (rc %d)\n", id, result);
|
|
|
|
}
|
|
|
|
|
2017-03-29 18:00:46 +07:00
|
|
|
int hash__alloc_context_id(void)
|
|
|
|
{
|
2017-03-29 13:21:53 +07:00
|
|
|
unsigned long max;
|
|
|
|
|
|
|
|
if (mmu_has_feature(MMU_FTR_68_BIT_VA))
|
|
|
|
max = MAX_USER_CONTEXT;
|
|
|
|
else
|
|
|
|
max = MAX_USER_CONTEXT_65BIT_VA;
|
|
|
|
|
|
|
|
return alloc_context_id(MIN_USER_CONTEXT, max);
|
2017-03-29 18:00:46 +07:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(hash__alloc_context_id);
|
|
|
|
|
2017-03-29 18:36:56 +07:00
|
|
|
static int hash__init_new_context(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
int index;
|
|
|
|
|
|
|
|
index = hash__alloc_context_id();
|
|
|
|
if (index < 0)
|
|
|
|
return index;
|
|
|
|
|
2017-03-22 10:36:58 +07:00
|
|
|
/*
|
2017-11-10 00:27:37 +07:00
|
|
|
* In the case of exec, use the default limit,
|
|
|
|
* otherwise inherit it from the mm we are duplicating.
|
2017-03-22 10:36:58 +07:00
|
|
|
*/
|
2017-11-10 00:27:40 +07:00
|
|
|
if (!mm->context.slb_addr_limit)
|
|
|
|
mm->context.slb_addr_limit = DEFAULT_MAP_WINDOW_USER64;
|
2017-03-22 10:36:58 +07:00
|
|
|
|
2017-03-29 18:36:56 +07:00
|
|
|
/*
|
|
|
|
* The old code would re-promote on fork, we don't do that when using
|
|
|
|
* slices as it could cause problem promoting slices that have been
|
|
|
|
* forced down to 4K.
|
|
|
|
*
|
|
|
|
* For book3s we have MMU_NO_CONTEXT set to be ~0. Hence check
|
|
|
|
* explicitly against context.id == 0. This ensures that we properly
|
|
|
|
* initialize context slice details for newly allocated mm's (which will
|
|
|
|
* have id == 0) and don't alter context slice inherited via fork (which
|
|
|
|
* will have id != 0).
|
|
|
|
*
|
|
|
|
* We should not be calling init_new_context() on init_mm. Hence a
|
|
|
|
* check against 0 is OK.
|
|
|
|
*/
|
|
|
|
if (mm->context.id == 0)
|
|
|
|
slice_set_user_psize(mm, mmu_virtual_psize);
|
|
|
|
|
|
|
|
subpage_prot_init_new_context(mm);
|
|
|
|
|
2018-01-19 08:50:25 +07:00
|
|
|
pkey_mm_init(mm);
|
2017-03-29 18:36:56 +07:00
|
|
|
return index;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int radix__init_new_context(struct mm_struct *mm)
|
2016-04-29 20:26:02 +07:00
|
|
|
{
|
|
|
|
unsigned long rts_field;
|
powerpc/mm/radix: Workaround prefetch issue with KVM
There's a somewhat architectural issue with Radix MMU and KVM.
When coming out of a guest with AIL (Alternate Interrupt Location, ie,
MMU enabled), we start executing hypervisor code with the PID register
still containing whatever the guest has been using.
The problem is that the CPU can (and will) then start prefetching or
speculatively load from whatever host context has that same PID (if
any), thus bringing translations for that context into the TLB, which
Linux doesn't know about.
This can cause stale translations and subsequent crashes.
Fixing this in a way that is neither racy nor a huge performance
impact is difficult. We could just make the host invalidations always
use broadcast forms but that would hurt single threaded programs for
example.
We chose to fix it instead by partitioning the PID space between guest
and host. This is possible because today Linux only use 19 out of the
20 bits of PID space, so existing guests will work if we make the host
use the top half of the 20 bits space.
We additionally add support for a property to indicate to Linux the
size of the PID register which will be useful if we eventually have
processors with a larger PID space available.
There is still an issue with malicious guests purposefully setting the
PID register to a value in the hosts PID range. Hopefully future HW
can prevent that, but in the meantime, we handle it with a pair of
kludges:
- On the way out of a guest, before we clear the current VCPU in the
PACA, we check the PID and if it's outside of the permitted range
we flush the TLB for that PID.
- When context switching, if the mm is "new" on that CPU (the
corresponding bit was set for the first time in the mm cpumask), we
check if any sibling thread is in KVM (has a non-NULL VCPU pointer
in the PACA). If that is the case, we also flush the PID for that
CPU (core).
This second part is needed to handle the case where a process is
migrated (or starts a new pthread) on a sibling thread of the CPU
coming out of KVM, as there's a window where stale translations can
exist before we detect it and flush them out.
A future optimization could be added by keeping track of whether the
PID has ever been used and avoid doing that for completely fresh PIDs.
We could similarily mark PIDs that have been the subject of a global
invalidation as "fresh". But for now this will do.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[mpe: Rework the asm to build with CONFIG_PPC_RADIX_MMU=n, drop
unneeded include of kvm_book3s_asm.h]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-07-24 11:26:06 +07:00
|
|
|
int index, max_id;
|
2017-03-29 18:36:56 +07:00
|
|
|
|
powerpc/mm/radix: Workaround prefetch issue with KVM
There's a somewhat architectural issue with Radix MMU and KVM.
When coming out of a guest with AIL (Alternate Interrupt Location, ie,
MMU enabled), we start executing hypervisor code with the PID register
still containing whatever the guest has been using.
The problem is that the CPU can (and will) then start prefetching or
speculatively load from whatever host context has that same PID (if
any), thus bringing translations for that context into the TLB, which
Linux doesn't know about.
This can cause stale translations and subsequent crashes.
Fixing this in a way that is neither racy nor a huge performance
impact is difficult. We could just make the host invalidations always
use broadcast forms but that would hurt single threaded programs for
example.
We chose to fix it instead by partitioning the PID space between guest
and host. This is possible because today Linux only use 19 out of the
20 bits of PID space, so existing guests will work if we make the host
use the top half of the 20 bits space.
We additionally add support for a property to indicate to Linux the
size of the PID register which will be useful if we eventually have
processors with a larger PID space available.
There is still an issue with malicious guests purposefully setting the
PID register to a value in the hosts PID range. Hopefully future HW
can prevent that, but in the meantime, we handle it with a pair of
kludges:
- On the way out of a guest, before we clear the current VCPU in the
PACA, we check the PID and if it's outside of the permitted range
we flush the TLB for that PID.
- When context switching, if the mm is "new" on that CPU (the
corresponding bit was set for the first time in the mm cpumask), we
check if any sibling thread is in KVM (has a non-NULL VCPU pointer
in the PACA). If that is the case, we also flush the PID for that
CPU (core).
This second part is needed to handle the case where a process is
migrated (or starts a new pthread) on a sibling thread of the CPU
coming out of KVM, as there's a window where stale translations can
exist before we detect it and flush them out.
A future optimization could be added by keeping track of whether the
PID has ever been used and avoid doing that for completely fresh PIDs.
We could similarily mark PIDs that have been the subject of a global
invalidation as "fresh". But for now this will do.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[mpe: Rework the asm to build with CONFIG_PPC_RADIX_MMU=n, drop
unneeded include of kvm_book3s_asm.h]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-07-24 11:26:06 +07:00
|
|
|
max_id = (1 << mmu_pid_bits) - 1;
|
|
|
|
index = alloc_context_id(mmu_base_pid, max_id);
|
2017-03-29 18:36:56 +07:00
|
|
|
if (index < 0)
|
|
|
|
return index;
|
2016-04-29 20:26:02 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* set the process table entry,
|
|
|
|
*/
|
2016-06-17 13:10:36 +07:00
|
|
|
rts_field = radix__get_tree_size();
|
2016-04-29 20:26:02 +07:00
|
|
|
process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE);
|
2017-03-29 18:36:56 +07:00
|
|
|
|
2017-07-08 04:12:16 +07:00
|
|
|
/*
|
|
|
|
* Order the above store with subsequent update of the PID
|
|
|
|
* register (at which point HW can start loading/caching
|
|
|
|
* the entry) and the corresponding load by the MMU from
|
|
|
|
* the L2 cache.
|
|
|
|
*/
|
|
|
|
asm volatile("ptesync;isync" : : : "memory");
|
|
|
|
|
2017-04-03 16:51:44 +07:00
|
|
|
mm->context.npu_context = NULL;
|
|
|
|
|
2017-03-29 18:36:56 +07:00
|
|
|
return index;
|
2016-04-29 20:26:02 +07:00
|
|
|
}
|
2009-11-02 19:02:30 +07:00
|
|
|
|
|
|
|
int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
int index;
|
|
|
|
|
2017-03-29 18:36:56 +07:00
|
|
|
if (radix_enabled())
|
|
|
|
index = radix__init_new_context(mm);
|
|
|
|
else
|
|
|
|
index = hash__init_new_context(mm);
|
|
|
|
|
2009-11-02 19:02:30 +07:00
|
|
|
if (index < 0)
|
|
|
|
return index;
|
|
|
|
|
2007-08-15 13:33:55 +07:00
|
|
|
mm->context.id = index;
|
2005-09-26 13:04:21 +07:00
|
|
|
|
2013-04-28 16:37:33 +07:00
|
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
|
|
mm->context.pte_frag = NULL;
|
2015-06-05 13:35:24 +07:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPAPR_TCE_IOMMU
|
2016-11-30 13:51:59 +07:00
|
|
|
mm_iommu_init(mm);
|
2013-04-28 16:37:33 +07:00
|
|
|
#endif
|
2017-07-24 11:28:02 +07:00
|
|
|
atomic_set(&mm->context.active_cpus, 0);
|
|
|
|
|
2005-09-26 13:04:21 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-02 19:02:30 +07:00
|
|
|
void __destroy_context(int context_id)
|
2005-09-26 13:04:21 +07:00
|
|
|
{
|
|
|
|
spin_lock(&mmu_context_lock);
|
2010-02-07 19:30:12 +07:00
|
|
|
ida_remove(&mmu_context_ida, context_id);
|
2005-09-26 13:04:21 +07:00
|
|
|
spin_unlock(&mmu_context_lock);
|
2009-11-02 19:02:30 +07:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(__destroy_context);
|
2005-09-26 13:04:21 +07:00
|
|
|
|
2013-04-28 16:37:33 +07:00
|
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
|
|
static void destroy_pagetable_page(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
int count;
|
|
|
|
void *pte_frag;
|
|
|
|
struct page *page;
|
|
|
|
|
|
|
|
pte_frag = mm->context.pte_frag;
|
|
|
|
if (!pte_frag)
|
|
|
|
return;
|
|
|
|
|
|
|
|
page = virt_to_page(pte_frag);
|
|
|
|
/* drop all the pending references */
|
|
|
|
count = ((unsigned long)pte_frag & ~PAGE_MASK) >> PTE_FRAG_SIZE_SHIFT;
|
|
|
|
/* We allow PTE_FRAG_NR fragments from a PTE page */
|
2016-03-18 04:19:26 +07:00
|
|
|
if (page_ref_sub_and_test(page, PTE_FRAG_NR - count)) {
|
2013-04-28 16:37:33 +07:00
|
|
|
pgtable_page_dtor(page);
|
2017-11-16 08:37:59 +07:00
|
|
|
free_unref_page(page);
|
2013-04-28 16:37:33 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
static inline void destroy_pagetable_page(struct mm_struct *mm)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-11-02 19:02:30 +07:00
|
|
|
void destroy_context(struct mm_struct *mm)
|
|
|
|
{
|
2015-06-05 13:35:24 +07:00
|
|
|
#ifdef CONFIG_SPAPR_TCE_IOMMU
|
2016-11-30 13:52:05 +07:00
|
|
|
WARN_ON_ONCE(!list_empty(&mm->context.iommu_group_mem_list));
|
2015-06-05 13:35:24 +07:00
|
|
|
#endif
|
2017-10-24 20:06:54 +07:00
|
|
|
if (radix_enabled())
|
|
|
|
WARN_ON(process_tb[mm->context.id].prtb0 != 0);
|
|
|
|
else
|
|
|
|
subpage_prot_free(mm);
|
|
|
|
destroy_pagetable_page(mm);
|
|
|
|
__destroy_context(mm->context.id);
|
|
|
|
mm->context.id = MMU_NO_CONTEXT;
|
|
|
|
}
|
|
|
|
|
|
|
|
void arch_exit_mmap(struct mm_struct *mm)
|
|
|
|
{
|
2017-07-08 19:45:32 +07:00
|
|
|
if (radix_enabled()) {
|
|
|
|
/*
|
|
|
|
* Radix doesn't have a valid bit in the process table
|
|
|
|
* entries. However we know that at least P9 implementation
|
|
|
|
* will avoid caching an entry with an invalid RTS field,
|
|
|
|
* and 0 is invalid. So this will do.
|
2017-10-24 20:06:54 +07:00
|
|
|
*
|
|
|
|
* This runs before the "fullmm" tlb flush in exit_mmap,
|
|
|
|
* which does a RIC=2 tlbie to clear the process table
|
|
|
|
* entry. See the "fullmm" comments in tlb-radix.c.
|
|
|
|
*
|
|
|
|
* No barrier required here after the store because
|
|
|
|
* this process will do the invalidate, which starts with
|
|
|
|
* ptesync.
|
2017-07-08 19:45:32 +07:00
|
|
|
*/
|
|
|
|
process_tb[mm->context.id].prtb0 = 0;
|
2017-10-24 20:06:54 +07:00
|
|
|
}
|
2005-09-26 13:04:21 +07:00
|
|
|
}
|
2016-04-29 20:26:02 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_RADIX_MMU
|
|
|
|
void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
|
|
|
|
{
|
2017-06-26 03:08:46 +07:00
|
|
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
|
|
|
|
isync();
|
|
|
|
mtspr(SPRN_PID, next->context.id);
|
|
|
|
isync();
|
|
|
|
asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
|
|
|
|
} else {
|
|
|
|
mtspr(SPRN_PID, next->context.id);
|
|
|
|
isync();
|
|
|
|
}
|
2016-04-29 20:26:02 +07:00
|
|
|
}
|
|
|
|
#endif
|