blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 04:50:22 +07:00
|
|
|
/*
|
2009-06-17 22:25:06 +07:00
|
|
|
* Common Blackfin memory map
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 04:50:22 +07:00
|
|
|
*
|
2009-06-17 22:25:06 +07:00
|
|
|
* Copyright 2004-2009 Analog Devices Inc.
|
|
|
|
* Licensed under the GPL-2 or later.
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 04:50:22 +07:00
|
|
|
*/
|
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
#ifndef __BFIN_MEM_MAP_H__
|
|
|
|
#define __BFIN_MEM_MAP_H__
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 04:50:22 +07:00
|
|
|
|
2008-08-27 09:51:02 +07:00
|
|
|
#include <mach/mem_map.h>
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 04:50:22 +07:00
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
/* Every Blackfin so far has MMRs like this */
|
|
|
|
#ifndef COREMMR_BASE
|
|
|
|
# define COREMMR_BASE 0xFFE00000
|
|
|
|
#endif
|
|
|
|
#ifndef SYSMMR_BASE
|
|
|
|
# define SYSMMR_BASE 0xFFC00000
|
|
|
|
#endif
|
2009-01-07 22:14:39 +07:00
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
|
|
|
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#ifndef L1_SCRATCH_START
|
|
|
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# define L1_SCRATCH_START 0xFFB00000
|
|
|
|
# define L1_SCRATCH_LENGTH 0x1000
|
|
|
|
#endif
|
2009-01-07 22:14:39 +07:00
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
/* Most parts lack on-chip L2 SRAM */
|
|
|
|
#ifndef L2_START
|
|
|
|
# define L2_START 0
|
|
|
|
# define L2_LENGTH 0
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Most parts lack on-chip L1 ROM */
|
|
|
|
#ifndef L1_ROM_START
|
|
|
|
# define L1_ROM_START 0
|
|
|
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# define L1_ROM_LENGTH 0
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Allow wonky SMP ports to override this */
|
|
|
|
#ifndef GET_PDA_SAFE
|
|
|
|
# define GET_PDA_SAFE(preg) \
|
|
|
|
preg.l = _cpu_pda; \
|
|
|
|
preg.h = _cpu_pda;
|
|
|
|
# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
|
2009-01-07 22:14:39 +07:00
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
# ifndef __ASSEMBLY__
|
2009-01-07 22:14:39 +07:00
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_scratch_start_cpu(int cpu)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return L1_SCRATCH_START;
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_code_start_cpu(int cpu)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return L1_CODE_START;
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_data_a_start_cpu(int cpu)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return L1_DATA_A_START;
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_data_b_start_cpu(int cpu)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return L1_DATA_B_START;
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_scratch_start(void)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return get_l1_scratch_start_cpu(0);
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_code_start(void)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return get_l1_code_start_cpu(0);
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_data_a_start(void)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return get_l1_data_a_start_cpu(0);
|
|
|
|
}
|
2009-06-17 22:25:06 +07:00
|
|
|
static inline unsigned long get_l1_data_b_start(void)
|
2009-01-07 22:14:39 +07:00
|
|
|
{
|
|
|
|
return get_l1_data_b_start_cpu(0);
|
|
|
|
}
|
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
# endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* !GET_PDA_SAFE */
|
2009-01-07 22:14:39 +07:00
|
|
|
|
2009-06-17 22:25:06 +07:00
|
|
|
#endif
|