mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 08:35:10 +07:00
292 lines
15 KiB
C
292 lines
15 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Lochnagar2 register definitions
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*
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* Copyright (c) 2017-2018 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*
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* Author: Charles Keepax <ckeepax@opensource.cirrus.com>
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*/
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#ifndef LOCHNAGAR2_REGISTERS_H
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#define LOCHNAGAR2_REGISTERS_H
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/* Register Addresses */
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#define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D
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#define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E
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#define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F
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#define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010
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#define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011
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#define LOCHNAGAR2_PSIA1_CTRL 0x0012
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#define LOCHNAGAR2_PSIA2_CTRL 0x0013
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#define LOCHNAGAR2_GF_AIF3_CTRL 0x0014
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#define LOCHNAGAR2_GF_AIF4_CTRL 0x0015
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#define LOCHNAGAR2_GF_AIF1_CTRL 0x0016
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#define LOCHNAGAR2_GF_AIF2_CTRL 0x0017
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#define LOCHNAGAR2_SPDIF_AIF_CTRL 0x0018
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#define LOCHNAGAR2_USB_AIF1_CTRL 0x0019
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#define LOCHNAGAR2_USB_AIF2_CTRL 0x001A
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#define LOCHNAGAR2_ADAT_AIF_CTRL 0x001B
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#define LOCHNAGAR2_CDC_MCLK1_CTRL 0x001E
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#define LOCHNAGAR2_CDC_MCLK2_CTRL 0x001F
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#define LOCHNAGAR2_DSP_CLKIN_CTRL 0x0020
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#define LOCHNAGAR2_PSIA1_MCLK_CTRL 0x0021
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#define LOCHNAGAR2_PSIA2_MCLK_CTRL 0x0022
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#define LOCHNAGAR2_SPDIF_MCLK_CTRL 0x0023
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#define LOCHNAGAR2_GF_CLKOUT1_CTRL 0x0024
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#define LOCHNAGAR2_GF_CLKOUT2_CTRL 0x0025
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#define LOCHNAGAR2_ADAT_MCLK_CTRL 0x0026
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#define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL 0x0027
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#define LOCHNAGAR2_GPIO_FPGA_GPIO1 0x0031
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#define LOCHNAGAR2_GPIO_FPGA_GPIO2 0x0032
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#define LOCHNAGAR2_GPIO_FPGA_GPIO3 0x0033
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#define LOCHNAGAR2_GPIO_FPGA_GPIO4 0x0034
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#define LOCHNAGAR2_GPIO_FPGA_GPIO5 0x0035
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#define LOCHNAGAR2_GPIO_FPGA_GPIO6 0x0036
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#define LOCHNAGAR2_GPIO_CDC_GPIO1 0x0037
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#define LOCHNAGAR2_GPIO_CDC_GPIO2 0x0038
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#define LOCHNAGAR2_GPIO_CDC_GPIO3 0x0039
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#define LOCHNAGAR2_GPIO_CDC_GPIO4 0x003A
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#define LOCHNAGAR2_GPIO_CDC_GPIO5 0x003B
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#define LOCHNAGAR2_GPIO_CDC_GPIO6 0x003C
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#define LOCHNAGAR2_GPIO_CDC_GPIO7 0x003D
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#define LOCHNAGAR2_GPIO_CDC_GPIO8 0x003E
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#define LOCHNAGAR2_GPIO_DSP_GPIO1 0x003F
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#define LOCHNAGAR2_GPIO_DSP_GPIO2 0x0040
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#define LOCHNAGAR2_GPIO_DSP_GPIO3 0x0041
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#define LOCHNAGAR2_GPIO_DSP_GPIO4 0x0042
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#define LOCHNAGAR2_GPIO_DSP_GPIO5 0x0043
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#define LOCHNAGAR2_GPIO_DSP_GPIO6 0x0044
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#define LOCHNAGAR2_GPIO_GF_GPIO2 0x0045
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#define LOCHNAGAR2_GPIO_GF_GPIO3 0x0046
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#define LOCHNAGAR2_GPIO_GF_GPIO7 0x0047
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#define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK 0x0048
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#define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT 0x0049
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#define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK 0x004A
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#define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT 0x004B
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#define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK 0x004C
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#define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT 0x004D
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#define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK 0x004E
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#define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT 0x004F
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#define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK 0x0050
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#define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT 0x0051
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#define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK 0x0052
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#define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT 0x0053
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#define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK 0x0054
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#define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT 0x0055
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#define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK 0x0056
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#define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT 0x0057
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#define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK 0x0058
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#define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT 0x0059
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#define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK 0x005A
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#define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT 0x005B
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#define LOCHNAGAR2_GPIO_PSIA1_BCLK 0x005C
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#define LOCHNAGAR2_GPIO_PSIA1_RXDAT 0x005D
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#define LOCHNAGAR2_GPIO_PSIA1_LRCLK 0x005E
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#define LOCHNAGAR2_GPIO_PSIA1_TXDAT 0x005F
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#define LOCHNAGAR2_GPIO_PSIA2_BCLK 0x0060
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#define LOCHNAGAR2_GPIO_PSIA2_RXDAT 0x0061
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#define LOCHNAGAR2_GPIO_PSIA2_LRCLK 0x0062
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#define LOCHNAGAR2_GPIO_PSIA2_TXDAT 0x0063
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#define LOCHNAGAR2_GPIO_GF_AIF3_BCLK 0x0064
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#define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT 0x0065
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#define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK 0x0066
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#define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT 0x0067
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#define LOCHNAGAR2_GPIO_GF_AIF4_BCLK 0x0068
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#define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT 0x0069
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#define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK 0x006A
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#define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT 0x006B
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#define LOCHNAGAR2_GPIO_GF_AIF1_BCLK 0x006C
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#define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT 0x006D
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#define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK 0x006E
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#define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT 0x006F
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#define LOCHNAGAR2_GPIO_GF_AIF2_BCLK 0x0070
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#define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT 0x0071
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#define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK 0x0072
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#define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT 0x0073
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#define LOCHNAGAR2_GPIO_DSP_UART1_RX 0x0074
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#define LOCHNAGAR2_GPIO_DSP_UART1_TX 0x0075
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#define LOCHNAGAR2_GPIO_DSP_UART2_RX 0x0076
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#define LOCHNAGAR2_GPIO_DSP_UART2_TX 0x0077
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#define LOCHNAGAR2_GPIO_GF_UART2_RX 0x0078
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#define LOCHNAGAR2_GPIO_GF_UART2_TX 0x0079
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#define LOCHNAGAR2_GPIO_USB_UART_RX 0x007A
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#define LOCHNAGAR2_GPIO_CDC_PDMCLK1 0x007C
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#define LOCHNAGAR2_GPIO_CDC_PDMDAT1 0x007D
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#define LOCHNAGAR2_GPIO_CDC_PDMCLK2 0x007E
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#define LOCHNAGAR2_GPIO_CDC_PDMDAT2 0x007F
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#define LOCHNAGAR2_GPIO_CDC_DMICCLK1 0x0080
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#define LOCHNAGAR2_GPIO_CDC_DMICDAT1 0x0081
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#define LOCHNAGAR2_GPIO_CDC_DMICCLK2 0x0082
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#define LOCHNAGAR2_GPIO_CDC_DMICDAT2 0x0083
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#define LOCHNAGAR2_GPIO_CDC_DMICCLK3 0x0084
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#define LOCHNAGAR2_GPIO_CDC_DMICDAT3 0x0085
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#define LOCHNAGAR2_GPIO_CDC_DMICCLK4 0x0086
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#define LOCHNAGAR2_GPIO_CDC_DMICDAT4 0x0087
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#define LOCHNAGAR2_GPIO_DSP_DMICCLK1 0x0088
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#define LOCHNAGAR2_GPIO_DSP_DMICDAT1 0x0089
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#define LOCHNAGAR2_GPIO_DSP_DMICCLK2 0x008A
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#define LOCHNAGAR2_GPIO_DSP_DMICDAT2 0x008B
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#define LOCHNAGAR2_GPIO_I2C2_SCL 0x008C
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#define LOCHNAGAR2_GPIO_I2C2_SDA 0x008D
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#define LOCHNAGAR2_GPIO_I2C3_SCL 0x008E
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#define LOCHNAGAR2_GPIO_I2C3_SDA 0x008F
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#define LOCHNAGAR2_GPIO_I2C4_SCL 0x0090
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#define LOCHNAGAR2_GPIO_I2C4_SDA 0x0091
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#define LOCHNAGAR2_GPIO_DSP_STANDBY 0x0092
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#define LOCHNAGAR2_GPIO_CDC_MCLK1 0x0093
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#define LOCHNAGAR2_GPIO_CDC_MCLK2 0x0094
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#define LOCHNAGAR2_GPIO_DSP_CLKIN 0x0095
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#define LOCHNAGAR2_GPIO_PSIA1_MCLK 0x0096
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#define LOCHNAGAR2_GPIO_PSIA2_MCLK 0x0097
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#define LOCHNAGAR2_GPIO_GF_GPIO1 0x0098
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#define LOCHNAGAR2_GPIO_GF_GPIO5 0x0099
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#define LOCHNAGAR2_GPIO_DSP_GPIO20 0x009A
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#define LOCHNAGAR2_GPIO_CHANNEL1 0x00B9
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#define LOCHNAGAR2_GPIO_CHANNEL2 0x00BA
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#define LOCHNAGAR2_GPIO_CHANNEL3 0x00BB
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#define LOCHNAGAR2_GPIO_CHANNEL4 0x00BC
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#define LOCHNAGAR2_GPIO_CHANNEL5 0x00BD
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#define LOCHNAGAR2_GPIO_CHANNEL6 0x00BE
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#define LOCHNAGAR2_GPIO_CHANNEL7 0x00BF
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#define LOCHNAGAR2_GPIO_CHANNEL8 0x00C0
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#define LOCHNAGAR2_GPIO_CHANNEL9 0x00C1
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#define LOCHNAGAR2_GPIO_CHANNEL10 0x00C2
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#define LOCHNAGAR2_GPIO_CHANNEL11 0x00C3
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#define LOCHNAGAR2_GPIO_CHANNEL12 0x00C4
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#define LOCHNAGAR2_GPIO_CHANNEL13 0x00C5
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#define LOCHNAGAR2_GPIO_CHANNEL14 0x00C6
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#define LOCHNAGAR2_GPIO_CHANNEL15 0x00C7
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#define LOCHNAGAR2_GPIO_CHANNEL16 0x00C8
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#define LOCHNAGAR2_MINICARD_RESETS 0x00DF
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#define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 0x00E3
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#define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 0x00E4
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#define LOCHNAGAR2_COMMS_CTRL4 0x00F0
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#define LOCHNAGAR2_SPDIF_CTRL 0x00FE
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#define LOCHNAGAR2_IMON_CTRL1 0x0108
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#define LOCHNAGAR2_IMON_CTRL2 0x0109
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#define LOCHNAGAR2_IMON_CTRL3 0x010A
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#define LOCHNAGAR2_IMON_CTRL4 0x010B
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#define LOCHNAGAR2_IMON_DATA1 0x010C
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#define LOCHNAGAR2_IMON_DATA2 0x010D
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#define LOCHNAGAR2_POWER_CTRL 0x0116
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#define LOCHNAGAR2_MICVDD_CTRL1 0x0119
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#define LOCHNAGAR2_MICVDD_CTRL2 0x011B
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#define LOCHNAGAR2_VDDCORE_CDC_CTRL1 0x011E
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#define LOCHNAGAR2_VDDCORE_CDC_CTRL2 0x0120
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#define LOCHNAGAR2_SOUNDCARD_AIF_CTRL 0x0180
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/* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */
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#define LOCHNAGAR2_AIF_ENA_MASK 0x8000
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#define LOCHNAGAR2_AIF_ENA_SHIFT 15
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#define LOCHNAGAR2_AIF_LRCLK_DIR_MASK 0x4000
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#define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT 14
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#define LOCHNAGAR2_AIF_BCLK_DIR_MASK 0x2000
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#define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT 13
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#define LOCHNAGAR2_AIF_SRC_MASK 0x00FF
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#define LOCHNAGAR2_AIF_SRC_SHIFT 0
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/* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */
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#define LOCHNAGAR2_CLK_ENA_MASK 0x8000
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#define LOCHNAGAR2_CLK_ENA_SHIFT 15
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#define LOCHNAGAR2_CLK_SRC_MASK 0x00FF
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#define LOCHNAGAR2_CLK_SRC_SHIFT 0
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/* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */
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#define LOCHNAGAR2_GPIO_SRC_MASK 0x00FF
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#define LOCHNAGAR2_GPIO_SRC_SHIFT 0
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/* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */
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#define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK 0x8000
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#define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT 15
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#define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK 0x00FF
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#define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT 0
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/* (0x00DF) MINICARD_RESETS */
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#define LOCHNAGAR2_DSP_RESET_MASK 0x0002
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#define LOCHNAGAR2_DSP_RESET_SHIFT 1
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#define LOCHNAGAR2_CDC_RESET_MASK 0x0001
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#define LOCHNAGAR2_CDC_RESET_SHIFT 0
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/* (0x00E3) ANALOGUE_PATH_CTRL1 */
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#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK 0x8000
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#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT 15
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#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK 0x4000
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#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT 14
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/* (0x00E4) ANALOGUE_PATH_CTRL2 */
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#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK 0x0080
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#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT 7
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#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK 0x0040
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#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT 6
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#define LOCHNAGAR2_P2_MICBIAS_SRC_MASK 0x0038
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#define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT 3
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#define LOCHNAGAR2_P1_MICBIAS_SRC_MASK 0x0007
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#define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT 0
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/* (0x00F0) COMMS_CTRL4 */
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#define LOCHNAGAR2_CDC_CIF1MODE_MASK 0x0001
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#define LOCHNAGAR2_CDC_CIF1MODE_SHIFT 0
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/* (0x00FE) SPDIF_CTRL */
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#define LOCHNAGAR2_SPDIF_HWMODE_MASK 0x0008
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#define LOCHNAGAR2_SPDIF_HWMODE_SHIFT 3
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#define LOCHNAGAR2_SPDIF_RESET_MASK 0x0001
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#define LOCHNAGAR2_SPDIF_RESET_SHIFT 0
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/* (0x0108) IMON_CTRL1 */
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#define LOCHNAGAR2_IMON_ENA_MASK 0x8000
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#define LOCHNAGAR2_IMON_ENA_SHIFT 15
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#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK 0x03FC
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#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT 2
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#define LOCHNAGAR2_IMON_MODE_SEL_MASK 0x0003
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#define LOCHNAGAR2_IMON_MODE_SEL_SHIFT 0
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/* (0x0109) IMON_CTRL2 */
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#define LOCHNAGAR2_IMON_FSR_MASK 0x03FF
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#define LOCHNAGAR2_IMON_FSR_SHIFT 0
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/* (0x010A) IMON_CTRL3 */
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#define LOCHNAGAR2_IMON_DONE_MASK 0x0004
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#define LOCHNAGAR2_IMON_DONE_SHIFT 2
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#define LOCHNAGAR2_IMON_CONFIGURE_MASK 0x0002
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#define LOCHNAGAR2_IMON_CONFIGURE_SHIFT 1
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#define LOCHNAGAR2_IMON_MEASURE_MASK 0x0001
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#define LOCHNAGAR2_IMON_MEASURE_SHIFT 0
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/* (0x010B) IMON_CTRL4 */
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#define LOCHNAGAR2_IMON_DATA_REQ_MASK 0x0080
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#define LOCHNAGAR2_IMON_DATA_REQ_SHIFT 7
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#define LOCHNAGAR2_IMON_CH_SEL_MASK 0x0070
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#define LOCHNAGAR2_IMON_CH_SEL_SHIFT 4
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#define LOCHNAGAR2_IMON_DATA_RDY_MASK 0x0008
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#define LOCHNAGAR2_IMON_DATA_RDY_SHIFT 3
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#define LOCHNAGAR2_IMON_CH_SRC_MASK 0x0007
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#define LOCHNAGAR2_IMON_CH_SRC_SHIFT 0
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/* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */
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#define LOCHNAGAR2_IMON_DATA_MASK 0xFFFF
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#define LOCHNAGAR2_IMON_DATA_SHIFT 0
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/* (0x0116) POWER_CTRL */
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#define LOCHNAGAR2_PWR_ENA_MASK 0x0001
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#define LOCHNAGAR2_PWR_ENA_SHIFT 0
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/* (0x0119) MICVDD_CTRL1 */
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#define LOCHNAGAR2_MICVDD_REG_ENA_MASK 0x8000
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#define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT 15
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/* (0x011B) MICVDD_CTRL2 */
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#define LOCHNAGAR2_MICVDD_VSEL_MASK 0x001F
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#define LOCHNAGAR2_MICVDD_VSEL_SHIFT 0
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/* (0x011E) VDDCORE_CDC_CTRL1 */
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#define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK 0x8000
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#define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT 15
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/* (0x0120) VDDCORE_CDC_CTRL2 */
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#define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK 0x007F
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#define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT 0
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#endif
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