2018-08-30 20:48:06 +07:00
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2018 Intel Corporation
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*/
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#include <linux/random.h>
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#include "../i915_selftest.h"
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2019-04-26 23:33:36 +07:00
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#include "igt_gem_utils.h"
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2018-08-30 20:48:06 +07:00
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#include "igt_flush_test.h"
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2019-04-26 23:33:36 +07:00
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#include "mock_context.h"
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2018-08-30 20:48:06 +07:00
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static int switch_to_context(struct drm_i915_private *i915,
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struct i915_gem_context *ctx)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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for_each_engine(engine, i915, id) {
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struct i915_request *rq;
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2019-04-26 23:33:36 +07:00
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rq = igt_request_alloc(ctx, engine);
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drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 03:07:17 +07:00
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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2018-08-30 20:48:06 +07:00
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i915_request_add(rq);
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}
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drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 03:07:17 +07:00
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return 0;
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2018-08-30 20:48:06 +07:00
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}
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static void trash_stolen(struct drm_i915_private *i915)
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{
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struct i915_ggtt *ggtt = &i915->ggtt;
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const u64 slot = ggtt->error_capture.start;
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const resource_size_t size = resource_size(&i915->dsm);
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unsigned long page;
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u32 prng = 0x12345678;
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for (page = 0; page < size; page += PAGE_SIZE) {
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const dma_addr_t dma = i915->dsm.start + page;
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u32 __iomem *s;
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int x;
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ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
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s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
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for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
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prng = next_pseudo_random32(prng);
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iowrite32(prng, &s[x]);
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}
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io_mapping_unmap_atomic(s);
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}
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ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
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}
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static void simulate_hibernate(struct drm_i915_private *i915)
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{
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2019-01-14 21:21:22 +07:00
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intel_wakeref_t wakeref;
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wakeref = intel_runtime_pm_get(i915);
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2018-08-30 20:48:06 +07:00
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/*
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* As a final sting in the tail, invalidate stolen. Under a real S4,
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* stolen is lost and needs to be refilled on resume. However, under
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* CI we merely do S4-device testing (as full S4 is too unreliable
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* for automated testing across a cluster), so to simulate the effect
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* of stolen being trashed across S4, we trash it ourselves.
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*/
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trash_stolen(i915);
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2019-01-14 21:21:22 +07:00
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intel_runtime_pm_put(i915, wakeref);
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2018-08-30 20:48:06 +07:00
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}
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static int pm_prepare(struct drm_i915_private *i915)
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{
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2019-03-08 16:36:54 +07:00
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i915_gem_suspend(i915);
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2018-08-30 20:48:06 +07:00
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2019-03-08 16:36:54 +07:00
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return 0;
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2018-08-30 20:48:06 +07:00
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}
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static void pm_suspend(struct drm_i915_private *i915)
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{
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2019-01-14 21:21:22 +07:00
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intel_wakeref_t wakeref;
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2019-01-14 21:21:23 +07:00
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with_intel_runtime_pm(i915, wakeref) {
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i915_gem_suspend_gtt_mappings(i915);
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i915_gem_suspend_late(i915);
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}
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2018-08-30 20:48:06 +07:00
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}
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static void pm_hibernate(struct drm_i915_private *i915)
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{
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2019-01-14 21:21:22 +07:00
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intel_wakeref_t wakeref;
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2019-01-14 21:21:23 +07:00
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with_intel_runtime_pm(i915, wakeref) {
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i915_gem_suspend_gtt_mappings(i915);
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2018-08-30 20:48:06 +07:00
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2019-01-14 21:21:23 +07:00
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i915_gem_freeze(i915);
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i915_gem_freeze_late(i915);
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}
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2018-08-30 20:48:06 +07:00
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}
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static void pm_resume(struct drm_i915_private *i915)
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{
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2019-01-14 21:21:22 +07:00
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intel_wakeref_t wakeref;
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2018-08-30 20:48:06 +07:00
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/*
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* Both suspend and hibernate follow the same wakeup path and assume
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* that runtime-pm just works.
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*/
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2019-01-14 21:21:23 +07:00
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with_intel_runtime_pm(i915, wakeref) {
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drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-25 03:07:17 +07:00
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intel_gt_sanitize(i915, false);
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2019-01-14 21:21:23 +07:00
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i915_gem_sanitize(i915);
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i915_gem_resume(i915);
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}
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2018-08-30 20:48:06 +07:00
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}
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static int igt_gem_suspend(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct i915_gem_context *ctx;
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struct drm_file *file;
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int err;
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file = mock_file(i915);
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if (IS_ERR(file))
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return PTR_ERR(file);
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err = -ENOMEM;
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mutex_lock(&i915->drm.struct_mutex);
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ctx = live_context(i915, file);
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if (!IS_ERR(ctx))
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err = switch_to_context(i915, ctx);
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mutex_unlock(&i915->drm.struct_mutex);
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if (err)
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goto out;
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err = pm_prepare(i915);
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if (err)
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goto out;
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pm_suspend(i915);
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/* Here be dragons! Note that with S3RST any S3 may become S4! */
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simulate_hibernate(i915);
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pm_resume(i915);
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mutex_lock(&i915->drm.struct_mutex);
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err = switch_to_context(i915, ctx);
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if (igt_flush_test(i915, I915_WAIT_LOCKED))
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err = -EIO;
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mutex_unlock(&i915->drm.struct_mutex);
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out:
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mock_file_free(i915, file);
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return err;
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}
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static int igt_gem_hibernate(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct i915_gem_context *ctx;
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struct drm_file *file;
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int err;
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file = mock_file(i915);
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if (IS_ERR(file))
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return PTR_ERR(file);
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err = -ENOMEM;
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mutex_lock(&i915->drm.struct_mutex);
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ctx = live_context(i915, file);
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if (!IS_ERR(ctx))
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err = switch_to_context(i915, ctx);
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mutex_unlock(&i915->drm.struct_mutex);
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if (err)
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goto out;
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err = pm_prepare(i915);
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if (err)
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goto out;
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pm_hibernate(i915);
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/* Here be dragons! */
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simulate_hibernate(i915);
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pm_resume(i915);
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mutex_lock(&i915->drm.struct_mutex);
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err = switch_to_context(i915, ctx);
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if (igt_flush_test(i915, I915_WAIT_LOCKED))
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err = -EIO;
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mutex_unlock(&i915->drm.struct_mutex);
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out:
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mock_file_free(i915, file);
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return err;
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}
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int i915_gem_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_gem_suspend),
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SUBTEST(igt_gem_hibernate),
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};
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2019-04-13 19:58:20 +07:00
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if (i915_terminally_wedged(i915))
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return 0;
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2018-08-30 20:48:06 +07:00
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return i915_subtests(tests, i915);
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}
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