2019-04-16 15:34:32 +07:00
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// SPDX-License-Identifier: GPL-2.0+
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2010-08-11 08:02:13 +07:00
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2010 Orex Computed Radiography
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*/
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/*
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* This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
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* to implement a Linux RTC. Times and alarms are truncated to seconds.
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* Since the RTC framework performs API locking via rtc->ops_lock the
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* only simultaneous accesses we need to deal with is updating DryIce
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* registers while servicing an alarm.
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*
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* Note that reading the DSR (DryIce Status Register) automatically clears
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* the WCF (Write Complete Flag). All DryIce writes are synchronized to the
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* LP (Low Power) domain and set the WCF upon completion. Writes to the
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* DIER (DryIce Interrupt Enable Register) are the only exception. These
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* occur at normal bus speeds and do not set WCF. Periodic interrupts are
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* not supported by the hardware.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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2011-09-15 06:21:47 +07:00
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#include <linux/sched.h>
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2012-12-21 06:05:19 +07:00
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#include <linux/spinlock.h>
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2010-08-11 08:02:13 +07:00
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#include <linux/workqueue.h>
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2012-12-18 07:02:23 +07:00
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#include <linux/of.h>
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2010-08-11 08:02:13 +07:00
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/* DryIce Register Definitions */
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#define DTCMR 0x00 /* Time Counter MSB Reg */
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#define DTCLR 0x04 /* Time Counter LSB Reg */
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#define DCAMR 0x08 /* Clock Alarm MSB Reg */
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#define DCALR 0x0c /* Clock Alarm LSB Reg */
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#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
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#define DCR 0x10 /* Control Reg */
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2015-02-14 05:40:45 +07:00
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#define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
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#define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
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#define DCR_KSSL (1 << 27) /* Key-select soft lock */
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#define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */
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#define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */
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#define DCR_TCHL (1 << 18) /* Timer-counter hard lock */
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#define DCR_TCSL (1 << 17) /* Timer-counter soft lock */
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#define DCR_FSHL (1 << 16) /* Failure state hard lock */
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2010-08-11 08:02:13 +07:00
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#define DCR_TCE (1 << 3) /* Time Counter Enable */
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2015-02-14 05:40:45 +07:00
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#define DCR_MCE (1 << 2) /* Monotonic Counter Enable */
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2010-08-11 08:02:13 +07:00
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#define DSR 0x14 /* Status Reg */
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2015-02-14 05:40:45 +07:00
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#define DSR_WTD (1 << 23) /* Wire-mesh tamper detected */
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#define DSR_ETBD (1 << 22) /* External tamper B detected */
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#define DSR_ETAD (1 << 21) /* External tamper A detected */
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#define DSR_EBD (1 << 20) /* External boot detected */
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#define DSR_SAD (1 << 19) /* SCC alarm detected */
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2016-11-19 20:03:33 +07:00
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#define DSR_TTD (1 << 18) /* Temperature tamper detected */
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2015-02-14 05:40:45 +07:00
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#define DSR_CTD (1 << 17) /* Clock tamper detected */
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#define DSR_VTD (1 << 16) /* Voltage tamper detected */
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#define DSR_WBF (1 << 10) /* Write Busy Flag (synchronous) */
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#define DSR_WNF (1 << 9) /* Write Next Flag (synchronous) */
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#define DSR_WCF (1 << 8) /* Write Complete Flag (synchronous)*/
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2010-08-11 08:02:13 +07:00
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#define DSR_WEF (1 << 7) /* Write Error Flag */
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#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
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2015-02-14 05:40:45 +07:00
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#define DSR_MCO (1 << 3) /* monotonic counter overflow */
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#define DSR_TCO (1 << 2) /* time counter overflow */
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2010-08-11 08:02:13 +07:00
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#define DSR_NVF (1 << 1) /* Non-Valid Flag */
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#define DSR_SVF (1 << 0) /* Security Violation Flag */
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2015-02-14 05:40:45 +07:00
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#define DIER 0x18 /* Interrupt Enable Reg (synchronous) */
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2010-08-11 08:02:13 +07:00
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#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
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#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
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#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
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#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
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2015-02-14 05:40:45 +07:00
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#define DIER_SVIE (1 << 0) /* Security-violation Interrupt Enable */
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#define DMCR 0x1c /* DryIce Monotonic Counter Reg */
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#define DTCR 0x28 /* DryIce Tamper Configuration Reg */
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#define DTCR_MOE (1 << 9) /* monotonic overflow enabled */
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#define DTCR_TOE (1 << 8) /* time overflow enabled */
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#define DTCR_WTE (1 << 7) /* wire-mesh tamper enabled */
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#define DTCR_ETBE (1 << 6) /* external B tamper enabled */
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#define DTCR_ETAE (1 << 5) /* external A tamper enabled */
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#define DTCR_EBE (1 << 4) /* external boot tamper enabled */
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#define DTCR_SAIE (1 << 3) /* SCC enabled */
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#define DTCR_TTE (1 << 2) /* temperature tamper enabled */
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#define DTCR_CTE (1 << 1) /* clock tamper enabled */
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#define DTCR_VTE (1 << 0) /* voltage tamper enabled */
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#define DGPR 0x3c /* DryIce General Purpose Reg */
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2010-08-11 08:02:13 +07:00
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/**
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* struct imxdi_dev - private imxdi rtc data
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* @pdev: pionter to platform dev
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* @rtc: pointer to rtc struct
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* @ioaddr: IO registers pointer
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* @clk: input reference clock
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* @dsr: copy of the DSR register
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* @irq_lock: interrupt enable register (DIER) lock
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* @write_wait: registers write complete queue
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* @write_mutex: serialize registers write
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* @work: schedule alarm work
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*/
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struct imxdi_dev {
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struct platform_device *pdev;
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struct rtc_device *rtc;
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void __iomem *ioaddr;
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struct clk *clk;
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u32 dsr;
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spinlock_t irq_lock;
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wait_queue_head_t write_wait;
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struct mutex write_mutex;
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struct work_struct work;
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};
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2015-04-27 20:59:48 +07:00
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/* Some background:
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*
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* The DryIce unit is a complex security/tamper monitor device. To be able do
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* its job in a useful manner it runs a bigger statemachine to bring it into
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* security/tamper failure state and once again to bring it out of this state.
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*
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* This unit can be in one of three states:
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*
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* - "NON-VALID STATE"
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* always after the battery power was removed
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* - "FAILURE STATE"
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* if one of the enabled security events has happened
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* - "VALID STATE"
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* if the unit works as expected
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*
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* Everything stops when the unit enters the failure state including the RTC
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* counter (to be able to detect the time the security event happened).
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*
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* The following events (when enabled) let the DryIce unit enter the failure
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* state:
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*
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* - wire-mesh-tamper detect
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* - external tamper B detect
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* - external tamper A detect
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* - temperature tamper detect
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* - clock tamper detect
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* - voltage tamper detect
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* - RTC counter overflow
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* - monotonic counter overflow
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* - external boot
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*
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* If we find the DryIce unit in "FAILURE STATE" and the TDCHL cleared, we
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* can only detect this state. In this case the unit is completely locked and
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* must force a second "SYSTEM POR" to bring the DryIce into the
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* "NON-VALID STATE" + "FAILURE STATE" where a recovery is possible.
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* If the TDCHL is set in the "FAILURE STATE" we are out of luck. In this case
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* a battery power cycle is required.
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*
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* In the "NON-VALID STATE" + "FAILURE STATE" we can clear the "FAILURE STATE"
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* and recover the DryIce unit. By clearing the "NON-VALID STATE" as the last
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* task, we bring back this unit into life.
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*/
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2015-04-27 20:59:49 +07:00
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/*
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* Do a write into the unit without interrupt support.
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* We do not need to check the WEF here, because the only reason this kind of
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* write error can happen is if we write to the unit twice within the 122 us
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* interval. This cannot happen, since we are using this function only while
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* setting up the unit.
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*/
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static void di_write_busy_wait(const struct imxdi_dev *imxdi, u32 val,
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unsigned reg)
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{
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/* do the register write */
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writel(val, imxdi->ioaddr + reg);
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/*
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* now it takes four 32,768 kHz clock cycles to take
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* the change into effect = 122 us
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*/
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usleep_range(130, 200);
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}
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static void di_report_tamper_info(struct imxdi_dev *imxdi, u32 dsr)
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{
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u32 dtcr;
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dtcr = readl(imxdi->ioaddr + DTCR);
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dev_emerg(&imxdi->pdev->dev, "DryIce tamper event detected\n");
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/* the following flags force a transition into the "FAILURE STATE" */
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if (dsr & DSR_VTD)
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dev_emerg(&imxdi->pdev->dev, "%sVoltage Tamper Event\n",
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dtcr & DTCR_VTE ? "" : "Spurious ");
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if (dsr & DSR_CTD)
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dev_emerg(&imxdi->pdev->dev, "%s32768 Hz Clock Tamper Event\n",
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dtcr & DTCR_CTE ? "" : "Spurious ");
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if (dsr & DSR_TTD)
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dev_emerg(&imxdi->pdev->dev, "%sTemperature Tamper Event\n",
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dtcr & DTCR_TTE ? "" : "Spurious ");
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if (dsr & DSR_SAD)
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dev_emerg(&imxdi->pdev->dev,
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"%sSecure Controller Alarm Event\n",
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dtcr & DTCR_SAIE ? "" : "Spurious ");
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if (dsr & DSR_EBD)
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dev_emerg(&imxdi->pdev->dev, "%sExternal Boot Tamper Event\n",
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dtcr & DTCR_EBE ? "" : "Spurious ");
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if (dsr & DSR_ETAD)
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dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper A Event\n",
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dtcr & DTCR_ETAE ? "" : "Spurious ");
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if (dsr & DSR_ETBD)
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dev_emerg(&imxdi->pdev->dev, "%sExternal Tamper B Event\n",
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dtcr & DTCR_ETBE ? "" : "Spurious ");
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if (dsr & DSR_WTD)
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dev_emerg(&imxdi->pdev->dev, "%sWire-mesh Tamper Event\n",
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dtcr & DTCR_WTE ? "" : "Spurious ");
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if (dsr & DSR_MCO)
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dev_emerg(&imxdi->pdev->dev,
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"%sMonotonic-counter Overflow Event\n",
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dtcr & DTCR_MOE ? "" : "Spurious ");
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if (dsr & DSR_TCO)
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dev_emerg(&imxdi->pdev->dev, "%sTimer-counter Overflow Event\n",
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dtcr & DTCR_TOE ? "" : "Spurious ");
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}
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static void di_what_is_to_be_done(struct imxdi_dev *imxdi,
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const char *power_supply)
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{
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dev_emerg(&imxdi->pdev->dev, "Please cycle the %s power supply in order to get the DryIce/RTC unit working again\n",
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power_supply);
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}
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static int di_handle_failure_state(struct imxdi_dev *imxdi, u32 dsr)
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{
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u32 dcr;
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dev_dbg(&imxdi->pdev->dev, "DSR register reports: %08X\n", dsr);
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/* report the cause */
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di_report_tamper_info(imxdi, dsr);
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dcr = readl(imxdi->ioaddr + DCR);
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if (dcr & DCR_FSHL) {
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/* we are out of luck */
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di_what_is_to_be_done(imxdi, "battery");
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return -ENODEV;
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}
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/*
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* with the next SYSTEM POR we will transit from the "FAILURE STATE"
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* into the "NON-VALID STATE" + "FAILURE STATE"
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*/
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di_what_is_to_be_done(imxdi, "main");
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return -ENODEV;
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}
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static int di_handle_valid_state(struct imxdi_dev *imxdi, u32 dsr)
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{
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/* initialize alarm */
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di_write_busy_wait(imxdi, DCAMR_UNSET, DCAMR);
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di_write_busy_wait(imxdi, 0, DCALR);
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/* clear alarm flag */
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if (dsr & DSR_CAF)
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di_write_busy_wait(imxdi, DSR_CAF, DSR);
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return 0;
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}
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static int di_handle_invalid_state(struct imxdi_dev *imxdi, u32 dsr)
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{
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u32 dcr, sec;
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/*
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* lets disable all sources which can force the DryIce unit into
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* the "FAILURE STATE" for now
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*/
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di_write_busy_wait(imxdi, 0x00000000, DTCR);
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/* and lets protect them at runtime from any change */
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di_write_busy_wait(imxdi, DCR_TDCSL, DCR);
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sec = readl(imxdi->ioaddr + DTCMR);
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if (sec != 0)
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dev_warn(&imxdi->pdev->dev,
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2015-11-28 23:38:40 +07:00
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"The security violation has happened at %u seconds\n",
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2015-04-27 20:59:49 +07:00
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sec);
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/*
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* the timer cannot be set/modified if
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* - the TCHL or TCSL bit is set in DCR
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*/
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dcr = readl(imxdi->ioaddr + DCR);
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if (!(dcr & DCR_TCE)) {
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if (dcr & DCR_TCHL) {
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/* we are out of luck */
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di_what_is_to_be_done(imxdi, "battery");
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return -ENODEV;
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}
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if (dcr & DCR_TCSL) {
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di_what_is_to_be_done(imxdi, "main");
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return -ENODEV;
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}
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}
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/*
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* - the timer counter stops/is stopped if
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* - its overflow flag is set (TCO in DSR)
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* -> clear overflow bit to make it count again
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* - NVF is set in DSR
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* -> clear non-valid bit to make it count again
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* - its TCE (DCR) is cleared
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* -> set TCE to make it count
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* - it was never set before
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* -> write a time into it (required again if the NVF was set)
|
|
|
|
*/
|
|
|
|
/* state handled */
|
|
|
|
di_write_busy_wait(imxdi, DSR_NVF, DSR);
|
|
|
|
/* clear overflow flag */
|
|
|
|
di_write_busy_wait(imxdi, DSR_TCO, DSR);
|
|
|
|
/* enable the counter */
|
|
|
|
di_write_busy_wait(imxdi, dcr | DCR_TCE, DCR);
|
|
|
|
/* set and trigger it to make it count */
|
|
|
|
di_write_busy_wait(imxdi, sec, DTCMR);
|
|
|
|
|
|
|
|
/* now prepare for the valid state */
|
|
|
|
return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int di_handle_invalid_and_failure_state(struct imxdi_dev *imxdi, u32 dsr)
|
|
|
|
{
|
|
|
|
u32 dcr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* now we must first remove the tamper sources in order to get the
|
|
|
|
* device out of the "FAILURE STATE"
|
|
|
|
* To disable any of the following sources we need to modify the DTCR
|
|
|
|
*/
|
|
|
|
if (dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD | DSR_EBD | DSR_SAD |
|
|
|
|
DSR_TTD | DSR_CTD | DSR_VTD | DSR_MCO | DSR_TCO)) {
|
|
|
|
dcr = __raw_readl(imxdi->ioaddr + DCR);
|
|
|
|
if (dcr & DCR_TDCHL) {
|
|
|
|
/*
|
|
|
|
* the tamper register is locked. We cannot disable the
|
|
|
|
* tamper detection. The TDCHL can only be reset by a
|
|
|
|
* DRYICE POR, but we cannot force a DRYICE POR in
|
|
|
|
* softwere because we are still in "FAILURE STATE".
|
|
|
|
* We need a DRYICE POR via battery power cycling....
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* out of luck!
|
|
|
|
* we cannot disable them without a DRYICE POR
|
|
|
|
*/
|
|
|
|
di_what_is_to_be_done(imxdi, "battery");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
if (dcr & DCR_TDCSL) {
|
|
|
|
/* a soft lock can be removed by a SYSTEM POR */
|
|
|
|
di_what_is_to_be_done(imxdi, "main");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* disable all sources */
|
|
|
|
di_write_busy_wait(imxdi, 0x00000000, DTCR);
|
|
|
|
|
|
|
|
/* clear the status bits now */
|
|
|
|
di_write_busy_wait(imxdi, dsr & (DSR_WTD | DSR_ETBD | DSR_ETAD |
|
|
|
|
DSR_EBD | DSR_SAD | DSR_TTD | DSR_CTD | DSR_VTD |
|
|
|
|
DSR_MCO | DSR_TCO), DSR);
|
|
|
|
|
|
|
|
dsr = readl(imxdi->ioaddr + DSR);
|
|
|
|
if ((dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |
|
|
|
|
DSR_WCF | DSR_WEF)) != 0)
|
|
|
|
dev_warn(&imxdi->pdev->dev,
|
|
|
|
"There are still some sources of pain in DSR: %08x!\n",
|
|
|
|
dsr & ~(DSR_NVF | DSR_SVF | DSR_WBF | DSR_WNF |
|
|
|
|
DSR_WCF | DSR_WEF));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* now we are trying to clear the "Security-violation flag" to
|
|
|
|
* get the DryIce out of this state
|
|
|
|
*/
|
|
|
|
di_write_busy_wait(imxdi, DSR_SVF, DSR);
|
|
|
|
|
|
|
|
/* success? */
|
|
|
|
dsr = readl(imxdi->ioaddr + DSR);
|
|
|
|
if (dsr & DSR_SVF) {
|
|
|
|
dev_crit(&imxdi->pdev->dev,
|
|
|
|
"Cannot clear the security violation flag. We are ending up in an endless loop!\n");
|
|
|
|
/* last resort */
|
|
|
|
di_what_is_to_be_done(imxdi, "battery");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* now we have left the "FAILURE STATE" and ending up in the
|
|
|
|
* "NON-VALID STATE" time to recover everything
|
|
|
|
*/
|
|
|
|
return di_handle_invalid_state(imxdi, dsr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int di_handle_state(struct imxdi_dev *imxdi)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
u32 dsr;
|
|
|
|
|
|
|
|
dsr = readl(imxdi->ioaddr + DSR);
|
|
|
|
|
|
|
|
switch (dsr & (DSR_NVF | DSR_SVF)) {
|
|
|
|
case DSR_NVF:
|
|
|
|
dev_warn(&imxdi->pdev->dev, "Invalid stated unit detected\n");
|
|
|
|
rc = di_handle_invalid_state(imxdi, dsr);
|
|
|
|
break;
|
|
|
|
case DSR_SVF:
|
|
|
|
dev_warn(&imxdi->pdev->dev, "Failure stated unit detected\n");
|
|
|
|
rc = di_handle_failure_state(imxdi, dsr);
|
|
|
|
break;
|
|
|
|
case DSR_NVF | DSR_SVF:
|
|
|
|
dev_warn(&imxdi->pdev->dev,
|
|
|
|
"Failure+Invalid stated unit detected\n");
|
|
|
|
rc = di_handle_invalid_and_failure_state(imxdi, dsr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_notice(&imxdi->pdev->dev, "Unlocked unit detected\n");
|
|
|
|
rc = di_handle_valid_state(imxdi, dsr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2010-08-11 08:02:13 +07:00
|
|
|
/*
|
|
|
|
* enable a dryice interrupt
|
|
|
|
*/
|
|
|
|
static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&imxdi->irq_lock, flags);
|
2015-04-27 20:59:47 +07:00
|
|
|
writel(readl(imxdi->ioaddr + DIER) | intr,
|
|
|
|
imxdi->ioaddr + DIER);
|
2010-08-11 08:02:13 +07:00
|
|
|
spin_unlock_irqrestore(&imxdi->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* disable a dryice interrupt
|
|
|
|
*/
|
|
|
|
static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&imxdi->irq_lock, flags);
|
2015-04-27 20:59:47 +07:00
|
|
|
writel(readl(imxdi->ioaddr + DIER) & ~intr,
|
|
|
|
imxdi->ioaddr + DIER);
|
2010-08-11 08:02:13 +07:00
|
|
|
spin_unlock_irqrestore(&imxdi->irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function attempts to clear the dryice write-error flag.
|
|
|
|
*
|
|
|
|
* A dryice write error is similar to a bus fault and should not occur in
|
|
|
|
* normal operation. Clearing the flag requires another write, so the root
|
|
|
|
* cause of the problem may need to be fixed before the flag can be cleared.
|
|
|
|
*/
|
|
|
|
static void clear_write_error(struct imxdi_dev *imxdi)
|
|
|
|
{
|
|
|
|
int cnt;
|
|
|
|
|
|
|
|
dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
|
|
|
|
|
|
|
|
/* clear the write error flag */
|
2015-04-27 20:59:47 +07:00
|
|
|
writel(DSR_WEF, imxdi->ioaddr + DSR);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
/* wait for it to take effect */
|
|
|
|
for (cnt = 0; cnt < 1000; cnt++) {
|
2015-04-27 20:59:47 +07:00
|
|
|
if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
|
2010-08-11 08:02:13 +07:00
|
|
|
return;
|
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
dev_err(&imxdi->pdev->dev,
|
|
|
|
"ERROR: Cannot clear write-error flag!\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write a dryice register and wait until it completes.
|
|
|
|
*
|
|
|
|
* This function uses interrupts to determine when the
|
|
|
|
* write has completed.
|
|
|
|
*/
|
|
|
|
static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
/* serialize register writes */
|
|
|
|
mutex_lock(&imxdi->write_mutex);
|
|
|
|
|
|
|
|
/* enable the write-complete interrupt */
|
|
|
|
di_int_enable(imxdi, DIER_WCIE);
|
|
|
|
|
|
|
|
imxdi->dsr = 0;
|
|
|
|
|
|
|
|
/* do the register write */
|
2015-04-27 20:59:47 +07:00
|
|
|
writel(val, imxdi->ioaddr + reg);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
/* wait for the write to finish */
|
|
|
|
ret = wait_event_interruptible_timeout(imxdi->write_wait,
|
|
|
|
imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
|
|
|
|
if (ret < 0) {
|
|
|
|
rc = ret;
|
|
|
|
goto out;
|
|
|
|
} else if (ret == 0) {
|
|
|
|
dev_warn(&imxdi->pdev->dev,
|
|
|
|
"Write-wait timeout "
|
|
|
|
"val = 0x%08x reg = 0x%08x\n", val, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check for write error */
|
|
|
|
if (imxdi->dsr & DSR_WEF) {
|
|
|
|
clear_write_error(imxdi);
|
|
|
|
rc = -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&imxdi->write_mutex);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* read the seconds portion of the current time from the dryice time counter
|
|
|
|
*/
|
|
|
|
static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
|
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
|
|
|
|
unsigned long now;
|
|
|
|
|
2015-04-27 20:59:47 +07:00
|
|
|
now = readl(imxdi->ioaddr + DTCMR);
|
2019-04-16 15:34:29 +07:00
|
|
|
rtc_time64_to_tm(now, tm);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* set the seconds portion of dryice time counter and clear the
|
|
|
|
* fractional part.
|
|
|
|
*/
|
2019-04-16 15:34:30 +07:00
|
|
|
static int dryice_rtc_set_time(struct device *dev, struct rtc_time *tm)
|
2010-08-11 08:02:13 +07:00
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
|
2015-04-27 20:59:51 +07:00
|
|
|
u32 dcr, dsr;
|
2010-08-11 08:02:13 +07:00
|
|
|
int rc;
|
|
|
|
|
2015-04-27 20:59:51 +07:00
|
|
|
dcr = readl(imxdi->ioaddr + DCR);
|
|
|
|
dsr = readl(imxdi->ioaddr + DSR);
|
|
|
|
|
|
|
|
if (!(dcr & DCR_TCE) || (dsr & DSR_SVF)) {
|
|
|
|
if (dcr & DCR_TCHL) {
|
|
|
|
/* we are even more out of luck */
|
|
|
|
di_what_is_to_be_done(imxdi, "battery");
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
if ((dcr & DCR_TCSL) || (dsr & DSR_SVF)) {
|
|
|
|
/* we are out of luck for now */
|
|
|
|
di_what_is_to_be_done(imxdi, "main");
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-08-11 08:02:13 +07:00
|
|
|
/* zero the fractional part first */
|
|
|
|
rc = di_write_wait(imxdi, 0, DTCLR);
|
2015-04-27 20:59:51 +07:00
|
|
|
if (rc != 0)
|
|
|
|
return rc;
|
2010-08-11 08:02:13 +07:00
|
|
|
|
2019-04-16 15:34:30 +07:00
|
|
|
rc = di_write_wait(imxdi, rtc_tm_to_time64(tm), DTCMR);
|
2015-04-27 20:59:51 +07:00
|
|
|
if (rc != 0)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
return di_write_wait(imxdi, readl(imxdi->ioaddr + DCR) | DCR_TCE, DCR);
|
2010-08-11 08:02:13 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dryice_rtc_alarm_irq_enable(struct device *dev,
|
|
|
|
unsigned int enabled)
|
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
if (enabled)
|
|
|
|
di_int_enable(imxdi, DIER_CAIE);
|
|
|
|
else
|
|
|
|
di_int_disable(imxdi, DIER_CAIE);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* read the seconds portion of the alarm register.
|
|
|
|
* the fractional part of the alarm register is always zero.
|
|
|
|
*/
|
|
|
|
static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
|
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
|
|
|
|
u32 dcamr;
|
|
|
|
|
2015-04-27 20:59:47 +07:00
|
|
|
dcamr = readl(imxdi->ioaddr + DCAMR);
|
2019-04-16 15:34:29 +07:00
|
|
|
rtc_time64_to_tm(dcamr, &alarm->time);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
/* alarm is enabled if the interrupt is enabled */
|
2015-04-27 20:59:47 +07:00
|
|
|
alarm->enabled = (readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
/* don't allow the DSR read to mess up DSR_WCF */
|
|
|
|
mutex_lock(&imxdi->write_mutex);
|
|
|
|
|
|
|
|
/* alarm is pending if the alarm flag is set */
|
2015-04-27 20:59:47 +07:00
|
|
|
alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
mutex_unlock(&imxdi->write_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* set the seconds portion of dryice alarm register
|
|
|
|
*/
|
|
|
|
static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
|
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = dev_get_drvdata(dev);
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* write the new alarm time */
|
2019-04-16 15:34:31 +07:00
|
|
|
rc = di_write_wait(imxdi, rtc_tm_to_time64(&alarm->time), DCAMR);
|
2010-08-11 08:02:13 +07:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
if (alarm->enabled)
|
|
|
|
di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
|
|
|
|
else
|
|
|
|
di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-05 23:55:05 +07:00
|
|
|
static const struct rtc_class_ops dryice_rtc_ops = {
|
2010-08-11 08:02:13 +07:00
|
|
|
.read_time = dryice_rtc_read_time,
|
2019-04-16 15:34:30 +07:00
|
|
|
.set_time = dryice_rtc_set_time,
|
2010-08-11 08:02:13 +07:00
|
|
|
.alarm_irq_enable = dryice_rtc_alarm_irq_enable,
|
|
|
|
.read_alarm = dryice_rtc_read_alarm,
|
|
|
|
.set_alarm = dryice_rtc_set_alarm,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
2017-01-04 01:49:50 +07:00
|
|
|
* interrupt handler for dryice "normal" and security violation interrupt
|
2010-08-11 08:02:13 +07:00
|
|
|
*/
|
2017-01-04 01:49:50 +07:00
|
|
|
static irqreturn_t dryice_irq(int irq, void *dev_id)
|
2010-08-11 08:02:13 +07:00
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = dev_id;
|
|
|
|
u32 dsr, dier;
|
|
|
|
irqreturn_t rc = IRQ_NONE;
|
|
|
|
|
2015-04-27 20:59:47 +07:00
|
|
|
dier = readl(imxdi->ioaddr + DIER);
|
2015-04-27 20:59:50 +07:00
|
|
|
dsr = readl(imxdi->ioaddr + DSR);
|
|
|
|
|
|
|
|
/* handle the security violation event */
|
|
|
|
if (dier & DIER_SVIE) {
|
|
|
|
if (dsr & DSR_SVF) {
|
|
|
|
/*
|
|
|
|
* Disable the interrupt when this kind of event has
|
|
|
|
* happened.
|
|
|
|
* There cannot be more than one event of this type,
|
|
|
|
* because it needs a complex state change
|
|
|
|
* including a main power cycle to get again out of
|
|
|
|
* this state.
|
|
|
|
*/
|
|
|
|
di_int_disable(imxdi, DIER_SVIE);
|
|
|
|
/* report the violation */
|
|
|
|
di_report_tamper_info(imxdi, dsr);
|
|
|
|
rc = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
/* handle write complete and write error cases */
|
2015-02-14 05:40:42 +07:00
|
|
|
if (dier & DIER_WCIE) {
|
2010-08-11 08:02:13 +07:00
|
|
|
/*If the write wait queue is empty then there is no pending
|
|
|
|
operations. It means the interrupt is for DryIce -Security.
|
|
|
|
IRQ must be returned as none.*/
|
sched/wait: Disambiguate wq_entry->task_list and wq_head->task_list naming
So I've noticed a number of instances where it was not obvious from the
code whether ->task_list was for a wait-queue head or a wait-queue entry.
Furthermore, there's a number of wait-queue users where the lists are
not for 'tasks' but other entities (poll tables, etc.), in which case
the 'task_list' name is actively confusing.
To clear this all up, name the wait-queue head and entry list structure
fields unambiguously:
struct wait_queue_head::task_list => ::head
struct wait_queue_entry::task_list => ::entry
For example, this code:
rqw->wait.task_list.next != &wait->task_list
... is was pretty unclear (to me) what it's doing, while now it's written this way:
rqw->wait.head.next != &wait->entry
... which makes it pretty clear that we are iterating a list until we see the head.
Other examples are:
list_for_each_entry_safe(pos, next, &x->task_list, task_list) {
list_for_each_entry(wq, &fence->wait.task_list, task_list) {
... where it's unclear (to me) what we are iterating, and during review it's
hard to tell whether it's trying to walk a wait-queue entry (which would be
a bug), while now it's written as:
list_for_each_entry_safe(pos, next, &x->head, entry) {
list_for_each_entry(wq, &fence->wait.head, entry) {
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-06-20 17:06:46 +07:00
|
|
|
if (list_empty_careful(&imxdi->write_wait.head))
|
2010-08-11 08:02:13 +07:00
|
|
|
return rc;
|
|
|
|
|
|
|
|
/* DSR_WCF clears itself on DSR read */
|
2015-02-14 05:40:42 +07:00
|
|
|
if (dsr & (DSR_WCF | DSR_WEF)) {
|
2010-08-11 08:02:13 +07:00
|
|
|
/* mask the interrupt */
|
|
|
|
di_int_disable(imxdi, DIER_WCIE);
|
|
|
|
|
|
|
|
/* save the dsr value for the wait queue */
|
|
|
|
imxdi->dsr |= dsr;
|
|
|
|
|
|
|
|
wake_up_interruptible(&imxdi->write_wait);
|
|
|
|
rc = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* handle the alarm case */
|
2015-02-14 05:40:42 +07:00
|
|
|
if (dier & DIER_CAIE) {
|
2010-08-11 08:02:13 +07:00
|
|
|
/* DSR_WCF clears itself on DSR read */
|
|
|
|
if (dsr & DSR_CAF) {
|
|
|
|
/* mask the interrupt */
|
|
|
|
di_int_disable(imxdi, DIER_CAIE);
|
|
|
|
|
|
|
|
/* finish alarm in user context */
|
|
|
|
schedule_work(&imxdi->work);
|
|
|
|
rc = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* post the alarm event from user context so it can sleep
|
|
|
|
* on the write completion.
|
|
|
|
*/
|
|
|
|
static void dryice_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = container_of(work,
|
|
|
|
struct imxdi_dev, work);
|
|
|
|
|
|
|
|
/* dismiss the interrupt (ignore error) */
|
|
|
|
di_write_wait(imxdi, DSR_CAF, DSR);
|
|
|
|
|
|
|
|
/* pass the alarm event to the rtc framework. */
|
|
|
|
rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* probe for dryice rtc device
|
|
|
|
*/
|
2013-04-30 06:18:24 +07:00
|
|
|
static int __init dryice_rtc_probe(struct platform_device *pdev)
|
2010-08-11 08:02:13 +07:00
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
struct imxdi_dev *imxdi;
|
2017-01-04 01:49:50 +07:00
|
|
|
int norm_irq, sec_irq;
|
2010-08-11 08:02:13 +07:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
|
|
|
|
if (!imxdi)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
imxdi->pdev = pdev;
|
|
|
|
|
2013-09-12 04:24:27 +07:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
imxdi->ioaddr = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(imxdi->ioaddr))
|
|
|
|
return PTR_ERR(imxdi->ioaddr);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
2012-10-26 03:38:11 +07:00
|
|
|
spin_lock_init(&imxdi->irq_lock);
|
|
|
|
|
2017-01-04 01:49:50 +07:00
|
|
|
norm_irq = platform_get_irq(pdev, 0);
|
|
|
|
if (norm_irq < 0)
|
|
|
|
return norm_irq;
|
|
|
|
|
|
|
|
/* the 2nd irq is the security violation irq
|
|
|
|
* make this optional, don't break the device tree ABI
|
|
|
|
*/
|
|
|
|
sec_irq = platform_get_irq(pdev, 1);
|
|
|
|
if (sec_irq <= 0)
|
|
|
|
sec_irq = IRQ_NOTCONNECTED;
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
init_waitqueue_head(&imxdi->write_wait);
|
|
|
|
|
|
|
|
INIT_WORK(&imxdi->work, dryice_work);
|
|
|
|
|
|
|
|
mutex_init(&imxdi->write_mutex);
|
|
|
|
|
2019-04-16 15:34:28 +07:00
|
|
|
imxdi->rtc = devm_rtc_allocate_device(&pdev->dev);
|
|
|
|
if (IS_ERR(imxdi->rtc))
|
|
|
|
return PTR_ERR(imxdi->rtc);
|
|
|
|
|
2013-02-22 07:45:35 +07:00
|
|
|
imxdi->clk = devm_clk_get(&pdev->dev, NULL);
|
2010-08-11 08:02:13 +07:00
|
|
|
if (IS_ERR(imxdi->clk))
|
|
|
|
return PTR_ERR(imxdi->clk);
|
2014-04-04 04:49:38 +07:00
|
|
|
rc = clk_prepare_enable(imxdi->clk);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize dryice hardware
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* mask all interrupts */
|
2015-04-27 20:59:47 +07:00
|
|
|
writel(0, imxdi->ioaddr + DIER);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
2015-04-27 20:59:49 +07:00
|
|
|
rc = di_handle_state(imxdi);
|
|
|
|
if (rc != 0)
|
|
|
|
goto err;
|
|
|
|
|
2017-01-04 01:49:50 +07:00
|
|
|
rc = devm_request_irq(&pdev->dev, norm_irq, dryice_irq,
|
|
|
|
IRQF_SHARED, pdev->name, imxdi);
|
2010-08-11 08:02:13 +07:00
|
|
|
if (rc) {
|
|
|
|
dev_warn(&pdev->dev, "interrupt not available.\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2017-01-04 01:49:50 +07:00
|
|
|
rc = devm_request_irq(&pdev->dev, sec_irq, dryice_irq,
|
|
|
|
IRQF_SHARED, pdev->name, imxdi);
|
|
|
|
if (rc) {
|
|
|
|
dev_warn(&pdev->dev, "security violation interrupt not available.\n");
|
|
|
|
/* this is not an error, see above */
|
|
|
|
}
|
|
|
|
|
2010-08-11 08:02:13 +07:00
|
|
|
platform_set_drvdata(pdev, imxdi);
|
2019-04-16 15:34:28 +07:00
|
|
|
|
|
|
|
imxdi->rtc->ops = &dryice_rtc_ops;
|
|
|
|
imxdi->rtc->range_max = U32_MAX;
|
|
|
|
|
|
|
|
rc = rtc_register_device(imxdi->rtc);
|
|
|
|
if (rc)
|
2010-08-11 08:02:13 +07:00
|
|
|
goto err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
2012-04-25 21:35:16 +07:00
|
|
|
clk_disable_unprepare(imxdi->clk);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2013-04-30 06:18:24 +07:00
|
|
|
static int __exit dryice_rtc_remove(struct platform_device *pdev)
|
2010-08-11 08:02:13 +07:00
|
|
|
{
|
|
|
|
struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
flush_work(&imxdi->work);
|
|
|
|
|
|
|
|
/* mask all interrupts */
|
2015-04-27 20:59:47 +07:00
|
|
|
writel(0, imxdi->ioaddr + DIER);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
2012-04-25 21:35:16 +07:00
|
|
|
clk_disable_unprepare(imxdi->clk);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-18 07:02:23 +07:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
static const struct of_device_id dryice_dt_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx25-rtc" },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, dryice_dt_ids);
|
|
|
|
#endif
|
|
|
|
|
2010-08-11 08:02:13 +07:00
|
|
|
static struct platform_driver dryice_rtc_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "imxdi_rtc",
|
2012-12-18 07:02:23 +07:00
|
|
|
.of_match_table = of_match_ptr(dryice_dt_ids),
|
2010-08-11 08:02:13 +07:00
|
|
|
},
|
2013-04-30 06:18:24 +07:00
|
|
|
.remove = __exit_p(dryice_rtc_remove),
|
2010-08-11 08:02:13 +07:00
|
|
|
};
|
|
|
|
|
2013-04-30 06:18:42 +07:00
|
|
|
module_platform_driver_probe(dryice_rtc_driver, dryice_rtc_probe);
|
2010-08-11 08:02:13 +07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
|
|
|
|
MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
|
|
|
|
MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
|
|
|
|
MODULE_LICENSE("GPL");
|